DE69024078T2 - Mehrprozessoranordnung mit Vervielfältigung von globalen Daten und mit zwei Stufen von Adressübersetzungseinheiten - Google Patents

Mehrprozessoranordnung mit Vervielfältigung von globalen Daten und mit zwei Stufen von Adressübersetzungseinheiten

Info

Publication number
DE69024078T2
DE69024078T2 DE69024078T DE69024078T DE69024078T2 DE 69024078 T2 DE69024078 T2 DE 69024078T2 DE 69024078 T DE69024078 T DE 69024078T DE 69024078 T DE69024078 T DE 69024078T DE 69024078 T2 DE69024078 T2 DE 69024078T2
Authority
DE
Germany
Prior art keywords
duplication
stages
address translation
global data
processor arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69024078T
Other languages
English (en)
Other versions
DE69024078D1 (de
Inventor
Angelo Casamatta
Calogero Mantellina
Daniele Zanzottera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Italia SpA, Bull HN Information Systems Inc filed Critical Bull HN Information Systems Italia SpA
Publication of DE69024078D1 publication Critical patent/DE69024078D1/de
Application granted granted Critical
Publication of DE69024078T2 publication Critical patent/DE69024078T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0692—Multiconfiguration, e.g. local and global addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
DE69024078T 1989-03-15 1990-03-03 Mehrprozessoranordnung mit Vervielfältigung von globalen Daten und mit zwei Stufen von Adressübersetzungseinheiten Expired - Fee Related DE69024078T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8919787A IT1228728B (it) 1989-03-15 1989-03-15 Sistema multiprocessore con replicazione di dati globali e due livelli di unita' di traduzione indirizzi.

Publications (2)

Publication Number Publication Date
DE69024078D1 DE69024078D1 (de) 1996-01-25
DE69024078T2 true DE69024078T2 (de) 1996-05-15

Family

ID=11161211

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69024078T Expired - Fee Related DE69024078T2 (de) 1989-03-15 1990-03-03 Mehrprozessoranordnung mit Vervielfältigung von globalen Daten und mit zwei Stufen von Adressübersetzungseinheiten

Country Status (5)

Country Link
US (1) US5247629A (de)
EP (1) EP0387644B1 (de)
JP (1) JPH02291044A (de)
DE (1) DE69024078T2 (de)
IT (1) IT1228728B (de)

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JP2826028B2 (ja) * 1993-01-28 1998-11-18 富士通株式会社 分散メモリ型プロセッサシステム
US5463750A (en) * 1993-11-02 1995-10-31 Intergraph Corporation Method and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLB's
US5649102A (en) * 1993-11-26 1997-07-15 Hitachi, Ltd. Distributed shared data management system for controlling structured shared data and for serializing access to shared data
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JP3687990B2 (ja) * 1994-01-25 2005-08-24 株式会社日立製作所 メモリアクセス機構
SE515344C2 (sv) * 1994-02-08 2001-07-16 Ericsson Telefon Ab L M Distribuerat databassystem
JP2625385B2 (ja) * 1994-06-30 1997-07-02 日本電気株式会社 マルチプロセッサシステム
US5696949A (en) * 1995-06-15 1997-12-09 Intel Corporation System for PCI slots expansion using asynchronous PCI-to-PCI bridge with clock generator for providing clock signal to the expansion mother board and expansion side of bridge
US5924125A (en) * 1995-08-01 1999-07-13 Arya; Siamak Method and apparatus for parallel access to consecutive TLB entries
US6101590A (en) * 1995-10-10 2000-08-08 Micro Unity Systems Engineering, Inc. Virtual memory system with local and global virtual address translation
US5940870A (en) * 1996-05-21 1999-08-17 Industrial Technology Research Institute Address translation for shared-memory multiprocessor clustering
US5860146A (en) * 1996-06-25 1999-01-12 Sun Microsystems, Inc. Auxiliary translation lookaside buffer for assisting in accessing data in remote address spaces
US5897664A (en) * 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies
US5862357A (en) 1996-07-02 1999-01-19 Sun Microsystems, Inc. Hierarchical SMP computer system
US5774648A (en) * 1996-10-02 1998-06-30 Mitsubishi Semiconductor Of America, Inc. Address generator for error control system
US5860116A (en) * 1996-12-11 1999-01-12 Ncr Corporation Memory page location control for multiple memory-multiple processor system
US5918249A (en) * 1996-12-19 1999-06-29 Ncr Corporation Promoting local memory accessing and data migration in non-uniform memory access system architectures
US6766472B2 (en) 2000-09-22 2004-07-20 Microsoft Corporation Systems and methods for replicating virtual memory on a host computer and debugging using the replicated memory
US20020161452A1 (en) * 2001-04-25 2002-10-31 Peltier Michael G. Hierarchical collective memory architecture for multiple processors and method therefor
EP1522923A3 (de) * 2003-10-08 2011-06-22 STMicroelectronics SA Architektur eines simultanen Multithreadprozessors (SMT)
US7290112B2 (en) * 2004-09-30 2007-10-30 International Business Machines Corporation System and method for virtualization of processor resources
US7551617B2 (en) * 2005-02-08 2009-06-23 Cisco Technology, Inc. Multi-threaded packet processing architecture with global packet memory, packet recirculation, and coprocessor
US7739426B1 (en) 2005-10-31 2010-06-15 Cisco Technology, Inc. Descriptor transfer logic
US7487341B2 (en) * 2006-06-29 2009-02-03 Intel Corporation Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource
US7685399B2 (en) * 2007-01-07 2010-03-23 International Business Machines Corporation Method, system, and computer program products for data movement within processor storage
US8719547B2 (en) 2009-09-18 2014-05-06 Intel Corporation Providing hardware support for shared virtual memory between local and remote physical memory
CN102110072B (zh) * 2009-12-29 2013-06-05 中兴通讯股份有限公司 一种多处理器完全互访的方法及系统
US8850557B2 (en) 2012-02-29 2014-09-30 International Business Machines Corporation Processor and data processing method with non-hierarchical computer security enhancements for context states
US20130197863A1 (en) * 2012-01-31 2013-08-01 Tata Consultancy Services Limited Performance and capacity analysis of computing systems

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US5072369A (en) * 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates

Also Published As

Publication number Publication date
DE69024078D1 (de) 1996-01-25
US5247629A (en) 1993-09-21
EP0387644A1 (de) 1990-09-19
IT1228728B (it) 1991-07-03
EP0387644B1 (de) 1995-12-13
JPH02291044A (ja) 1990-11-30
IT8919787A0 (it) 1989-03-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee