DE69013254D1 - Halbleiter-IC-Bauelement mit verbesserter Interkonnektionsstruktur. - Google Patents

Halbleiter-IC-Bauelement mit verbesserter Interkonnektionsstruktur.

Info

Publication number
DE69013254D1
DE69013254D1 DE69013254T DE69013254T DE69013254D1 DE 69013254 D1 DE69013254 D1 DE 69013254D1 DE 69013254 T DE69013254 T DE 69013254T DE 69013254 T DE69013254 T DE 69013254T DE 69013254 D1 DE69013254 D1 DE 69013254D1
Authority
DE
Germany
Prior art keywords
semiconductor
component
interconnection structure
improved interconnection
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69013254T
Other languages
English (en)
Other versions
DE69013254T2 (de
Inventor
Hiroshi Ishioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69013254D1 publication Critical patent/DE69013254D1/de
Application granted granted Critical
Publication of DE69013254T2 publication Critical patent/DE69013254T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
DE69013254T 1989-07-19 1990-07-17 Halbleiter-IC-Bauelement mit verbesserter Interkonnektionsstruktur. Expired - Lifetime DE69013254T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1186600A JPH088330B2 (ja) 1989-07-19 1989-07-19 Ｌｏｃ型リードフレームを備えた半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69013254D1 true DE69013254D1 (de) 1994-11-17
DE69013254T2 DE69013254T2 (de) 1995-05-24

Family

ID=16191400

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69013254T Expired - Lifetime DE69013254T2 (de) 1989-07-19 1990-07-17 Halbleiter-IC-Bauelement mit verbesserter Interkonnektionsstruktur.

Country Status (4)

Country Link
US (1) US5089876A (de)
EP (1) EP0409173B1 (de)
JP (1) JPH088330B2 (de)
DE (1) DE69013254T2 (de)

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KR0158868B1 (ko) * 1988-09-20 1998-12-01 미다 가쓰시게 반도체장치
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads
WO1992003035A1 (en) * 1990-08-01 1992-02-20 Staktek Corporation Ultra high density integrated circuit packages, method and apparatus
US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5367766A (en) * 1990-08-01 1994-11-29 Staktek Corporation Ultra high density integrated circuit packages method
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
JP3011510B2 (ja) * 1990-12-20 2000-02-21 株式会社東芝 相互連結回路基板を有する半導体装置およびその製造方法
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5448450A (en) * 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
JP2634978B2 (ja) * 1991-08-29 1997-07-30 川崎製鉄株式会社 保護素子付リードフレーム
JPH05226559A (ja) * 1991-10-11 1993-09-03 Hitachi Cable Ltd 樹脂封止型半導体装置
KR940006187Y1 (ko) * 1991-10-15 1994-09-10 금성일렉트론 주식회사 반도체장치
KR100276781B1 (ko) * 1992-02-03 2001-01-15 비센트 비. 인그라시아 리드-온-칩 반도체장치 및 그 제조방법
JPH05218281A (ja) * 1992-02-07 1993-08-27 Texas Instr Japan Ltd 半導体装置
EP0576708A1 (de) * 1992-07-01 1994-01-05 Siemens Aktiengesellschaft Integrierter Schaltkreis mit Leiterrahmen
US5334802A (en) * 1992-09-02 1994-08-02 Texas Instruments Incorporated Method and configuration for reducing electrical noise in integrated circuit devices
KR940008066A (ko) * 1992-09-18 1994-04-28 윌리엄 이. 힐러 집적 회로용 다중층 리드 프레임 어셈블리 및 방법
US5311057A (en) * 1992-11-27 1994-05-10 Motorola Inc. Lead-on-chip semiconductor device and method for making the same
US5302849A (en) * 1993-03-01 1994-04-12 Motorola, Inc. Plastic and grid array semiconductor device and method for making the same
US5399902A (en) * 1993-03-04 1995-03-21 International Business Machines Corporation Semiconductor chip packaging structure including a ground plane
US5369056A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
JP2856642B2 (ja) * 1993-07-16 1999-02-10 株式会社東芝 半導体装置及びその製造方法
US5700715A (en) * 1994-06-14 1997-12-23 Lsi Logic Corporation Process for mounting a semiconductor device to a circuit substrate
US5545912A (en) * 1994-10-27 1996-08-13 Motorola, Inc. Electronic device enclosure including a conductive cap and substrate
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
US5872398A (en) * 1996-01-11 1999-02-16 Micron Technology, Inc. Reduced stress LOC assembly including cantilevered leads
US5945732A (en) 1997-03-12 1999-08-31 Staktek Corporation Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package
DE19835393A1 (de) * 1998-08-05 1999-11-04 Siemens Ag Bauelement mit wenigstens einer integrierten elektronischen Schaltung und Verfahren zur Herstellung des Bauelementes
EP2568496A3 (de) 2011-09-09 2017-12-06 Assa Abloy Ab Verfahren und Vorrichtung zur Aufrechterhaltung der Betriebstemperatur einer integrierten Schaltung
US8629539B2 (en) 2012-01-16 2014-01-14 Allegro Microsystems, Llc Methods and apparatus for magnetic sensor having non-conductive die paddle
US9666788B2 (en) * 2012-03-20 2017-05-30 Allegro Microsystems, Llc Integrated circuit package having a split lead frame
US10234513B2 (en) 2012-03-20 2019-03-19 Allegro Microsystems, Llc Magnetic field sensor integrated circuit with integral ferromagnetic material
US9494660B2 (en) 2012-03-20 2016-11-15 Allegro Microsystems, Llc Integrated circuit package having a split lead frame
US9812588B2 (en) 2012-03-20 2017-11-07 Allegro Microsystems, Llc Magnetic field sensor integrated circuit with integral ferromagnetic material
US9411025B2 (en) 2013-04-26 2016-08-09 Allegro Microsystems, Llc Integrated circuit package having a split lead frame and a magnet
US10921391B2 (en) 2018-08-06 2021-02-16 Allegro Microsystems, Llc Magnetic field sensor with spacer
US10991644B2 (en) 2019-08-22 2021-04-27 Allegro Microsystems, Llc Integrated circuit package having a low profile

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US4534105A (en) * 1983-08-10 1985-08-13 Rca Corporation Method for grounding a pellet support pad in an integrated circuit device
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JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
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US4801999A (en) * 1987-07-15 1989-01-31 Advanced Micro Devices, Inc. Integrated circuit lead frame assembly containing voltage bussing and distribution to an integrated circuit die using tape automated bonding with two metal layers
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Also Published As

Publication number Publication date
EP0409173A3 (en) 1991-07-24
EP0409173A2 (de) 1991-01-23
US5089876A (en) 1992-02-18
JPH0350859A (ja) 1991-03-05
JPH088330B2 (ja) 1996-01-29
EP0409173B1 (de) 1994-10-12
DE69013254T2 (de) 1995-05-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP