DE68929224D1 - Pipeline, die einen Cachespeicher für Rechnerprozessoren enthält - Google Patents

Pipeline, die einen Cachespeicher für Rechnerprozessoren enthält

Info

Publication number
DE68929224D1
DE68929224D1 DE68929224T DE68929224T DE68929224D1 DE 68929224 D1 DE68929224 D1 DE 68929224D1 DE 68929224 T DE68929224 T DE 68929224T DE 68929224 T DE68929224 T DE 68929224T DE 68929224 D1 DE68929224 D1 DE 68929224D1
Authority
DE
Germany
Prior art keywords
pipeline
cache memory
data
computer processors
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68929224T
Other languages
English (en)
Other versions
DE68929224T2 (de
Inventor
Richard T Witek
Douglas D Williams
Timothy J Stanley
David M Fenwick
Douglas J Burns
Rebecca L Stamm
Richard Heye
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE68929224D1 publication Critical patent/DE68929224D1/de
Publication of DE68929224T2 publication Critical patent/DE68929224T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8061—Details on data memory access
    • G06F15/8069—Details on data memory access using a cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G06F15/8076—Details on data register access
    • G06F15/8084—Special arrangements thereof, e.g. mask or switch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
DE68929224T 1988-07-25 1989-07-20 Pipeline, die einen Cachespeicher für Rechnerprozessoren enthält Expired - Fee Related DE68929224T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/224,483 US5148536A (en) 1988-07-25 1988-07-25 Pipeline having an integral cache which processes cache misses and loads data in parallel

Publications (2)

Publication Number Publication Date
DE68929224D1 true DE68929224D1 (de) 2000-07-20
DE68929224T2 DE68929224T2 (de) 2001-02-22

Family

ID=22840901

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68929224T Expired - Fee Related DE68929224T2 (de) 1988-07-25 1989-07-20 Pipeline, die einen Cachespeicher für Rechnerprozessoren enthält

Country Status (6)

Country Link
US (2) US5148536A (de)
EP (1) EP0352633B1 (de)
JP (1) JPH0290265A (de)
KR (1) KR920004289B1 (de)
AT (1) ATE193949T1 (de)
DE (1) DE68929224T2 (de)

Families Citing this family (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535359A (en) * 1988-12-02 1996-07-09 Mitsubishi Denki Kabushiki Kaisha Computer system with cache memory having address mask register
JPH0666056B2 (ja) * 1989-10-12 1994-08-24 甲府日本電気株式会社 情報処理システム
US5317718A (en) * 1990-03-27 1994-05-31 Digital Equipment Corporation Data processing system and method with prefetch buffers
JP2862948B2 (ja) * 1990-04-13 1999-03-03 三菱電機株式会社 半導体記憶装置
US5838946A (en) * 1990-04-14 1998-11-17 Sun Microsystems, Inc. Method and apparatus for accomplishing processor read of selected information through a cache memory
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
US5724548A (en) * 1990-09-18 1998-03-03 Fujitsu Limited System including processor and cache memory and method of controlling the cache memory
JP2677706B2 (ja) * 1990-10-19 1997-11-17 富士通株式会社 メモリアクセス制御回路
JP2678527B2 (ja) * 1991-01-08 1997-11-17 三菱電機株式会社 キャッシュメモリ装置
US5265233A (en) * 1991-05-17 1993-11-23 Sun Microsystems, Inc. Method and apparatus for providing total and partial store ordering for a memory in multi-processor system
JP2625277B2 (ja) * 1991-05-20 1997-07-02 富士通株式会社 メモリアクセス装置
JPH079632B2 (ja) * 1991-06-18 1995-02-01 インターナショナル・ビジネス・マシーンズ・コーポレイション アドレス変換装置および方法
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5386526A (en) * 1991-10-18 1995-01-31 Sun Microsystems, Inc. Cache memory controller and method for reducing CPU idle time by fetching data during a cache fill
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5398330A (en) * 1992-03-05 1995-03-14 Seiko Epson Corporation Register file backup queue
JP3730252B2 (ja) 1992-03-31 2005-12-21 トランスメタ コーポレイション レジスタ名称変更方法及び名称変更システム
WO1993022722A1 (en) * 1992-05-01 1993-11-11 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
US5398325A (en) * 1992-05-07 1995-03-14 Sun Microsystems, Inc. Methods and apparatus for improving cache consistency using a single copy of a cache tag memory in multiple processor computer systems
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
JP3644959B2 (ja) * 1992-09-29 2005-05-11 セイコーエプソン株式会社 マイクロプロセッサシステム
US5388226A (en) * 1992-10-05 1995-02-07 Motorola, Inc. Method and apparatus for accessing a register in a data processing system
US5572714A (en) * 1992-10-23 1996-11-05 Matsushita Electric Industrial Co., Ltd. Integrated circuit for pipeline data processing
EP1107111A3 (de) 1992-12-31 2002-02-06 Seiko Epson Corporation System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
JP3230898B2 (ja) * 1993-06-02 2001-11-19 シャープ株式会社 データ駆動型情報処理システム
US5553270A (en) * 1993-09-01 1996-09-03 Digital Equipment Corporation Apparatus for providing improved memory access in page mode access systems with pipelined cache access and main memory address replay
US6128721A (en) * 1993-11-17 2000-10-03 Sun Microsystems, Inc. Temporary pipeline register file for a superpipelined superscalar processor
US5996062A (en) * 1993-11-24 1999-11-30 Intergraph Corporation Method and apparatus for controlling an instruction pipeline in a data processing system
US5671444A (en) * 1994-02-28 1997-09-23 Intel Corporaiton Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers
EP0676690B1 (de) * 1994-03-09 2003-05-14 Sun Microsystems, Inc. Verzögertes Cachespeicherschreiben eines Speicherungsbefehls
US6021471A (en) * 1994-11-15 2000-02-01 Advanced Micro Devices, Inc. Multiple level cache control system with address and data pipelines
GB2307072B (en) 1994-06-10 1998-05-13 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
US5787465A (en) * 1994-07-01 1998-07-28 Digital Equipment Corporation Destination indexed miss status holding registers
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
US5701433A (en) * 1994-10-14 1997-12-23 Compaq Computer Corporation Computer system having a memory controller which performs readahead operations which can be aborted prior to completion
US5548728A (en) * 1994-11-04 1996-08-20 Canon Information Systems, Inc. System for reducing bus contention using counter of outstanding acknowledgement in sending processor and issuing of acknowledgement signal by receiving processor to indicate available space in shared memory
US5699538A (en) * 1994-12-09 1997-12-16 International Business Machines Corporation Efficient firm consistency support mechanisms in an out-of-order execution superscaler multiprocessor
US5680338A (en) * 1995-01-04 1997-10-21 International Business Machines Corporation Method and system for vector processing utilizing selected vector elements
US5887183A (en) * 1995-01-04 1999-03-23 International Business Machines Corporation Method and system in a data processing system for loading and storing vectors in a plurality of modes
US5832533A (en) * 1995-01-04 1998-11-03 International Business Machines Corporation Method and system for addressing registers in a data processing unit in an indexed addressing mode
US5890222A (en) * 1995-01-04 1999-03-30 International Business Machines Corporation Method and system for addressing registers in a data processing unit in an indirect addressing mode
JP3569811B2 (ja) * 1995-01-25 2004-09-29 株式会社ルネサステクノロジ パイプライン処理機能を有するデータ処理装置
US5687350A (en) * 1995-02-10 1997-11-11 International Business Machines Corporation Protocol and system for performing line-fill address during copy-back operation
JPH0934786A (ja) * 1995-07-14 1997-02-07 Fujitsu Ltd 命令供給装置
US5924125A (en) * 1995-08-01 1999-07-13 Arya; Siamak Method and apparatus for parallel access to consecutive TLB entries
US6076150A (en) * 1995-08-10 2000-06-13 Lsi Logic Corporation Cache controller with improved instruction and data forwarding during refill operation
US5767856A (en) * 1995-08-22 1998-06-16 Rendition, Inc. Pixel engine pipeline for a 3D graphics accelerator
US6101590A (en) 1995-10-10 2000-08-08 Micro Unity Systems Engineering, Inc. Virtual memory system with local and global virtual address translation
US5809530A (en) * 1995-11-13 1998-09-15 Motorola, Inc. Method and apparatus for processing multiple cache misses using reload folding and store merging
US5848287A (en) 1996-02-20 1998-12-08 Advanced Micro Devices, Inc. Superscalar microprocessor including a reorder buffer which detects dependencies between accesses to a pair of caches
US5761720A (en) * 1996-03-15 1998-06-02 Rendition, Inc. Pixel engine pipeline processor data caching mechanism
DE29608748U1 (de) 1996-05-14 1996-08-01 Storck Markus Fahrradkurbel
US5652774A (en) * 1996-07-08 1997-07-29 International Business Machines Corporation Method and apparatus for decreasing the cycle times of a data processing system
US5802564A (en) * 1996-07-08 1998-09-01 International Business Machines Corp. Method and apparatus for increasing processor performance
US6209020B1 (en) * 1996-09-20 2001-03-27 Nortel Networks Limited Distributed pipeline memory architecture for a computer system with even and odd pids
US6088788A (en) * 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
US6085292A (en) * 1997-06-05 2000-07-04 Digital Equipment Corporation Apparatus and method for providing non-blocking pipelined cache
US7197625B1 (en) * 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US6105051A (en) * 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6076157A (en) * 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6567839B1 (en) 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6697935B1 (en) 1997-10-23 2004-02-24 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US6061710A (en) * 1997-10-29 2000-05-09 International Business Machines Corporation Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
US6256775B1 (en) 1997-12-11 2001-07-03 International Business Machines Corporation Facilities for detailed software performance analysis in a multithreaded processor
US6018759A (en) * 1997-12-22 2000-01-25 International Business Machines Corporation Thread switch tuning tool for optimal performance in a computer processor
US6148372A (en) * 1998-01-21 2000-11-14 Sun Microsystems, Inc. Apparatus and method for detection and recovery from structural stalls in a multi-level non-blocking cache system
US6226713B1 (en) 1998-01-21 2001-05-01 Sun Microsystems, Inc. Apparatus and method for queueing structures in a multi-level non-blocking cache subsystem
US6012134A (en) * 1998-04-09 2000-01-04 Institute For The Development Of Emerging Architectures, L.L.C. High-performance processor with streaming buffer that facilitates prefetching of instructions
US6438650B1 (en) * 1998-12-16 2002-08-20 Intel Corporation Method and apparatus for processing cache misses
US6437789B1 (en) 1999-02-19 2002-08-20 Evans & Sutherland Computer Corporation Multi-level cache controller
US6237066B1 (en) 1999-03-22 2001-05-22 Sun Microsystems, Inc. Supporting multiple outstanding requests to multiple targets in a pipelined memory system
US20020108022A1 (en) * 1999-04-28 2002-08-08 Hong-Yi Hubert Chen System and method for allowing back to back write operations in a processing system utilizing a single port cache
US6651164B1 (en) * 1999-10-14 2003-11-18 Hewlett-Packard Development Company, L.P. System and method for detecting an erroneous data hazard between instructions of an instruction group and resulting from a compiler grouping error
US6327645B1 (en) * 1999-11-08 2001-12-04 Silicon Integrated Systems Corp. Cache memory system with memory request address queue, cache write address queue, and cache read address queue
US7062523B1 (en) * 2000-08-01 2006-06-13 Analog Devices, Inc. Method for efficiently computing a fast fourier transform
US20020080655A1 (en) * 2000-12-27 2002-06-27 Clark Lawrence T. Integrated circuit having synchronized pipelining and method therefor
US7310706B1 (en) * 2001-06-01 2007-12-18 Mips Technologies, Inc. Random cache line refill
US7673164B1 (en) 2004-12-13 2010-03-02 Massachusetts Institute Of Technology Managing power in a parallel processing environment
US7437537B2 (en) * 2005-02-17 2008-10-14 Qualcomm Incorporated Methods and apparatus for predicting unaligned memory access
US7447868B2 (en) * 2005-06-15 2008-11-04 International Business Machines Corporation Using vector processors to accelerate cache lookups
US20080282034A1 (en) * 2005-09-19 2008-11-13 Via Technologies, Inc. Memory Subsystem having a Multipurpose Cache for a Stream Graphics Multiprocessor
US20070067572A1 (en) * 2005-09-19 2007-03-22 Via Technologies, Inc. Buffering missed requests in processor caches
US20070180156A1 (en) * 2006-02-01 2007-08-02 International Business Machines Corporation Method for completing IO commands after an IO translation miss
US7882307B1 (en) 2006-04-14 2011-02-01 Tilera Corporation Managing cache memory in a parallel processing environment
US7853755B1 (en) 2006-09-29 2010-12-14 Tilera Corporation Caching in multicore and multiprocessor architectures
EP2104930A2 (de) 2006-12-12 2009-09-30 Evans & Sutherland Computer Corporation System und methode zum ausgleichen des rgb-licht in einem monomodulator projektor
US8358317B2 (en) 2008-05-23 2013-01-22 Evans & Sutherland Computer Corporation System and method for displaying a planar image on a curved surface
US8702248B1 (en) 2008-06-11 2014-04-22 Evans & Sutherland Computer Corporation Projection method for reducing interpixel gaps on a viewing surface
US8077378B1 (en) 2008-11-12 2011-12-13 Evans & Sutherland Computer Corporation Calibration system and method for light modulation device
US9641826B1 (en) 2011-10-06 2017-05-02 Evans & Sutherland Computer Corporation System and method for displaying distant 3-D stereo on a dome surface
KR102238650B1 (ko) * 2014-04-30 2021-04-09 삼성전자주식회사 저장 장치, 상기 저장 장치를 포함하는 컴퓨팅 시스템 및 상기 저장 장치의 동작 방법

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092713A (en) * 1977-06-13 1978-05-30 Sperry Rand Corporation Post-write address word correction in cache memory system
US4354232A (en) * 1977-12-16 1982-10-12 Honeywell Information Systems Inc. Cache memory command buffer circuit
US4349871A (en) * 1980-01-28 1982-09-14 Digital Equipment Corporation Duplicate tag store for cached multiprocessor system
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4370710A (en) * 1980-08-26 1983-01-25 Control Data Corporation Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
JPS58133696A (ja) * 1982-02-03 1983-08-09 Hitachi Ltd 記憶制御方式
JPS58149541A (ja) * 1982-03-01 1983-09-05 Hitachi Ltd デ−タ処理装置
US4494190A (en) * 1982-05-12 1985-01-15 Honeywell Information Systems Inc. FIFO buffer to cache memory
US4594682A (en) * 1982-12-22 1986-06-10 Ibm Corporation Vector processing
US4594655A (en) * 1983-03-14 1986-06-10 International Business Machines Corporation (k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache
JPS60134974A (ja) * 1983-12-23 1985-07-18 Hitachi Ltd ベクトル処理装置
JPH0644245B2 (ja) * 1983-12-29 1994-06-08 富士通株式会社 ストアバッファ装置
US4701844A (en) * 1984-03-30 1987-10-20 Motorola Computer Systems, Inc. Dual cache for independent prefetch and execution units
US4646233A (en) * 1984-06-20 1987-02-24 Weatherford James R Physical cache unit for computer
US4620275A (en) * 1984-06-20 1986-10-28 Wallach Steven J Computer system
US4695943A (en) * 1984-09-27 1987-09-22 Honeywell Information Systems Inc. Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization
EP0192578A3 (de) * 1985-02-22 1990-04-25 Intergraph Corporation Mehrbusanordnung mit einem Mikroprozessor mit getrennten Befehls- und Datenschnittstellen und Cachespeichern
US4860192A (en) * 1985-02-22 1989-08-22 Intergraph Corporation Quadword boundary cache system
US4884197A (en) * 1985-02-22 1989-11-28 Intergraph Corporation Method and apparatus for addressing a cache memory
US4722049A (en) * 1985-10-11 1988-01-26 Unisys Corporation Apparatus for out-of-order program execution
US4855904A (en) * 1986-08-27 1989-08-08 Amdahl Corporation Cache storage queue
US4933837A (en) * 1986-12-01 1990-06-12 Advanced Micro Devices, Inc. Methods and apparatus for optimizing instruction processing in computer systems employing a combination of instruction cache and high speed consecutive transfer memories
US4811215A (en) * 1986-12-12 1989-03-07 Intergraph Corporation Instruction execution accelerator for a pipelined digital machine with virtual memory
US4858113A (en) * 1987-04-10 1989-08-15 The United States Of America As Represented By The Director Of The National Security Agency Reconfigurable pipelined processor
US4920477A (en) * 1987-04-20 1990-04-24 Multiflow Computer, Inc. Virtual address table look aside buffer miss recovery method and apparatus
DE3782335T2 (de) * 1987-04-22 1993-05-06 Ibm Speichersteuersystem.
US4926317A (en) * 1987-07-24 1990-05-15 Convex Computer Corporation Hierarchical memory system with logical cache, physical cache, and address translation unit for generating a sequence of physical addresses

Also Published As

Publication number Publication date
US5430888A (en) 1995-07-04
US5148536A (en) 1992-09-15
DE68929224T2 (de) 2001-02-22
EP0352633A3 (de) 1991-04-17
ATE193949T1 (de) 2000-06-15
KR900002180A (ko) 1990-02-28
EP0352633A2 (de) 1990-01-31
JPH0290265A (ja) 1990-03-29
KR920004289B1 (ko) 1992-06-01
EP0352633B1 (de) 2000-06-14

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Free format text: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, 80538 MUENCHEN

8339 Ceased/non-payment of the annual fee