DE68907089T2 - Leiterplatten mit niedriger Dielektrizitätskonstante. - Google Patents

Leiterplatten mit niedriger Dielektrizitätskonstante.

Info

Publication number: DE68907089T2
Authority: DE; Germany
Prior art keywords: printed circuit; dielectric constant; circuit boards; low dielectric; boards
Prior art date: 1988-03-16
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE89101910T

Other languages

English (en)

Other versions

DE68907089D1 (de

Inventor

Donald Joseph Lazzarini

John Pennock Wiley

Robert Taylor Wiley

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

International Business Machines Corp

Original Assignee

International Business Machines Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1988-03-16

Filing date

1989-02-03

Publication date

1993-12-02

1989-02-03 Application filed by International Business Machines Corp filed Critical International Business Machines Corp

1993-07-22 Publication of DE68907089D1 publication Critical patent/DE68907089D1/de

1993-12-02 Application granted granted Critical

1993-12-02 Publication of DE68907089T2 publication Critical patent/DE68907089T2/de

2009-02-04 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/015—Fluoropolymer, e.g. polytetrafluoroethylene [PTFE]
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/061—Lamination of previously made multilayered subassemblies
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases

DE89101910T 1988-03-16 1989-02-03 Leiterplatten mit niedriger Dielektrizitätskonstante. Expired - Fee Related DE68907089T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US07/168,928 US4864722A (en)	1988-03-16	1988-03-16	Low dielectric printed circuit boards

Publications (2)

Publication Number	Publication Date
DE68907089D1 DE68907089D1 (de)	1993-07-22
DE68907089T2 true DE68907089T2 (de)	1993-12-02

Family

ID=22613539

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE89101910T Expired - Fee Related DE68907089T2 (de)	1988-03-16	1989-02-03	Leiterplatten mit niedriger Dielektrizitätskonstante.

Country Status (4)

Country	Link
US (1)	US4864722A (de)
EP (1)	EP0332834B1 (de)
JP (1)	JPH0666551B2 (de)
DE (1)	DE68907089T2 (de)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPH03150895A (ja) *	1989-11-08	1991-06-27	Hitachi Ltd	多層回路基板及びその製造方法
US5157477A (en) *	1990-01-10	1992-10-20	International Business Machines Corporation	Matched impedance vertical conductors in multilevel dielectric laminated wiring
US5032803A (en) *	1990-02-02	1991-07-16	American Telephone & Telegraph Company	Directional stripline structure and manufacture
US5948533A (en) *	1990-02-09	1999-09-07	Ormet Corporation	Vertically interconnected electronic assemblies and compositions useful therefor
US5039965A (en) *	1990-08-24	1991-08-13	Motorola, Inc.	Radio frequency filter feedthrough structure for multilayer circuit boards
US5142775A (en) *	1990-10-30	1992-09-01	International Business Machines Corporation	Bondable via
US5129142A (en) *	1990-10-30	1992-07-14	International Business Machines Corporation	Encapsulated circuitized power core alignment and lamination
JP2874329B2 (ja) *	1990-11-05	1999-03-24	日本電気株式会社	多層印刷配線板の製造方法
DE69210329T2 (de) *	1991-07-25	1996-11-28	Ncr Int Inc	Mehrschichtiger Träger für integrierte Schaltungen und Verfahren zu dessen Herstellung
US5276955A (en) *	1992-04-14	1994-01-11	Supercomputer Systems Limited Partnership	Multilayer interconnect system for an area array interconnection using solid state diffusion
US5245135A (en) *	1992-04-20	1993-09-14	Hughes Aircraft Company	Stackable high density interconnection mechanism (SHIM)
US5309629A (en) *	1992-09-01	1994-05-10	Rogers Corporation	Method of manufacturing a multilayer circuit board
JP3083416B2 (ja) *	1992-11-06	2000-09-04	進工業株式会社	ディレイライン素子およびその製造方法
US5316803A (en) *	1992-12-10	1994-05-31	International Business Machines Corporation	Method for forming electrical interconnections in laminated vias
US5418689A (en) *	1993-02-01	1995-05-23	International Business Machines Corporation	Printed circuit board or card for direct chip attachment and fabrication thereof
US5401913A (en) *	1993-06-08	1995-03-28	Minnesota Mining And Manufacturing Company	Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board
US5773195A (en) *	1994-12-01	1998-06-30	International Business Machines Corporation	Cap providing flat surface for DCA and solder ball attach and for sealing plated through holes, multi-layer electronic structures including the cap, and a process of forming the cap and for forming multi-layer electronic structures including the cap
US6720501B1 (en) *	1998-04-14	2004-04-13	Formfactor, Inc.	PC board having clustered blind vias
US6834426B1 (en) *	2000-07-25	2004-12-28	International Business Machines Corporation	Method of fabricating a laminate circuit structure
KR100944695B1 (ko) *	2001-06-27	2010-02-26	신꼬오덴기 고교 가부시키가이샤	위치 정보를 갖는 배선 기판
JP3910387B2 (ja) *	2001-08-24	2007-04-25	新光電気工業株式会社	半導体パッケージ及びその製造方法並びに半導体装置
JP4063533B2 (ja) *	2001-12-10	2008-03-19	日本碍子株式会社	フレキシブル配線板
US7038143B2 (en) *	2002-05-16	2006-05-02	Mitsubishi Denki Kabushiki Kaisha	Wiring board, fabrication method of wiring board, and semiconductor device
JP2005223127A (ja) *	2004-02-05	2005-08-18	Sharp Corp	平行導体板伝送路
US7270845B2 (en) *	2004-03-31	2007-09-18	Endicott Interconnect Technologies, Inc.	Dielectric composition for forming dielectric layer for use in circuitized substrates
US7145221B2 (en) *	2004-03-31	2006-12-05	Endicott Interconnect Technologies, Inc.	Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same
US7078816B2 (en) *	2004-03-31	2006-07-18	Endicott Interconnect Technologies, Inc.	Circuitized substrate
KR102125905B1 (ko) *	2013-04-25	2020-06-24	삼성디스플레이 주식회사	인쇄 회로 기판, 표시 장치 및 인쇄 회로 기판의 제조 방법
JP2015226034A (ja) *	2014-05-30	2015-12-14	京セラサーキットソリューションズ株式会社	配線基板
TWI526129B (zh) *	2014-11-05	2016-03-11	Elite Material Co Ltd	Multilayer printed circuit boards with dimensional stability
US9786976B2 (en)	2015-06-24	2017-10-10	Taiwan Semiconductor Manufacturing Company, Ltd.	Transmission line design and method, where high-k dielectric surrounds the transmission line for increased isolation
US10405421B2 (en) *	2017-12-18	2019-09-03	International Business Machines Corporation	Selective dielectric resin application on circuitized core layers

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
CA757597A (en) *	1963-12-30	1967-04-25	L. Mees John	Method for making printed circuits
US3740678A (en) *	1971-03-19	1973-06-19	Ibm	Strip transmission line structures
US3795047A (en) *	1972-06-15	1974-03-05	Ibm	Electrical interconnect structuring for laminate assemblies and fabricating methods therefor
US3972755A (en) *	1972-12-14	1976-08-03	The United States Of America As Represented By The Secretary Of The Navy	Dielectric circuit board bonding
JPS53124768A (en) *	1977-04-06	1978-10-31	Fujitsu Ltd	Method of producing multilayer printed board
JPS55133597A (en) *	1979-04-06	1980-10-17	Hitachi Ltd	Multilayer circuit board
JPS5658298A (en) *	1979-10-19	1981-05-21	Hitachi Ltd	Apparatus for preparing laminar layer for miltilayer printed circuit board
JPS57145397A (en) *	1981-03-04	1982-09-08	Hitachi Ltd	Method of producing multilayer printed circuit board
JPS58180094A (ja) *	1982-04-16	1983-10-21	株式会社日立製作所	多層プリント配線板の製造方法
US4591659A (en) *	1983-12-22	1986-05-27	Trw Inc.	Multilayer printed circuit board structure
JPS60214941A (ja) *	1984-04-10	1985-10-28	株式会社　潤工社	プリント基板
JPH0642515B2 (ja) *	1984-12-26	1994-06-01	株式会社東芝	回路基板
JPH023631Y2 (de) *	1984-12-28	1990-01-29
US4747897A (en) *	1985-02-26	1988-05-31	W. L. Gore & Associates, Inc.	Dielectric materials
JPS61220499A (ja) *	1985-03-27	1986-09-30	株式会社日立製作所	混成多層配線基板
US4661301A (en) *	1985-08-14	1987-04-28	Toray Industries, Inc.	Method for producing laminate board containing uniformly distributed filler particles
US4755783A (en) *	1986-11-18	1988-07-05	Rogers Corporation	Inductive devices for printed wiring boards
US4755911A (en) *	1987-04-28	1988-07-05	Junkosha Co., Ltd.	Multilayer printed circuit board

1988
- 1988-03-16 US US07/168,928 patent/US4864722A/en not_active Expired - Lifetime
1989
- 1989-02-03 DE DE89101910T patent/DE68907089T2/de not_active Expired - Fee Related
- 1989-02-03 EP EP89101910A patent/EP0332834B1/de not_active Expired - Lifetime
- 1989-02-06 JP JP1025966A patent/JPH0666551B2/ja not_active Expired - Fee Related

Also Published As

Publication number	Publication date
DE68907089D1 (de)	1993-07-22
US4864722A (en)	1989-09-12
EP0332834B1 (de)	1993-06-16
JPH01245594A (ja)	1989-09-29
JPH0666551B2 (ja)	1994-08-24
EP0332834A1 (de)	1989-09-20

Legal Events

Date	Code	Title	Description
1994-07-14	8364	No opposition during term of opposition
2005-12-15	8339	Ceased/non-payment of the annual fee

Publication	Publication Date	Title
DE68907089T2 (de)	1993-12-02	Leiterplatten mit niedriger Dielektrizitätskonstante.
DE68908687T2 (de)	1994-04-07	Gedruckte Schaltungsplatte.
DE3880385T2 (de)	1993-10-28	Gedruckte Leiterplatte.
DE69019030D1 (de)	1995-06-08	Gedruckte Leiterplatte.
DE69015878T2 (de)	1995-07-13	Mehrschichtleiterplattenstruktur.
DE3677937D1 (de)	1991-04-11	Modul mit zwei gedruckten schaltungsplatten.
DE68922118T2 (de)	1995-10-12	Schaltungsplatte.
DE3485957T2 (de)	1993-03-04	Gedruckte schaltungsplatte.
DE68910891D1 (de)	1994-01-05	Schaltungsplatine mit mehreren Computerschnittstellen.
DE3669431D1 (de)	1990-04-12	Gedruckte schaltungsplatte mit hoher dichte.
DE3881973T2 (de)	1993-10-14	Mehrschichtschaltungsplatte.
DE68916068D1 (de)	1994-07-21	Hochleistungsleiterplatten.
DE3873896T2 (de)	1993-02-04	Laminiermaterial fuer gedruckte schaltungsplatte mit niedriger dielektrizitaetskonstanten.
DE69020204D1 (de)	1995-07-27	Mehrschichtige gedruckte Leiterplatte.
KR900702760A (ko)	1990-12-08	인쇄회로기판
DE3771707D1 (de)	1991-08-29	Gedruckte leiterplatte.
DE3679627D1 (de)	1991-07-11	Mehrschichtige gedruckte schaltungsplatte.
DE3851118D1 (de)	1994-09-22	Leiterplatte.
DE68906160T2 (de)	1993-10-28	Gedruckte Schaltungsplatte.
DE3850626D1 (de)	1994-08-18	Leiterplatte.
DE3872865T2 (de)	1993-03-04	Gedruckte leiterkarte.
NO861792L (no)	1986-11-07	Styrekrets.
DE3784634T2 (de)	1993-07-15	Gedruckte schaltungsplatte.
DE69008944D1 (de)	1994-06-23	Gedruckte Schaltungsplatte.
DE68923099T2 (de)	1996-05-15	Überprüfung von Leiterplatten mit Mehrfachmustern.