DE60239052D1 - Monotone dynamische/statische pseudo-nmos logikschaltung und verfahren zur erzeugung eines logischen gatterfelds - Google Patents
Monotone dynamische/statische pseudo-nmos logikschaltung und verfahren zur erzeugung eines logischen gatterfeldsInfo
- Publication number
- DE60239052D1 DE60239052D1 DE60239052T DE60239052T DE60239052D1 DE 60239052 D1 DE60239052 D1 DE 60239052D1 DE 60239052 T DE60239052 T DE 60239052T DE 60239052 T DE60239052 T DE 60239052T DE 60239052 D1 DE60239052 D1 DE 60239052D1
- Authority
- DE
- Germany
- Prior art keywords
- dynamic
- monotone
- generating
- clock
- gate field
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003068 static effect Effects 0.000 title abstract 2
- 230000000295 complement effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/788,109 US6649476B2 (en) | 2001-02-15 | 2001-02-15 | Monotonic dynamic-static pseudo-NMOS logic circuit and method of forming a logic gate array |
| PCT/US2002/003512 WO2002071611A2 (en) | 2001-02-15 | 2002-02-07 | Monotonic dynamic-static pseudo-nmos logic circuit and method of forming a logic gate array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE60239052D1 true DE60239052D1 (de) | 2011-03-10 |
Family
ID=25143469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60239052T Expired - Lifetime DE60239052D1 (de) | 2001-02-15 | 2002-02-07 | Monotone dynamische/statische pseudo-nmos logikschaltung und verfahren zur erzeugung eines logischen gatterfelds |
Country Status (9)
| Country | Link |
|---|---|
| US (3) | US6649476B2 (de) |
| EP (1) | EP1378060B1 (de) |
| JP (1) | JP4036096B2 (de) |
| KR (1) | KR100581010B1 (de) |
| CN (2) | CN100464502C (de) |
| AT (1) | ATE497279T1 (de) |
| AU (1) | AU2002238056A1 (de) |
| DE (1) | DE60239052D1 (de) |
| WO (1) | WO2002071611A2 (de) |
Families Citing this family (52)
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| US6917221B2 (en) * | 2003-04-28 | 2005-07-12 | International Business Machines Corporation | Method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits |
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| US6987037B2 (en) * | 2003-05-07 | 2006-01-17 | Micron Technology, Inc. | Strained Si/SiGe structures by ion implantation |
| US7115480B2 (en) * | 2003-05-07 | 2006-10-03 | Micron Technology, Inc. | Micromechanical strained semiconductor by wafer bonding |
| US7501329B2 (en) | 2003-05-21 | 2009-03-10 | Micron Technology, Inc. | Wafer gettering using relaxed silicon germanium epitaxial proximity layers |
| US7662701B2 (en) | 2003-05-21 | 2010-02-16 | Micron Technology, Inc. | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
| US7439158B2 (en) | 2003-07-21 | 2008-10-21 | Micron Technology, Inc. | Strained semiconductor by full wafer bonding |
| US6929984B2 (en) | 2003-07-21 | 2005-08-16 | Micron Technology Inc. | Gettering using voids formed by surface transformation |
| US6969656B2 (en) * | 2003-12-05 | 2005-11-29 | Freescale Semiconductor, Inc. | Method and circuit for multiplying signals with a transistor having more than one independent gate structure |
| US7142478B2 (en) * | 2004-03-19 | 2006-11-28 | Infineon Technologies Ag | Clock stop detector |
| US7084667B2 (en) * | 2004-07-13 | 2006-08-01 | International Business Machines Corporation | Low leakage monotonic CMOS logic |
| US7518182B2 (en) | 2004-07-20 | 2009-04-14 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
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| US7285812B2 (en) * | 2004-09-02 | 2007-10-23 | Micron Technology, Inc. | Vertical transistors |
| US7199419B2 (en) * | 2004-12-13 | 2007-04-03 | Micron Technology, Inc. | Memory structure for reduced floating body effect |
| US7229895B2 (en) * | 2005-01-14 | 2007-06-12 | Micron Technology, Inc | Memory array buried digit line |
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| US20060176757A1 (en) * | 2005-02-09 | 2006-08-10 | International Business Machines Corporation | High performance CMOS NOR predecode circuit |
| US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
| US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
| US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
| US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
| US7439576B2 (en) * | 2005-08-29 | 2008-10-21 | Micron Technology, Inc. | Ultra-thin body vertical tunneling transistor |
| US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
| US7312626B2 (en) * | 2005-08-31 | 2007-12-25 | Micron Technology, Inc. | CMOS circuits with reduced crowbar current |
| US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
| US7446372B2 (en) * | 2005-09-01 | 2008-11-04 | Micron Technology, Inc. | DRAM tunneling access transistor |
| US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
| US7557032B2 (en) | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
| US7544584B2 (en) | 2006-02-16 | 2009-06-09 | Micron Technology, Inc. | Localized compressive strained semiconductor |
| US20070228491A1 (en) * | 2006-04-04 | 2007-10-04 | Micron Technology, Inc. | Tunneling transistor with sublithographic channel |
| US8354311B2 (en) | 2006-04-04 | 2013-01-15 | Micron Technology, Inc. | Method for forming nanofin transistors |
| US8734583B2 (en) * | 2006-04-04 | 2014-05-27 | Micron Technology, Inc. | Grown nanofin transistors |
| US7491995B2 (en) * | 2006-04-04 | 2009-02-17 | Micron Technology, Inc. | DRAM with nanofin transistors |
| US7425491B2 (en) | 2006-04-04 | 2008-09-16 | Micron Technology, Inc. | Nanowire transistor with surrounding gate |
| US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
| WO2009033184A2 (en) * | 2007-09-06 | 2009-03-12 | Picogem Corp. | Clock guided logic with reduced switching |
| US8347165B2 (en) | 2007-12-17 | 2013-01-01 | Micron Technology, Inc. | Self-timed error correcting code evaluation system and method |
| KR101468897B1 (ko) * | 2008-03-11 | 2014-12-04 | 삼성전자주식회사 | 도미도 로직 회로 및 파이프라인 도미노 로직 회로 |
| US8134854B2 (en) * | 2008-11-25 | 2012-03-13 | Mediatek Inc. | Efuse device |
| WO2013018061A1 (en) * | 2011-08-03 | 2013-02-07 | Ben Gurion University Of The Negev Research And Development Authority | Device and method for dual-mode logic |
| US9401363B2 (en) | 2011-08-23 | 2016-07-26 | Micron Technology, Inc. | Vertical transistor devices, memory arrays, and methods of forming vertical transistor devices |
| US8806316B2 (en) | 2012-01-11 | 2014-08-12 | Micron Technology, Inc. | Circuits, integrated circuits, and methods for interleaved parity computation |
| US9859286B2 (en) | 2014-12-23 | 2018-01-02 | International Business Machines Corporation | Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices |
| US10079602B1 (en) | 2017-10-10 | 2018-09-18 | Tacho Holdings, Llc | Unipolar latched logic circuits |
| US10505540B2 (en) | 2017-03-08 | 2019-12-10 | Tacho Holdings, Llc | Unipolar logic circuits |
| US11750191B2 (en) | 2017-10-10 | 2023-09-05 | Tacho Holdings, Llc | Three-dimensional logic circuit |
| US11228315B2 (en) | 2017-10-10 | 2022-01-18 | Tacho Holdings, Llc | Three-dimensional logic circuit |
| KR102105945B1 (ko) * | 2018-12-10 | 2020-04-29 | 포항공과대학교 산학협력단 | 의사 상보성 로직 네트워크 |
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-
2001
- 2001-02-15 US US09/788,109 patent/US6649476B2/en not_active Expired - Fee Related
-
2002
- 2002-02-07 CN CNB028050738A patent/CN100464502C/zh not_active Expired - Fee Related
- 2002-02-07 AT AT02704367T patent/ATE497279T1/de not_active IP Right Cessation
- 2002-02-07 AU AU2002238056A patent/AU2002238056A1/en not_active Abandoned
- 2002-02-07 JP JP2002570406A patent/JP4036096B2/ja not_active Expired - Fee Related
- 2002-02-07 DE DE60239052T patent/DE60239052D1/de not_active Expired - Lifetime
- 2002-02-07 CN CN2005100995858A patent/CN1738047B/zh not_active Expired - Fee Related
- 2002-02-07 KR KR1020037010613A patent/KR100581010B1/ko not_active IP Right Cessation
- 2002-02-07 EP EP02704367A patent/EP1378060B1/de not_active Expired - Lifetime
- 2002-02-07 WO PCT/US2002/003512 patent/WO2002071611A2/en not_active Application Discontinuation
- 2002-10-29 US US10/283,775 patent/US6801056B2/en not_active Expired - Fee Related
-
2003
- 2003-02-13 US US10/367,519 patent/US6946879B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| ATE497279T1 (de) | 2011-02-15 |
| KR20040051575A (ko) | 2004-06-18 |
| CN1738047B (zh) | 2010-05-12 |
| US6801056B2 (en) | 2004-10-05 |
| US6946879B2 (en) | 2005-09-20 |
| CN1491483A (zh) | 2004-04-21 |
| CN100464502C (zh) | 2009-02-25 |
| WO2002071611A3 (en) | 2003-10-30 |
| US20030153156A1 (en) | 2003-08-14 |
| KR100581010B1 (ko) | 2006-05-16 |
| EP1378060B1 (de) | 2011-01-26 |
| US20030049910A1 (en) | 2003-03-13 |
| JP4036096B2 (ja) | 2008-01-23 |
| CN1738047A (zh) | 2006-02-22 |
| EP1378060A2 (de) | 2004-01-07 |
| US20020110032A1 (en) | 2002-08-15 |
| JP2005505150A (ja) | 2005-02-17 |
| US6649476B2 (en) | 2003-11-18 |
| WO2002071611A2 (en) | 2002-09-12 |
| AU2002238056A1 (en) | 2002-09-19 |
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