DE60205626D1 - Mehrphasenkodiertes protokoll und bussynchronisation - Google Patents

Mehrphasenkodiertes protokoll und bussynchronisation

Info

Publication number
DE60205626D1
DE60205626D1 DE60205626T DE60205626T DE60205626D1 DE 60205626 D1 DE60205626 D1 DE 60205626D1 DE 60205626 T DE60205626 T DE 60205626T DE 60205626 T DE60205626 T DE 60205626T DE 60205626 D1 DE60205626 D1 DE 60205626D1
Authority
DE
Germany
Prior art keywords
bus
commands
phase coded
bus synchronization
encoded protocol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60205626T
Other languages
English (en)
Other versions
DE60205626T2 (de
Inventor
Karl Mauritz
Paul Levy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE60205626D1 publication Critical patent/DE60205626D1/de
Application granted granted Critical
Publication of DE60205626T2 publication Critical patent/DE60205626T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
DE60205626T 2001-06-19 2002-06-13 Mehrphasenkodiertes protokoll und bussynchronisation Expired - Lifetime DE60205626T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US885394 2001-06-19
US09/885,394 US6996632B2 (en) 2001-06-19 2001-06-19 Multiphase encoded protocol and synchronization of buses
PCT/US2002/018980 WO2002103534A1 (en) 2001-06-19 2002-06-13 Multiphase encoded protocol and synchronization of buses

Publications (2)

Publication Number Publication Date
DE60205626D1 true DE60205626D1 (de) 2005-09-22
DE60205626T2 DE60205626T2 (de) 2006-06-29

Family

ID=25386807

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60205626T Expired - Lifetime DE60205626T2 (de) 2001-06-19 2002-06-13 Mehrphasenkodiertes protokoll und bussynchronisation

Country Status (8)

Country Link
US (2) US6996632B2 (de)
EP (1) EP1397749B1 (de)
JP (1) JP4544858B2 (de)
CN (1) CN1262936C (de)
AT (1) ATE302445T1 (de)
DE (1) DE60205626T2 (de)
TW (1) TWI254526B (de)
WO (1) WO2002103534A1 (de)

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US6996632B2 (en) 2001-06-19 2006-02-07 Intel Corporation Multiphase encoded protocol and synchronization of buses
US7346099B2 (en) * 2002-01-03 2008-03-18 Intel Corporation Network fabric physical layer
US7283566B2 (en) * 2002-06-14 2007-10-16 Silicon Image, Inc. Method and circuit for generating time stamp data from an embedded-clock audio data stream and a video clock
US7440515B2 (en) * 2004-10-25 2008-10-21 Atmel Corporation System and method for controlling modulation
WO2007125472A2 (en) * 2006-04-28 2007-11-08 Nxp B.V. Data processing apparatus
US8428098B2 (en) * 2006-07-06 2013-04-23 Qualcomm Incorporated Geo-locating end-user devices on a communication network
US8340682B2 (en) * 2006-07-06 2012-12-25 Qualcomm Incorporated Method for disseminating geolocation information for network infrastructure devices
JP4645717B2 (ja) * 2008-09-26 2011-03-09 ソニー株式会社 インタフェース回路および映像装置
US8633455B2 (en) * 2010-01-12 2014-01-21 Landauer, Inc. Optical system for dosimeter reader
CN105262565B (zh) * 2015-09-11 2018-10-09 烽火通信科技股份有限公司 一种基于相位调制传递时钟与数据的编码方法及系统

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JPS61175799A (ja) 1985-01-31 1986-08-07 ソニー株式会社 ワイヤレスリモ−トコントロ−ル装置
US5436897A (en) * 1992-04-15 1995-07-25 Ford Motor Company Multiplex wiring system using varying duration pulse width modulation
FI95757C (fi) 1992-10-09 1996-03-11 Nokia Mobile Phones Ltd Menetelmä sekä IC-väylärakenne sarjamuotoisen datan siirtämiseksi
US5412697A (en) 1993-01-14 1995-05-02 Apple Computer, Inc. Delay line separator for data bus
US5438897A (en) * 1993-12-29 1995-08-08 Murata Machinery, Ltd., Machine Tool Division Stripper arrangement for a punch holder
WO1996033464A1 (en) * 1995-04-18 1996-10-24 International Business Machines Corporation Processing unit to clock interface
US5881247A (en) * 1995-11-30 1999-03-09 Allen-Bradley Company Llc System having a plurality of frame bytes capable of identifying addressed recipients and assert a busy signal onto the backplane bus to forthrightly abort the message transfer
TW375529B (en) * 1997-05-14 1999-12-01 Sega Corp Data transmission method and game system using the same
US6442644B1 (en) * 1997-08-11 2002-08-27 Advanced Memory International, Inc. Memory system having synchronous-link DRAM (SLDRAM) devices and controller
US6008734A (en) * 1997-10-08 1999-12-28 Adc Telecommunications, Inc. Method and system for diminishing phase shift between two signals
US6009488A (en) * 1997-11-07 1999-12-28 Microlinc, Llc Computer having packet-based interconnect channel
US6426943B1 (en) * 1998-04-10 2002-07-30 Top Layer Networks, Inc. Application-level data communication switching system and process for automatic detection of and quality of service adjustment for bulk data transfers
US6404771B1 (en) * 1998-06-17 2002-06-11 Advanced Micro Devices, Inc. Clock lead/lag extraction in an isochronous data bus
US6085270A (en) * 1998-06-17 2000-07-04 Advanced Micro Devices, Inc. Multi-channel, multi-rate isochronous data bus
US6338127B1 (en) * 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6594284B1 (en) * 1998-09-16 2003-07-15 Cirrus Logic, Inc. Network synchronization
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US6704882B2 (en) * 2001-01-22 2004-03-09 Mayo Foundation For Medical Education And Research Data bit-to-clock alignment circuit with first bit capture capability
US6996632B2 (en) 2001-06-19 2006-02-07 Intel Corporation Multiphase encoded protocol and synchronization of buses
US8008734B2 (en) * 2007-01-11 2011-08-30 Fuji Electric Co., Ltd. Power semiconductor device

Also Published As

Publication number Publication date
ATE302445T1 (de) 2005-09-15
TWI254526B (en) 2006-05-01
CN1262936C (zh) 2006-07-05
US7673073B2 (en) 2010-03-02
DE60205626T2 (de) 2006-06-29
CN1514974A (zh) 2004-07-21
JP4544858B2 (ja) 2010-09-15
WO2002103534A1 (en) 2002-12-27
EP1397749A1 (de) 2004-03-17
US6996632B2 (en) 2006-02-07
JP2004531150A (ja) 2004-10-07
US20030014543A1 (en) 2003-01-16
US20060069810A1 (en) 2006-03-30
EP1397749B1 (de) 2005-08-17

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