DE602005026658D1 - Mehrkernprozessor mit unterstützung für mehrere virtuelle prozessoren - Google Patents

Mehrkernprozessor mit unterstützung für mehrere virtuelle prozessoren

Info

Publication number
DE602005026658D1
DE602005026658D1 DE602005026658T DE602005026658T DE602005026658D1 DE 602005026658 D1 DE602005026658 D1 DE 602005026658D1 DE 602005026658 T DE602005026658 T DE 602005026658T DE 602005026658 T DE602005026658 T DE 602005026658T DE 602005026658 D1 DE602005026658 D1 DE 602005026658D1
Authority
DE
Germany
Prior art keywords
processor
virtual processors
support
subset
core processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005026658T
Other languages
English (en)
Inventor
Ricky C Hetherington
Bikram Saha
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oracle America Inc
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Publication of DE602005026658D1 publication Critical patent/DE602005026658D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
DE602005026658T 2004-06-30 2005-06-30 Mehrkernprozessor mit unterstützung für mehrere virtuelle prozessoren Active DE602005026658D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US58406404P 2004-06-30 2004-06-30
US11/063,793 US7873776B2 (en) 2004-06-30 2005-02-23 Multiple-core processor with support for multiple virtual processors
PCT/US2005/023182 WO2006004875A1 (en) 2004-06-30 2005-06-30 Multiple-core processor with support for multiple virtual processors

Publications (1)

Publication Number Publication Date
DE602005026658D1 true DE602005026658D1 (de) 2011-04-14

Family

ID=35062981

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005026658T Active DE602005026658D1 (de) 2004-06-30 2005-06-30 Mehrkernprozessor mit unterstützung für mehrere virtuelle prozessoren

Country Status (5)

Country Link
US (1) US7873776B2 (de)
EP (1) EP1766529B1 (de)
AT (1) ATE500557T1 (de)
DE (1) DE602005026658D1 (de)
WO (1) WO2006004875A1 (de)

Families Citing this family (129)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7685354B1 (en) * 2004-06-30 2010-03-23 Sun Microsystems, Inc. Multiple-core processor with flexible mapping of processor cores to cache banks
US7873776B2 (en) 2004-06-30 2011-01-18 Oracle America, Inc. Multiple-core processor with support for multiple virtual processors
US7716521B1 (en) * 2005-05-06 2010-05-11 Oracle America, Inc. Multiple-core, multithreaded processor with flexible error steering mechanism
US7657807B1 (en) 2005-06-27 2010-02-02 Sun Microsystems, Inc. Integrated circuit with embedded test functionality
EP1908295A2 (de) * 2005-07-28 2008-04-09 Thomson Licensing Verfahren und gerät zur videobewegungsprozessoptimierung mit einem hierarchischen cache
US7552283B2 (en) * 2006-01-20 2009-06-23 Qualcomm Incorporated Efficient memory hierarchy management
US7774590B2 (en) * 2006-03-23 2010-08-10 Intel Corporation Resiliently retaining state information of a many-core processor
US7533316B2 (en) * 2006-03-31 2009-05-12 Intel Corporation Method and apparatus for disabling and swapping cores in a multi-core microprocessor
US8766995B2 (en) * 2006-04-26 2014-07-01 Qualcomm Incorporated Graphics system with configurable caches
US20070268289A1 (en) * 2006-05-16 2007-11-22 Chun Yu Graphics system with dynamic reposition of depth engine
US20070271130A1 (en) * 2006-05-19 2007-11-22 Microsoft Corporation Flexible scheduling and pricing of multicore computer chips
US8884972B2 (en) * 2006-05-25 2014-11-11 Qualcomm Incorporated Graphics processor with arithmetic and elementary function units
US8869147B2 (en) * 2006-05-31 2014-10-21 Qualcomm Incorporated Multi-threaded processor with deferred thread output control
US8644643B2 (en) 2006-06-14 2014-02-04 Qualcomm Incorporated Convolution filtering in a graphics processor
US8766996B2 (en) * 2006-06-21 2014-07-01 Qualcomm Incorporated Unified virtual addressed register file
CN101479686A (zh) * 2006-06-27 2009-07-08 皇家飞利浦电子股份有限公司 用于管理多个数据处理单元的功率消耗的设备和方法
DE102006045113B3 (de) * 2006-09-25 2008-04-03 Qimonda Ag Speichermodul-System, Speichermodul, Buffer-Bauelement, Speichermodul-Platine, und Verfahren zum Betreiben eines Speichermoduls
WO2008047179A1 (en) * 2006-10-20 2008-04-24 Freescale Semiconductor, Inc. Device having redundant core and a method for providing core redundancy
US20080229065A1 (en) * 2007-03-13 2008-09-18 Hung Qui Le Configurable Microprocessor
US20080229058A1 (en) * 2007-03-13 2008-09-18 Hung Qui Le Configurable Microprocessor
US8316258B2 (en) * 2007-05-03 2012-11-20 Oracle America, Inc. System and method for error detection in a data storage system
US7984272B2 (en) * 2007-06-27 2011-07-19 International Business Machines Corporation Design structure for single hot forward interconnect scheme for delayed execution pipelines
US7769987B2 (en) * 2007-06-27 2010-08-03 International Business Machines Corporation Single hot forward interconnect scheme for delayed execution pipelines
US7949913B2 (en) * 2007-08-14 2011-05-24 Dell Products L.P. Method for creating a memory defect map and optimizing performance using the memory defect map
US9373362B2 (en) * 2007-08-14 2016-06-21 Dell Products L.P. System and method for implementing a memory defect map
US7945815B2 (en) * 2007-08-14 2011-05-17 Dell Products L.P. System and method for managing memory errors in an information handling system
WO2009064864A1 (en) * 2007-11-13 2009-05-22 Rockwell Automation Technologies, Inc. Industrial controller using shared memory multicore architecture
US7996648B2 (en) 2007-12-19 2011-08-09 Microsoft Corporation Coupled symbiotic operating systems
US7512837B1 (en) * 2008-04-04 2009-03-31 International Business Machines Corporation System and method for the recovery of lost cache capacity due to defective cores in a multi-core chip
US8135916B1 (en) * 2008-04-25 2012-03-13 Marvell International Ltd. Method and apparatus for hardware-configurable multi-policy coherence protocol
US8561072B2 (en) * 2008-05-16 2013-10-15 Microsoft Corporation Scheduling collections in a scheduler
US8566830B2 (en) * 2008-05-16 2013-10-22 Microsoft Corporation Local collections of tasks in a scheduler
JP2009289307A (ja) * 2008-05-28 2009-12-10 Toshiba Corp 半導体記憶装置
US8230196B1 (en) * 2009-05-28 2012-07-24 Micron Technology, Inc. Configurable partitions for non-volatile memory
US9274851B2 (en) 2009-11-25 2016-03-01 Brocade Communications Systems, Inc. Core-trunking across cores on physically separated processors allocated to a virtual machine based on configuration information including context information for virtual machines
US8503289B2 (en) 2010-03-19 2013-08-06 Brocade Communications Systems, Inc. Synchronizing multicast information for linecards
US8769155B2 (en) * 2010-03-19 2014-07-01 Brocade Communications Systems, Inc. Techniques for synchronizing application object instances
US9104619B2 (en) 2010-07-23 2015-08-11 Brocade Communications Systems, Inc. Persisting data across warm boots
US8495418B2 (en) 2010-07-23 2013-07-23 Brocade Communications Systems, Inc. Achieving ultra-high availability using a single CPU
US8606999B2 (en) * 2010-08-13 2013-12-10 Advanced Micro Devices, Inc. Cache partitioning
US8418177B2 (en) 2010-10-01 2013-04-09 Microsoft Corporation Virtual machine and/or multi-level scheduling support on systems with asymmetric processor cores
WO2012092268A1 (en) * 2010-12-29 2012-07-05 Citrix Systems, Inc. Systems and methods for scalable n-core statistics aggregation
US9378560B2 (en) * 2011-06-17 2016-06-28 Advanced Micro Devices, Inc. Real time on-chip texture decompression using shader processors
US9098561B2 (en) 2011-08-30 2015-08-04 Intel Corporation Determining an effective stress level on a processor
US9143335B2 (en) 2011-09-16 2015-09-22 Brocade Communications Systems, Inc. Multicast route cache system
US8724408B2 (en) 2011-11-29 2014-05-13 Kingtiger Technology (Canada) Inc. Systems and methods for testing and assembling memory modules
US8914615B2 (en) 2011-12-02 2014-12-16 Arm Limited Mapping same logical register specifier for different instruction sets with divergent association to architectural register file using common address format
US9069598B2 (en) * 2012-01-06 2015-06-30 International Business Machines Corporation Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core
KR101865990B1 (ko) * 2012-02-22 2018-07-04 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 컴퓨터에서 운영 체제로부터 논리 프로세서를 은폐하기
US8898397B2 (en) 2012-04-11 2014-11-25 Moon J. Kim Memory and process sharing across multiple chipsets via input/output with virtualization
US8910179B2 (en) * 2012-05-15 2014-12-09 Freescale Semiconductor, Inc. Systems and methods for providing semaphore-based protection of system resources
US9117552B2 (en) 2012-08-28 2015-08-25 Kingtiger Technology(Canada), Inc. Systems and methods for testing memory
US10581763B2 (en) 2012-09-21 2020-03-03 Avago Technologies International Sales Pte. Limited High availability application messaging layer
US9203690B2 (en) 2012-09-24 2015-12-01 Brocade Communications Systems, Inc. Role based multicast messaging infrastructure
US9967106B2 (en) 2012-09-24 2018-05-08 Brocade Communications Systems LLC Role based multicast messaging infrastructure
US9292318B2 (en) * 2012-11-26 2016-03-22 International Business Machines Corporation Initiating software applications requiring different processor architectures in respective isolated execution environment of an operating system
US9639372B2 (en) 2012-12-28 2017-05-02 Intel Corporation Apparatus and method for heterogeneous processors mapping to virtual cores
US9329900B2 (en) * 2012-12-28 2016-05-03 Intel Corporation Hetergeneous processor apparatus and method
US9672046B2 (en) 2012-12-28 2017-06-06 Intel Corporation Apparatus and method for intelligently powering heterogeneous processor components
US9448829B2 (en) 2012-12-28 2016-09-20 Intel Corporation Hetergeneous processor apparatus and method
US8965288B2 (en) 2012-12-31 2015-02-24 Elwha Llc Cost-effective mobile connectivity protocols
US9876762B2 (en) * 2012-12-31 2018-01-23 Elwha Llc Cost-effective mobile connectivity protocols
US9781664B2 (en) 2012-12-31 2017-10-03 Elwha Llc Cost-effective mobile connectivity protocols
US9635605B2 (en) 2013-03-15 2017-04-25 Elwha Llc Protocols for facilitating broader access in wireless communications
US9713013B2 (en) 2013-03-15 2017-07-18 Elwha Llc Protocols for providing wireless communications connectivity maps
US9451394B2 (en) 2012-12-31 2016-09-20 Elwha Llc Cost-effective mobile connectivity protocols
US9980114B2 (en) 2013-03-15 2018-05-22 Elwha Llc Systems and methods for communication management
US9832628B2 (en) 2012-12-31 2017-11-28 Elwha, Llc Cost-effective mobile connectivity protocols
TWI507991B (zh) * 2013-02-27 2015-11-11 Rdc Semiconductor Co Ltd 多核心處理器及其相關控制方法與電腦系統
US9706382B2 (en) 2013-03-15 2017-07-11 Elwha Llc Protocols for allocating communication services cost in wireless communications
US9781554B2 (en) 2013-03-15 2017-10-03 Elwha Llc Protocols for facilitating third party authorization for a rooted communication device in wireless communications
US9727345B2 (en) 2013-03-15 2017-08-08 Intel Corporation Method for booting a heterogeneous system and presenting a symmetric core view
US9866706B2 (en) 2013-03-15 2018-01-09 Elwha Llc Protocols for facilitating broader access in wireless communications
US9693214B2 (en) 2013-03-15 2017-06-27 Elwha Llc Protocols for facilitating broader access in wireless communications
US9807582B2 (en) 2013-03-15 2017-10-31 Elwha Llc Protocols for facilitating broader access in wireless communications
US9596584B2 (en) 2013-03-15 2017-03-14 Elwha Llc Protocols for facilitating broader access in wireless communications by conditionally authorizing a charge to an account of a third party
US9813887B2 (en) 2013-03-15 2017-11-07 Elwha Llc Protocols for facilitating broader access in wireless communications responsive to charge authorization statuses
US9843917B2 (en) 2013-03-15 2017-12-12 Elwha, Llc Protocols for facilitating charge-authorized connectivity in wireless communications
US9706060B2 (en) 2013-03-15 2017-07-11 Elwha Llc Protocols for facilitating broader access in wireless communications
EP2979170B1 (de) 2013-03-28 2020-07-08 Hewlett-Packard Enterprise Development LP Herstellung von rechenspeicher- und expansionsbladevorrichtungen zur verwendung für ein betriebssystem
WO2014158153A1 (en) 2013-03-28 2014-10-02 Hewlett-Packard Development Company, L.P. Identifying memory of a blade device for use by an operating system of a partition including the blade device
WO2014158161A1 (en) 2013-03-28 2014-10-02 Hewlett-Packard Development Company, L.P. Error coordination message for a blade device having a logical processor in another system firmware domain
US9317389B2 (en) 2013-06-28 2016-04-19 Intel Corporation Apparatus and method for controlling the reliability stress rate on a processor
US9223715B2 (en) 2013-08-21 2015-12-29 Via Alliance Semiconductor Co., Ltd. Microprocessor mechanism for decompression of cache correction data
US9348690B2 (en) * 2013-08-21 2016-05-24 Via Alliance Semiconductor Co., Ltd. Correctable configuration data compression and decompression system
WO2015030717A1 (en) * 2013-08-27 2015-03-05 Empire Technology Development Llc Consolidating operations associated with a plurality of host devices
GB2526018B (en) * 2013-10-31 2018-11-14 Silicon Tailor Ltd Multistage switch
US9519596B2 (en) * 2014-03-06 2016-12-13 Stmicroelectronics (Grenoble 2) Sas Resource access control in a system-on-chip
US9223574B2 (en) 2014-03-27 2015-12-29 International Business Machines Corporation Start virtual execution instruction for dispatching multiple threads in a computer
US9772867B2 (en) 2014-03-27 2017-09-26 International Business Machines Corporation Control area for managing multiple threads in a computer
US9195493B2 (en) 2014-03-27 2015-11-24 International Business Machines Corporation Dispatching multiple threads in a computer
US9213569B2 (en) 2014-03-27 2015-12-15 International Business Machines Corporation Exiting multiple threads in a computer
US9665490B2 (en) 2014-05-22 2017-05-30 Via Alliance Semiconductor Co., Ltd. Apparatus and method for repairing cache arrays in a multi-core microprocessor
US9524241B2 (en) 2014-05-22 2016-12-20 Via Alliance Semiconductor Co., Ltd. Multi-core microprocessor power gating cache restoral mechanism
US9606933B2 (en) 2014-05-22 2017-03-28 Via Alliance Semiconductor Co., Ltd. Multi-core apparatus and method for restoring data arrays following a power gating event
US9395802B2 (en) 2014-05-22 2016-07-19 Via Alliance Semiconductor Co., Ltd. Multi-core data array power gating restoral mechanism
US9904339B2 (en) 2014-09-10 2018-02-27 Intel Corporation Providing lifetime statistical information for a processor
US9619349B2 (en) 2014-10-14 2017-04-11 Brocade Communications Systems, Inc. Biasing active-standby determination
US9489309B2 (en) * 2014-10-31 2016-11-08 Oracle International Corporation Method and system for dynamic cache partitioning using address remapping
US9720861B2 (en) * 2014-12-02 2017-08-01 Qualcomm Incorporated Memory access by dual processor systems
GB2533292B (en) * 2014-12-15 2016-11-02 Ibm Differential data access
US9704598B2 (en) 2014-12-27 2017-07-11 Intel Corporation Use of in-field programmable fuses in the PCH dye
CN106033725B (zh) * 2015-03-13 2020-10-16 联华电子股份有限公司 半导体元件及其制作工艺
DE102015207323A1 (de) * 2015-04-22 2016-10-27 Robert Bosch Gmbh Verfahren und Vorrichtung zur Synthese eines Schaltungslayouts
US10346168B2 (en) 2015-06-26 2019-07-09 Microsoft Technology Licensing, Llc Decoupled processor instruction window and operand buffer
US11755484B2 (en) 2015-06-26 2023-09-12 Microsoft Technology Licensing, Llc Instruction block allocation
US10169044B2 (en) 2015-06-26 2019-01-01 Microsoft Technology Licensing, Llc Processing an encoding format field to interpret header information regarding a group of instructions
US10175988B2 (en) 2015-06-26 2019-01-08 Microsoft Technology Licensing, Llc Explicit instruction scheduler state information for a processor
US10191747B2 (en) 2015-06-26 2019-01-29 Microsoft Technology Licensing, Llc Locking operand values for groups of instructions executed atomically
US10409599B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Decoding information about a group of instructions including a size of the group of instructions
US9946548B2 (en) 2015-06-26 2018-04-17 Microsoft Technology Licensing, Llc Age-based management of instruction blocks in a processor instruction window
US9952867B2 (en) 2015-06-26 2018-04-24 Microsoft Technology Licensing, Llc Mapping instruction blocks based on block size
US10409606B2 (en) 2015-06-26 2019-09-10 Microsoft Technology Licensing, Llc Verifying branch targets
US20170052799A1 (en) * 2015-08-21 2017-02-23 Microchip Technology Incorporated Integrated Circuit Device With Selectable Processor Core
US11126433B2 (en) 2015-09-19 2021-09-21 Microsoft Technology Licensing, Llc Block-based processor core composition register
US11016770B2 (en) 2015-09-19 2021-05-25 Microsoft Technology Licensing, Llc Distinct system registers for logical processors
US10768936B2 (en) 2015-09-19 2020-09-08 Microsoft Technology Licensing, Llc Block-based processor including topology and control registers to indicate resource sharing and size of logical processor
TWI710899B (zh) * 2015-10-14 2020-11-21 南韓商三星電子股份有限公司 計算系統以及其操作方法
US10324722B2 (en) 2016-06-24 2019-06-18 Hewlett Packard Enterprise Development Lp Global capabilities transferrable across node boundaries
US11531552B2 (en) 2017-02-06 2022-12-20 Microsoft Technology Licensing, Llc Executing multiple programs simultaneously on a processor core
US10303615B2 (en) 2017-06-16 2019-05-28 Hewlett Packard Enterprise Development Lp Matching pointers across levels of a memory hierarchy
US11210092B2 (en) * 2018-03-06 2021-12-28 International Business Machines Corporation Servicing indirect data storage requests with multiple memory controllers
CA3036879A1 (en) * 2018-03-16 2019-09-16 Feng Pan Integrated solution techniques for security constrained unit commitment problem
US10565036B1 (en) * 2019-02-14 2020-02-18 Axis Semiconductor, Inc. Method of synchronizing host and coprocessor operations via FIFO communication
US11301254B2 (en) * 2019-07-25 2022-04-12 International Business Machines Corporation Instruction streaming using state migration
US11061681B2 (en) * 2019-07-25 2021-07-13 International Business Machines Corporation Instruction streaming using copy select vector
US20220180162A1 (en) * 2020-12-08 2022-06-09 Electronics And Telecommunications Research Institute Ai accelerator, cache memory and method of operating cache memory using the same
US11762587B2 (en) 2021-05-05 2023-09-19 Samsung Electronics Co., Ltd Method and memory device for atomic processing of fused commands
US20230342296A1 (en) * 2022-04-26 2023-10-26 Cadence Design Systems, Inc. Managing Multiple Cache Memory Circuit Operations

Family Cites Families (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754394A (en) * 1984-10-24 1988-06-28 International Business Machines Corporation Multiprocessing system having dynamically allocated local/global storage and including interleaving transformation circuit for transforming real addresses to corresponding absolute address of the storage
EP0477595A3 (en) * 1990-09-26 1992-11-19 Siemens Aktiengesellschaft Cache memory device with m bus connections
DE69226150T2 (de) * 1991-11-05 1999-02-18 Hsu Fu Chieh Redundanzarchitektur für Schaltungsmodul
GB2271202B (en) * 1992-10-01 1995-12-13 Digital Equipment Int Dynamic non-coherent cache memory resizing mechanism
US5598568A (en) * 1993-05-06 1997-01-28 Mercury Computer Systems, Inc. Multicomputer memory access architecture
DE69427734T2 (de) * 1993-10-29 2002-05-23 Advanced Micro Devices Inc Linearadressierter Mikroprozessorcachespeicher
US5692193A (en) * 1994-03-31 1997-11-25 Nec Research Institute, Inc. Software architecture for control of highly parallel computer systems
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US6182203B1 (en) * 1997-01-24 2001-01-30 Texas Instruments Incorporated Microprocessor
US6567837B1 (en) 1997-01-29 2003-05-20 Iq Systems Object oriented processor arrays
US6662216B1 (en) * 1997-04-14 2003-12-09 International Business Machines Corporation Fixed bus tags for SMP buses
US6049856A (en) * 1997-05-27 2000-04-11 Unisys Corporation System for simultaneously accessing two portions of a shared memory
US6035374A (en) * 1997-06-25 2000-03-07 Sun Microsystems, Inc. Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US6012103A (en) * 1997-07-02 2000-01-04 Cypress Semiconductor Corp. Bus interface system and method
US6058475A (en) * 1997-09-22 2000-05-02 Ncr Corporation Booting method for multi-processor computer
US6381682B2 (en) * 1998-06-10 2002-04-30 Compaq Information Technologies Group, L.P. Method and apparatus for dynamically sharing memory in a multiprocessor system
US6226734B1 (en) * 1998-06-10 2001-05-01 Compaq Computer Corporation Method and apparatus for processor migration from different processor states in a multi-processor computer system
US6119185A (en) * 1997-11-25 2000-09-12 Ncr Corporation Computer system configuration apparatus and method that performs pre-assignment conflict analysis
US6298426B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Controller configurable for use with multiple memory organizations
JP3614650B2 (ja) * 1998-03-20 2005-01-26 富士通株式会社 マルチプロセッサ制御方式及びこれに用いられるブート装置及びブート制御装置
US6247109B1 (en) * 1998-06-10 2001-06-12 Compaq Computer Corp. Dynamically assigning CPUs to different partitions each having an operation system instance in a shared memory space
US6240490B1 (en) * 1998-07-20 2001-05-29 International Business Machines Corporation Comprehensive multilevel cache preloading mechanism in a multiprocessing simulation environment
US6314471B1 (en) * 1998-11-13 2001-11-06 Cray Inc. Techniques for an interrupt free operating system
US6360333B1 (en) * 1998-11-19 2002-03-19 Compaq Computer Corporation Method and apparatus for determining a processor failure in a multiprocessor computer
US6349363B2 (en) * 1998-12-08 2002-02-19 Intel Corporation Multi-section cache with different attributes for each section
US6401202B1 (en) * 1999-06-18 2002-06-04 Phoenix Technologies Ltd. Multitasking during BIOS boot-up
US6374338B1 (en) * 1999-06-25 2002-04-16 International Business Machines Corporation Method for performing configuration tasks prior to and including memory configuration within a processor-based system
US6501999B1 (en) * 1999-12-22 2002-12-31 Intel Corporation Multi-processor mobile computer system having one processor integrated with a chipset
US6381669B1 (en) * 1999-12-27 2002-04-30 Gregory V. Chudnovsky Multi-bank, fault-tolerant, high-performance memory addressing system and method
US6694421B2 (en) * 1999-12-29 2004-02-17 Intel Corporation Cache memory bank access prediction
WO2001061500A1 (en) 2000-02-16 2001-08-23 Intel Corporation Processor with cache divided for processor core and pixel engine uses
JP2001265652A (ja) * 2000-03-17 2001-09-28 Hitachi Ltd キャッシュディレクトリ構成方法および情報処理装置
JP2001352358A (ja) 2000-06-07 2001-12-21 Nec Corp モデム用集積回路
DE60041444D1 (de) * 2000-08-21 2009-03-12 Texas Instruments Inc Mikroprozessor
JP2002063069A (ja) * 2000-08-21 2002-02-28 Hitachi Ltd メモリ制御装置、データ処理システム及び半導体装置
JP4394298B2 (ja) * 2001-02-20 2010-01-06 日本電気株式会社 マルチプロセッサシステムとその共有メモリ制御方法、及び共有メモリ制御プログラム
JP2002259352A (ja) * 2001-03-01 2002-09-13 Handotai Rikougaku Kenkyu Center:Kk マルチプロセッサシステム装置
US6662271B2 (en) * 2001-06-27 2003-12-09 Intel Corporation Cache architecture with redundant sub array
US6839808B2 (en) * 2001-07-06 2005-01-04 Juniper Networks, Inc. Processing cluster having multiple compute engines and shared tier one caches
US6874056B2 (en) * 2001-10-09 2005-03-29 Agere Systems Inc. Method and apparatus for reducing cache thrashing
US6871264B2 (en) * 2002-03-06 2005-03-22 Hewlett-Packard Development Company, L.P. System and method for dynamic processor core and cache partitioning on large-scale multithreaded, multiprocessor integrated circuits
US7055060B2 (en) * 2002-12-19 2006-05-30 Intel Corporation On-die mechanism for high-reliability processor
US7055003B2 (en) * 2003-04-25 2006-05-30 International Business Machines Corporation Data cache scrub mechanism for large L2/L3 data cache structures
US7240160B1 (en) * 2004-06-30 2007-07-03 Sun Microsystems, Inc. Multiple-core processor with flexible cache directory scheme
US7873776B2 (en) 2004-06-30 2011-01-18 Oracle America, Inc. Multiple-core processor with support for multiple virtual processors

Also Published As

Publication number Publication date
US7873776B2 (en) 2011-01-18
EP1766529A1 (de) 2007-03-28
US20060004942A1 (en) 2006-01-05
WO2006004875A1 (en) 2006-01-12
ATE500557T1 (de) 2011-03-15
EP1766529B1 (de) 2011-03-02

Similar Documents

Publication Publication Date Title
DE602005026658D1 (de) Mehrkernprozessor mit unterstützung für mehrere virtuelle prozessoren
DE60236309D1 (de) Leistungssteuerung für dram
Li et al. STT-RAM based energy-efficiency hybrid cache for CMPs
Volkov Better performance at lower occupancy
DE602004031855D1 (de) Mehrkern-mehrthread-prozessor
ATE366985T1 (de) Integrierte schaltung und verfahren zum cache- umabbilden
TW200710723A (en) Dual thread processor
WO2011022110A3 (en) Allocating processor cores with cache memory associativity
DE602004008783D1 (de) Cache-crossbar-arbitrierung
WO2009107048A3 (en) Methods and systems for dynamic cache partitioning for distributed applications operating on multiprocessor architectures
WO2009120997A3 (en) Technique to share information among different cache coherency domains
JP2007195191A5 (de)
WO2011163417A3 (en) Method and system to reduce the power consumption of a memory device
WO2019079083A3 (en) Multi-processor core device with mbist
Syu et al. High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy
ATE513264T1 (de) Direktzugriffsspeichersystem mit destruktivem lesen, gepuffert mit einem speicher-cache mit destruktivem lesen
GB2383868A (en) Cache dynamically configured for simultaneous accesses by multiple computing engines
TW200802805A (en) Nonvolatile memory cell and memory system
Li et al. Cache coherence enabled adaptive refresh for volatile STT-RAM
AR076209A1 (es) Tarjeta indicadora de humedad de bromuro de cobre
ATE550716T1 (de) Crossbar-architektur mit mehrkern-mehrthread- prozessoren
Schuchhardt et al. The impact of dynamic directories on multicore interconnects
WO2005020080A3 (en) Cache bank interface unit
Mandke et al. Adaptive power optimization of on-chip SNUCA cache on tiled chip multicore architecture using remap policy
Marino et al. Insights on memory controller scaling in multi-core embedded systems