DE602004025479D1 - Verfahren zur Verringerung von Stapelfehler-Keimstellen in bipolaren Siliziumkarbid-bauelementen - Google Patents

Verfahren zur Verringerung von Stapelfehler-Keimstellen in bipolaren Siliziumkarbid-bauelementen

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Publication number
DE602004025479D1
DE602004025479D1 DE602004025479T DE602004025479T DE602004025479D1 DE 602004025479 D1 DE602004025479 D1 DE 602004025479D1 DE 602004025479 T DE602004025479 T DE 602004025479T DE 602004025479 T DE602004025479 T DE 602004025479T DE 602004025479 D1 DE602004025479 D1 DE 602004025479D1
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Germany
Prior art keywords
silicon carbide
substrate
stacking fault
thereafter
etch
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Active
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DE602004025479T
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English (en)
Inventor
Joseph John Sumakeris
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Wolfspeed Inc
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Cree Inc
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Application filed by Cree Inc filed Critical Cree Inc
Publication of DE602004025479D1 publication Critical patent/DE602004025479D1/de
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • H01L21/30608Anisotropic liquid etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02019Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02378Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02529Silicon carbide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/931Silicon carbide semiconductor

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Weting (AREA)
  • Bipolar Transistors (AREA)
  • Chemical Vapour Deposition (AREA)
DE602004025479T 2003-09-22 2004-09-14 Verfahren zur Verringerung von Stapelfehler-Keimstellen in bipolaren Siliziumkarbid-bauelementen Active DE602004025479D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/605,312 US7018554B2 (en) 2003-09-22 2003-09-22 Method to reduce stacking fault nucleation sites and reduce forward voltage drift in bipolar devices
PCT/US2004/030041 WO2005034208A2 (en) 2003-09-22 2004-09-14 METHOD TO REDUCE STACKING FAULT NUCLEATION SITES AND REDUCE Vf DRIFT IN BIPOLAR DEVICES

Publications (1)

Publication Number Publication Date
DE602004025479D1 true DE602004025479D1 (de) 2010-03-25

Family

ID=34312546

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004025479T Active DE602004025479D1 (de) 2003-09-22 2004-09-14 Verfahren zur Verringerung von Stapelfehler-Keimstellen in bipolaren Siliziumkarbid-bauelementen

Country Status (9)

Country Link
US (2) US7018554B2 (de)
EP (1) EP1665343B1 (de)
JP (1) JP4723500B2 (de)
CN (1) CN100470725C (de)
AT (1) ATE457523T1 (de)
CA (1) CA2539618A1 (de)
DE (1) DE602004025479D1 (de)
TW (1) TW200525582A (de)
WO (1) WO2005034208A2 (de)

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US7173285B2 (en) 2004-03-18 2007-02-06 Cree, Inc. Lithographic methods to reduce stacking fault nucleation sites
JP4639326B2 (ja) * 2004-03-24 2011-02-23 独立行政法人産業技術総合研究所 半導体装置
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US8497552B2 (en) * 2008-12-01 2013-07-30 Cree, Inc. Semiconductor devices with current shifting regions and related methods
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CN104851781B (zh) * 2015-06-08 2020-04-14 国网智能电网研究院 一种n型低偏角碳化硅外延片的制备方法
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CN104993030A (zh) * 2015-06-08 2015-10-21 国网智能电网研究院 一种p型低缺陷碳化硅外延片的制备方法
CN105140111A (zh) * 2015-08-11 2015-12-09 中国科学院半导体研究所 消除碳化硅外延面穿通缺陷的方法
CN105244255B (zh) * 2015-08-27 2019-03-05 中国电子科技集团公司第十三研究所 一种碳化硅外延材料及其生产方法
WO2018150861A1 (ja) 2017-02-20 2018-08-23 日立金属株式会社 炭化ケイ素積層基板およびその製造方法
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JPWO2021025085A1 (de) 2019-08-06 2021-02-11
CN110767593A (zh) * 2019-10-14 2020-02-07 芯盟科技有限公司 一种半导体结构及其形成方法
CN111005068A (zh) * 2019-12-09 2020-04-14 中国电子科技集团公司第五十五研究所 一种生长高表面质量超厚igbt结构碳化硅外延材料的方法
JPWO2022153918A1 (de) * 2021-01-15 2022-07-21
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Also Published As

Publication number Publication date
CA2539618A1 (en) 2005-04-14
EP1665343B1 (de) 2010-02-10
JP4723500B2 (ja) 2011-07-13
US7279115B1 (en) 2007-10-09
TW200525582A (en) 2005-08-01
WO2005034208A3 (en) 2005-06-02
EP1665343A2 (de) 2006-06-07
US20070221614A1 (en) 2007-09-27
CN1856862A (zh) 2006-11-01
US7018554B2 (en) 2006-03-28
JP2007506289A (ja) 2007-03-15
ATE457523T1 (de) 2010-02-15
CN100470725C (zh) 2009-03-18
US20050064723A1 (en) 2005-03-24
WO2005034208A2 (en) 2005-04-14

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