DE602004022029D1 - St) mit verteilter befehlsinterpretation und verallgemeinertem befehlsprotokoll - Google Patents

St) mit verteilter befehlsinterpretation und verallgemeinertem befehlsprotokoll

Info

Publication number
DE602004022029D1
DE602004022029D1 DE602004022029T DE602004022029T DE602004022029D1 DE 602004022029 D1 DE602004022029 D1 DE 602004022029D1 DE 602004022029 T DE602004022029 T DE 602004022029T DE 602004022029 T DE602004022029 T DE 602004022029T DE 602004022029 D1 DE602004022029 D1 DE 602004022029D1
Authority
DE
Germany
Prior art keywords
command
distributed
interpretation
protocol
general
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004022029T
Other languages
English (en)
Inventor
Roberto F Averbuj
David W Hansquine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of DE602004022029D1 publication Critical patent/DE602004022029D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14Implementation of control logic, e.g. test mode decoders
    • G11C29/16Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
DE602004022029T 2003-03-20 2004-03-19 St) mit verteilter befehlsinterpretation und verallgemeinertem befehlsprotokoll Expired - Lifetime DE602004022029D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US45645103P 2003-03-20 2003-03-20
US10/630,480 US7392442B2 (en) 2003-03-20 2003-07-29 Built-in self-test (BIST) architecture having distributed interpretation and generalized command protocol
PCT/US2004/008664 WO2004086411A1 (en) 2003-03-20 2004-03-19 Memory built-in self-test (bist) architecture having distributed command interpretation and generalized command protocol

Publications (1)

Publication Number Publication Date
DE602004022029D1 true DE602004022029D1 (de) 2009-08-27

Family

ID=39733993

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004022029T Expired - Lifetime DE602004022029D1 (de) 2003-03-20 2004-03-19 St) mit verteilter befehlsinterpretation und verallgemeinertem befehlsprotokoll

Country Status (7)

Country Link
US (2) US7392442B2 (de)
EP (1) EP1604372B1 (de)
CA (1) CA2519618A1 (de)
DE (1) DE602004022029D1 (de)
ES (1) ES2329797T3 (de)
RU (1) RU2336581C2 (de)
WO (1) WO2004086411A1 (de)

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JP4683014B2 (ja) * 2007-06-25 2011-05-11 株式会社デンソー 経路案内装置、道路地図データ作成装置及び道路地図データ作成方法
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GB2498980A (en) * 2012-02-01 2013-08-07 Inside Secure Device and method to perform a parallel memory test
US9230046B2 (en) 2012-03-30 2016-01-05 International Business Machines Corporation Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
US9286423B2 (en) * 2012-03-30 2016-03-15 International Business Machines Corporation Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
US8872322B2 (en) 2012-10-22 2014-10-28 International Business Machines Corporation Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks
US8853847B2 (en) 2012-10-22 2014-10-07 International Business Machines Corporation Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks
US9194912B2 (en) 2012-11-29 2015-11-24 International Business Machines Corporation Circuits for self-reconfiguration or intrinsic functional changes of chips before vs. after stacking
US9116876B2 (en) 2012-12-18 2015-08-25 Qualcomm Incorporated Programmable built-in-self tester (BIST) in memory controller
US9275757B2 (en) * 2013-02-01 2016-03-01 Scaleo Chip Apparatus and method for non-intrusive random memory failure emulation within an integrated circuit
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CN105706064B (zh) 2013-07-27 2019-08-27 奈特力斯股份有限公司 具有本地分别同步的内存模块
US9946620B2 (en) 2015-02-03 2018-04-17 Invecas, Inc. Memory built-in self test system
US9715942B2 (en) 2015-06-09 2017-07-25 International Business Machines Corporation Built-in self-test (BIST) circuit and associated BIST method for embedded memories
KR102391385B1 (ko) * 2015-08-13 2022-04-27 삼성전자주식회사 내장형 로직 분석기 및 이를 포함하는 집적 회로
US9761329B2 (en) 2015-10-20 2017-09-12 Globalfoundries Inc. Built-in self-test (BIST) circuit and associated BIST method for embedded memories
US9881693B2 (en) * 2016-02-16 2018-01-30 Micron Technology, Inc. Selectors on interface die for memory device
CN109275109B (zh) * 2017-07-17 2021-08-24 中兴通讯股份有限公司 消息的处理方法、装置、终端及基站
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CN114518902A (zh) 2020-11-20 2022-05-20 马来西亚瑞天芯私人有限公司 一种内存定序器系统和应用该系统的内存定序方法

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Also Published As

Publication number Publication date
RU2336581C2 (ru) 2008-10-20
US20050257109A1 (en) 2005-11-17
EP1604372A1 (de) 2005-12-14
EP1604372B1 (de) 2009-07-15
RU2005132307A (ru) 2006-04-10
US7814380B2 (en) 2010-10-12
CA2519618A1 (en) 2004-10-07
US7392442B2 (en) 2008-06-24
WO2004086411A1 (en) 2004-10-07
US20080215944A1 (en) 2008-09-04
ES2329797T3 (es) 2009-12-01

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