DE60108993D1 - Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch - Google Patents

Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch

Info

Publication number
DE60108993D1
DE60108993D1 DE60108993T DE60108993T DE60108993D1 DE 60108993 D1 DE60108993 D1 DE 60108993D1 DE 60108993 T DE60108993 T DE 60108993T DE 60108993 T DE60108993 T DE 60108993T DE 60108993 D1 DE60108993 D1 DE 60108993D1
Authority
DE
Germany
Prior art keywords
scan
customization
low
consumption operation
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60108993T
Other languages
English (en)
Other versions
DE60108993T2 (de
Inventor
Lee D Whetsel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE60108993D1 publication Critical patent/DE60108993D1/de
Publication of DE60108993T2 publication Critical patent/DE60108993T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31724—Test controller, e.g. BIST state machine
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving
DE60108993T 2000-03-09 2001-03-07 Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch Expired - Lifetime DE60108993T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18810900P 2000-03-09 2000-03-09
US188109P 2000-03-09

Publications (2)

Publication Number Publication Date
DE60108993D1 true DE60108993D1 (de) 2005-03-31
DE60108993T2 DE60108993T2 (de) 2005-07-21

Family

ID=22691804

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60108993T Expired - Lifetime DE60108993T2 (de) 2000-03-09 2001-03-07 Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch

Country Status (5)

Country Link
US (13) US6763488B2 (de)
EP (1) EP1146343B1 (de)
JP (1) JP4971547B2 (de)
KR (1) KR100790238B1 (de)
DE (1) DE60108993T2 (de)

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US6557129B1 (en) 1999-11-23 2003-04-29 Janusz Rajski Method and apparatus for selectively compacting test responses
US6874109B1 (en) 1999-11-23 2005-03-29 Janusz Rajski Phase shifter with reduced linear dependency
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US9664739B2 (en) 1999-11-23 2017-05-30 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6353842B1 (en) * 1999-11-23 2002-03-05 Janusz Rajski Method for synthesizing linear finite state machines
US8533547B2 (en) * 1999-11-23 2013-09-10 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US9134370B2 (en) 1999-11-23 2015-09-15 Mentor Graphics Corporation Continuous application and decompression of test patterns and selective compaction of test responses
US6684358B1 (en) 1999-11-23 2004-01-27 Janusz Rajski Decompressor/PRPG for applying pseudo-random and deterministic test patterns
DE60108993T2 (de) 2000-03-09 2005-07-21 Texas Instruments Inc., Dallas Anpassung von "Scan-BIST"-Architekturen für einen Betrieb mit niedrigem Verbrauch
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US7831877B2 (en) * 2007-03-08 2010-11-09 Silicon Image, Inc. Circuitry to prevent peak power problems during scan shift
US8271252B2 (en) * 2007-11-08 2012-09-18 Nvidia Corporation Automatic verification of device models
US8510616B2 (en) * 2008-02-14 2013-08-13 Nvidia Corporation Scalable scan-based test architecture with reduced test time and test power
US8046651B2 (en) 2008-04-02 2011-10-25 Texas Instruments Incorporated Compare circuit receiving scan register and inverted clock flip-flop data
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US8516409B2 (en) * 2010-11-11 2013-08-20 International Business Machines Corporation Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device
US8468405B2 (en) * 2010-12-22 2013-06-18 Arm Limited Integrated circuit testing
CN103076513A (zh) * 2012-12-21 2013-05-01 广州致远电子股份有限公司 一种便携式电能质量分析方法
CN104678240B (zh) 2013-12-03 2019-03-29 恩智浦美国有限公司 用于在多个电力模式中测试电源的电路
CN103676893A (zh) * 2013-12-19 2014-03-26 上海华龙测试仪器股份有限公司 一种试验机测控系统
US9261560B2 (en) * 2013-12-31 2016-02-16 Texas Instruments Incorporated Handling slower scan outputs at optimal frequency
JP6305823B2 (ja) * 2014-05-12 2018-04-04 株式会社メガチップス スキャンテスト回路
US9791503B1 (en) 2015-09-30 2017-10-17 Integrated Device Technology, Inc. Packaged oscillators with built-in self-test circuits that support resonator testing with reduced pin count
DE102015115915A1 (de) 2015-09-21 2017-03-23 Wisco Tailored Blanks Gmbh Laserschweißverfahren zur Herstellung eines Blechhalbzeugs aus härtbarem Stahl mit einer Beschichtung auf Aluminium- oder Aluminium-Silizium-Basis
US10088525B2 (en) 2016-02-11 2018-10-02 Texas Instruments Incorporated Non-interleaved scan operation for achieving higher scan throughput in presence of slower scan outputs
CN105823978B (zh) * 2016-03-11 2018-09-14 福州瑞芯微电子股份有限公司 一种通用的芯片测试时钟电路及其测试方法
CN105824351B (zh) * 2016-03-11 2018-12-18 福州瑞芯微电子股份有限公司 Cpu的可测试性时钟电路及其测试方法
US10107860B2 (en) * 2016-06-21 2018-10-23 International Business Machines Corporation Bitwise rotating scan section for microelectronic chip testing and diagnostics
US10014899B2 (en) * 2016-07-15 2018-07-03 Texas Instruments Incorporated System and method for built-in self-test of electronic circuits
TWI612317B (zh) 2016-11-01 2018-01-21 國立成功大學 一種測試資料之解壓縮器及其測試方法
US10340370B2 (en) * 2016-12-07 2019-07-02 Qualcomm Incorporated Asymmetric gated fin field effect transistor (FET) (finFET) diodes
KR102035421B1 (ko) * 2018-05-08 2019-10-22 한양대학교 에리카산학협력단 Ic chip의 저전력 테스트 방법 및 장치
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Also Published As

Publication number Publication date
US20120297262A1 (en) 2012-11-22
US6763488B2 (en) 2004-07-13
JP4971547B2 (ja) 2012-07-11
US20110161758A1 (en) 2011-06-30
US20050005219A1 (en) 2005-01-06
US20170016957A1 (en) 2017-01-19
US20140013176A1 (en) 2014-01-09
US8261144B2 (en) 2012-09-04
JP2001289908A (ja) 2001-10-19
US9476941B2 (en) 2016-10-25
US20170269158A1 (en) 2017-09-21
US20020112199A1 (en) 2002-08-15
KR100790238B1 (ko) 2007-12-31
EP1146343B1 (de) 2005-02-23
US9709628B2 (en) 2017-07-18
US20130246871A1 (en) 2013-09-19
US8015466B2 (en) 2011-09-06
US8566659B2 (en) 2013-10-22
US10060977B2 (en) 2018-08-28
US20100223517A1 (en) 2010-09-02
DE60108993T2 (de) 2005-07-21
US20060242520A1 (en) 2006-10-26
US8453025B2 (en) 2013-05-28
US20090183042A1 (en) 2009-07-16
US20110283154A1 (en) 2011-11-17
US7925945B2 (en) 2011-04-12
US20150309116A1 (en) 2015-10-29
EP1146343A1 (de) 2001-10-17
US7747919B2 (en) 2010-06-29
US9103881B2 (en) 2015-08-11
US7526695B2 (en) 2009-04-28
US7051257B2 (en) 2006-05-23
KR20010089208A (ko) 2001-09-29

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