DE60044209D1 - Verteilte speichersteuerung und bandbreitenoptimierung - Google Patents

Verteilte speichersteuerung und bandbreitenoptimierung

Info

Publication number
DE60044209D1
DE60044209D1 DE60044209T DE60044209T DE60044209D1 DE 60044209 D1 DE60044209 D1 DE 60044209D1 DE 60044209 T DE60044209 T DE 60044209T DE 60044209 T DE60044209 T DE 60044209T DE 60044209 D1 DE60044209 D1 DE 60044209D1
Authority
DE
Germany
Prior art keywords
memory
memory control
distributed memory
bandwidth optimization
control logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60044209T
Other languages
English (en)
Inventor
Gilbert Wolrich
Debra Bernstein
Matthew J Adiletta
William Wheeler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60044209D1 publication Critical patent/DE60044209D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
DE60044209T 1999-12-28 2000-12-06 Verteilte speichersteuerung und bandbreitenoptimierung Expired - Lifetime DE60044209D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/473,112 US6560667B1 (en) 1999-12-28 1999-12-28 Handling contiguous memory references in a multi-queue system
PCT/US2000/042663 WO2001048619A2 (en) 1999-12-28 2000-12-06 Distributed memory control and bandwidth optimization

Publications (1)

Publication Number Publication Date
DE60044209D1 true DE60044209D1 (de) 2010-05-27

Family

ID=23878258

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60044209T Expired - Lifetime DE60044209D1 (de) 1999-12-28 2000-12-06 Verteilte speichersteuerung und bandbreitenoptimierung

Country Status (9)

Country Link
US (1) US6560667B1 (de)
EP (1) EP1282862B1 (de)
CN (1) CN1238793C (de)
AT (1) ATE464604T1 (de)
AU (1) AU5788001A (de)
DE (1) DE60044209D1 (de)
HK (1) HK1051241A1 (de)
TW (1) TWI229259B (de)
WO (1) WO2001048619A2 (de)

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US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
WO2001016702A1 (en) 1999-09-01 2001-03-08 Intel Corporation Register set used in multithreaded parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6631430B1 (en) * 1999-12-28 2003-10-07 Intel Corporation Optimizations to receive packet status from fifo bus
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US6625654B1 (en) * 1999-12-28 2003-09-23 Intel Corporation Thread signaling in multi-threaded network processor
US6661794B1 (en) 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6584522B1 (en) * 1999-12-30 2003-06-24 Intel Corporation Communication between processors
US6631462B1 (en) * 2000-01-05 2003-10-07 Intel Corporation Memory shared between processing threads
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7126952B2 (en) * 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7853778B2 (en) 2001-12-20 2010-12-14 Intel Corporation Load/move and duplicate instructions for a processor
US7895239B2 (en) 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US6934951B2 (en) * 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
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US7769097B2 (en) 2003-09-15 2010-08-03 Intel Corporation Methods and apparatus to control transmission of a multicarrier wireless communication channel through multiple antennas
US20050198361A1 (en) * 2003-12-29 2005-09-08 Chandra Prashant R. Method and apparatus for meeting a given content throughput using at least one memory channel
US7213099B2 (en) * 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
US20050204111A1 (en) * 2004-03-10 2005-09-15 Rohit Natarajan Command scheduling for dual-data-rate two (DDR2) memory devices
US7418540B2 (en) * 2004-04-28 2008-08-26 Intel Corporation Memory controller with command queue look-ahead
US7162567B2 (en) * 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US20060067348A1 (en) * 2004-09-30 2006-03-30 Sanjeev Jain System and method for efficient memory access of queue control data structures
US7277990B2 (en) 2004-09-30 2007-10-02 Sanjeev Jain Method and apparatus providing efficient queue descriptor memory access
US20060129764A1 (en) * 2004-12-09 2006-06-15 International Business Machines Corporation Methods and apparatus for storing a command
US7418543B2 (en) 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US7555630B2 (en) * 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US20060140203A1 (en) * 2004-12-28 2006-06-29 Sanjeev Jain System and method for packet queuing
US7467256B2 (en) * 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
US20060236011A1 (en) * 2005-04-15 2006-10-19 Charles Narad Ring management
CN100346285C (zh) * 2006-01-06 2007-10-31 华为技术有限公司 处理器芯片与存储控制系统及方法
US20070245074A1 (en) * 2006-03-30 2007-10-18 Rosenbluth Mark B Ring with on-chip buffer for efficient message passing
US7926013B2 (en) * 2007-12-31 2011-04-12 Intel Corporation Validating continuous signal phase matching in high-speed nets routed as differential pairs
CN101625625B (zh) * 2008-07-11 2011-11-30 鸿富锦精密工业（深圳）有限公司 信号中继装置及利用该装置访问外部存储器的方法
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Also Published As

Publication number Publication date
EP1282862B1 (de) 2010-04-14
WO2001048619A3 (en) 2002-11-14
CN1238793C (zh) 2006-01-25
CN1437730A (zh) 2003-08-20
EP1282862A2 (de) 2003-02-12
ATE464604T1 (de) 2010-04-15
WO2001048619A2 (en) 2001-07-05
US6560667B1 (en) 2003-05-06
HK1051241A1 (en) 2003-07-25
AU5788001A (en) 2001-07-09
TWI229259B (en) 2005-03-11

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