DE60034369D1 - Mos-transistor und speicherzelle mit eingekapselter wolfram-gate, und herstellungsverfahren - Google Patents
Mos-transistor und speicherzelle mit eingekapselter wolfram-gate, und herstellungsverfahrenInfo
- Publication number
- DE60034369D1 DE60034369D1 DE60034369T DE60034369T DE60034369D1 DE 60034369 D1 DE60034369 D1 DE 60034369D1 DE 60034369 T DE60034369 T DE 60034369T DE 60034369 T DE60034369 T DE 60034369T DE 60034369 D1 DE60034369 D1 DE 60034369D1
- Authority
- DE
- Germany
- Prior art keywords
- memory cell
- mos transistor
- tungsten gate
- manufacturing
- encapsulated tungsten
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title abstract 3
- 229910052721 tungsten Inorganic materials 0.000 title abstract 3
- 239000010937 tungsten Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000002939 deleterious effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15212699P | 1999-09-02 | 1999-09-02 | |
US152126P | 1999-09-02 | ||
US09/649,027 US6346467B1 (en) | 1999-09-02 | 2000-08-28 | Method of making tungsten gate MOS transistor and memory cell by encapsulating |
US649027 | 2000-08-28 | ||
PCT/US2000/024271 WO2001017021A1 (en) | 1999-09-02 | 2000-08-31 | Encapsulated tungsten gate mos transistor and memory cell and method of making same |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60034369D1 true DE60034369D1 (de) | 2007-05-24 |
DE60034369T2 DE60034369T2 (de) | 2008-01-10 |
Family
ID=26849276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60034369T Expired - Lifetime DE60034369T2 (de) | 1999-09-02 | 2000-08-31 | Mos-transistor und speicherzelle mit eingekapselter wolfram-gate, und herstellungsverfahren |
Country Status (8)
Country | Link |
---|---|
US (2) | US6346467B1 (de) |
EP (1) | EP1247299B1 (de) |
JP (1) | JP2003531472A (de) |
KR (1) | KR100773994B1 (de) |
CN (1) | CN1192434C (de) |
AT (1) | ATE359601T1 (de) |
DE (1) | DE60034369T2 (de) |
WO (1) | WO2001017021A1 (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6583460B1 (en) * | 2000-08-29 | 2003-06-24 | Micron Technology, Inc. | Method of forming a metal to polysilicon contact in oxygen environment |
JP3332909B2 (ja) * | 2000-10-30 | 2002-10-07 | 松下電器産業株式会社 | ゲート電極構造体、その形成方法及び電極構造体の形成方法 |
DE10120523A1 (de) | 2001-04-26 | 2002-10-31 | Infineon Technologies Ag | Verfahren zur Minimierung der Wolframoxidausdampfung bei der selektiven Seitenwandoxidation von Wolfram-Silizium-Gates |
KR100414562B1 (ko) * | 2001-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | 비휘발성 메모리 셀의 제조 방법 |
US7297592B1 (en) | 2002-03-27 | 2007-11-20 | Spansion Llc | Semiconductor memory with data retention liner |
US6803624B2 (en) * | 2002-07-03 | 2004-10-12 | Micron Technology, Inc. | Programmable memory devices supported by semiconductive substrates |
KR100713326B1 (ko) * | 2002-12-30 | 2007-05-04 | 동부일렉트로닉스 주식회사 | 반도체 소자의 극 미세 트랜지스터 제작방법 |
US7033897B2 (en) * | 2003-10-23 | 2006-04-25 | Texas Instruments Incorporated | Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology |
DE102004008784B3 (de) * | 2004-02-23 | 2005-09-15 | Infineon Technologies Ag | Verfahren zur Durchkontaktierung von Feldeffekttransistoren mit einer selbstorganisierten Monolage einer organischen Verbindung als Gatedielektrikum |
GB0405325D0 (en) * | 2004-03-10 | 2004-04-21 | Koninkl Philips Electronics Nv | Trench-gate transistors and their manufacture |
US7030431B2 (en) * | 2004-03-19 | 2006-04-18 | Nanya Technology Corp. | Metal gate with composite film stack |
CN100388501C (zh) * | 2004-03-26 | 2008-05-14 | 力晶半导体股份有限公司 | 与非门型闪存存储单元列及其制造方法 |
KR100586006B1 (ko) * | 2004-06-15 | 2006-06-01 | 삼성전자주식회사 | 불휘발성 메모리 장치의 게이트 구조물 형성 방법 및 이를수행하기 위한 장치 |
KR100697286B1 (ko) * | 2005-05-31 | 2007-03-20 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 형성 방법 |
US7269067B2 (en) * | 2005-07-06 | 2007-09-11 | Spansion Llc | Programming a memory device |
KR100849852B1 (ko) * | 2005-08-09 | 2008-08-01 | 삼성전자주식회사 | 비휘발성 반도체 집적 회로 장치 및 이의 제조 방법 |
US20070200149A1 (en) * | 2006-02-28 | 2007-08-30 | Veronika Polei | Semiconductor device and method of production |
US7524722B2 (en) | 2006-10-12 | 2009-04-28 | Macronix International Co., Ltd. | Resistance type memory device and fabricating method and operating method thereof |
US20080149990A1 (en) * | 2006-12-21 | 2008-06-26 | Spansion Llc | Memory system with poly metal gate |
KR100953050B1 (ko) * | 2007-10-10 | 2010-04-14 | 주식회사 하이닉스반도체 | 비휘발성 메모리 소자 및 그의 제조 방법 |
KR100953034B1 (ko) * | 2008-02-21 | 2010-04-14 | 주식회사 하이닉스반도체 | 반도체 소자 및 이의 제조 방법 |
KR100972716B1 (ko) * | 2008-03-10 | 2010-07-27 | 주식회사 하이닉스반도체 | 반도체 소자 및 이의 제조 방법 |
KR101038603B1 (ko) * | 2008-05-26 | 2011-06-03 | 주식회사 하이닉스반도체 | 반도체 소자 및 이의 제조 방법 |
WO2010076601A1 (en) * | 2008-12-30 | 2010-07-08 | Giulio Albini | Memory device and method of fabricating thereof |
US20110001179A1 (en) * | 2009-07-03 | 2011-01-06 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of the same |
US8546214B2 (en) * | 2010-04-22 | 2013-10-01 | Sandisk Technologies Inc. | P-type control gate in non-volatile storage and methods for forming same |
US9153656B2 (en) | 2013-08-08 | 2015-10-06 | Kabushiki Kaisha Toshiba | NAND type nonvolatile semiconductor memory device and method for manufacturing same |
TWI555066B (zh) * | 2015-05-14 | 2016-10-21 | 力晶科技股份有限公司 | 半導體元件的製作方法 |
EP3381046B1 (de) | 2015-11-23 | 2022-12-28 | Entegris, Inc. | Verfahren zum selektiven ätzen von p-dotiertem polysilicium relativ zu siliciumnitrid |
US9929046B2 (en) | 2016-07-21 | 2018-03-27 | International Business Machines Corporation | Self-aligned contact cap |
FR3069374B1 (fr) | 2017-07-21 | 2020-01-17 | Stmicroelectronics (Rousset) Sas | Transistor mos a effet bosse reduit |
FR3069377B1 (fr) * | 2017-07-21 | 2020-07-03 | Stmicroelectronics (Rousset) Sas | Transistor mos a double blocs de grille a tension de claquage augmentee |
FR3069376B1 (fr) | 2017-07-21 | 2020-07-03 | Stmicroelectronics (Rousset) Sas | Transistor comprenant une grille elargie |
US10468491B1 (en) | 2018-07-03 | 2019-11-05 | International Business Machines Corporation | Low resistance contact for transistors |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5077691A (en) | 1989-10-23 | 1991-12-31 | Advanced Micro Devices, Inc. | Flash EEPROM array with negative gate voltage erase operation |
JP2803548B2 (ja) | 1993-12-28 | 1998-09-24 | 日本電気株式会社 | 半導体装置の製造方法 |
US5470773A (en) | 1994-04-25 | 1995-11-28 | Advanced Micro Devices, Inc. | Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch |
TW295695B (de) | 1994-09-19 | 1997-01-11 | Motorola Inc | |
KR0161402B1 (ko) | 1995-03-22 | 1998-12-01 | 김광호 | 불휘발성 메모리 제조방법 |
WO1998037583A1 (fr) * | 1997-02-20 | 1998-08-27 | Hitachi, Ltd. | Procede pour fabriquer un dispositif a semi-conducteurs |
US5925918A (en) * | 1997-07-30 | 1999-07-20 | Micron, Technology, Inc. | Gate stack with improved sidewall integrity |
JPH1168095A (ja) * | 1997-08-11 | 1999-03-09 | Fujitsu Ltd | 半導体装置の製造方法 |
US6107171A (en) * | 1998-07-09 | 2000-08-22 | Vanguard International Semiconductor Corporation | Method to manufacture metal gate of integrated circuits |
US6074914A (en) | 1998-10-30 | 2000-06-13 | Halo Lsi Design & Device Technology, Inc. | Integration method for sidewall split gate flash transistor |
-
2000
- 2000-08-28 US US09/649,027 patent/US6346467B1/en not_active Expired - Lifetime
- 2000-08-31 CN CNB008133034A patent/CN1192434C/zh not_active Expired - Fee Related
- 2000-08-31 WO PCT/US2000/024271 patent/WO2001017021A1/en active IP Right Grant
- 2000-08-31 DE DE60034369T patent/DE60034369T2/de not_active Expired - Lifetime
- 2000-08-31 AT AT00959866T patent/ATE359601T1/de not_active IP Right Cessation
- 2000-08-31 JP JP2001520468A patent/JP2003531472A/ja active Pending
- 2000-08-31 EP EP00959866A patent/EP1247299B1/de not_active Expired - Lifetime
- 2000-08-31 KR KR1020027002807A patent/KR100773994B1/ko not_active IP Right Cessation
-
2002
- 2002-01-31 US US10/059,119 patent/US20020137284A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20020137284A1 (en) | 2002-09-26 |
CN1192434C (zh) | 2005-03-09 |
DE60034369T2 (de) | 2008-01-10 |
KR100773994B1 (ko) | 2007-11-08 |
EP1247299B1 (de) | 2007-04-11 |
ATE359601T1 (de) | 2007-05-15 |
EP1247299A1 (de) | 2002-10-09 |
JP2003531472A (ja) | 2003-10-21 |
US6346467B1 (en) | 2002-02-12 |
KR20020029772A (ko) | 2002-04-19 |
CN1376309A (zh) | 2002-10-23 |
WO2001017021A1 (en) | 2001-03-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |