DE60031949D1 - Leiterplatte und verfahren zu ihrer herstellung - Google Patents

Leiterplatte und verfahren zu ihrer herstellung

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Publication number
DE60031949D1
DE60031949D1 DE60031949T DE60031949T DE60031949D1 DE 60031949 D1 DE60031949 D1 DE 60031949D1 DE 60031949 T DE60031949 T DE 60031949T DE 60031949 T DE60031949 T DE 60031949T DE 60031949 D1 DE60031949 D1 DE 60031949D1
Authority
DE
Germany
Prior art keywords
pcb
production
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60031949T
Other languages
English (en)
Other versions
DE60031949T2 (de
Inventor
Yasushi Inagaki
Motoo Asai
Dongdong Wang
Hideo Yabashi
Seiji Shirai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Application granted granted Critical
Publication of DE60031949D1 publication Critical patent/DE60031949D1/de
Publication of DE60031949T2 publication Critical patent/DE60031949T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
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    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
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    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
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JP24831199 1999-09-02
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JP2000230868 2000-07-31
JP2000230868 2000-07-31
JP2000230869 2000-07-31
JP2000230870 2000-07-31
JP2000230869 2000-07-31
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