DE60010907D1 - Sram-steuerungvorrichtung für parallele prozessorarchitektur mit adressen- und befehlswarteschlange und arbiter - Google Patents

Sram-steuerungvorrichtung für parallele prozessorarchitektur mit adressen- und befehlswarteschlange und arbiter

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Publication number
DE60010907D1
DE60010907D1 DE60010907T DE60010907T DE60010907D1 DE 60010907 D1 DE60010907 D1 DE 60010907D1 DE 60010907 T DE60010907 T DE 60010907T DE 60010907 T DE60010907 T DE 60010907T DE 60010907 D1 DE60010907 D1 DE 60010907D1
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Germany
Prior art keywords
address
command queue
arbiter
control device
parallel processor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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DE60010907T
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English (en)
Other versions
DE60010907T2 (de
Inventor
J Adiletta
William Wheeler
James Redfield
Daniel Cutter
Gilbert Wolrich
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Intel Corp
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Intel Corp
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Publication of DE60010907D1 publication Critical patent/DE60010907D1/de
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Publication of DE60010907T2 publication Critical patent/DE60010907T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
DE60010907T 1999-08-31 2000-08-17 Sram-steuerungvorrichtung für parallele prozessorarchitektur mit adressen- und befehlswarteschlange und arbiter Expired - Lifetime DE60010907T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US387110 1999-08-31
US09/387,110 US6427196B1 (en) 1999-08-31 1999-08-31 SRAM controller for parallel processor architecture including address and command queue and arbiter
PCT/US2000/022653 WO2001016769A1 (en) 1999-08-31 2000-08-17 Sram controller for parallel processor architecture

Publications (2)

Publication Number Publication Date
DE60010907D1 true DE60010907D1 (de) 2004-06-24
DE60010907T2 DE60010907T2 (de) 2005-07-21

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DE60010907T Expired - Lifetime DE60010907T2 (de) 1999-08-31 2000-08-17 Sram-steuerungvorrichtung für parallele prozessorarchitektur mit adressen- und befehlswarteschlange und arbiter

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US (3) US6427196B1 (de)
EP (1) EP1214660B1 (de)
CN (1) CN1192314C (de)
AT (1) ATE267420T1 (de)
AU (1) AU6646100A (de)
CA (1) CA2391792C (de)
DE (1) DE60010907T2 (de)
HK (1) HK1053728A1 (de)
WO (1) WO2001016769A1 (de)

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US20040162933A1 (en) 2004-08-19
CN1192314C (zh) 2005-03-09
CN1399739A (zh) 2003-02-26
CA2391792C (en) 2004-12-07
ATE267420T1 (de) 2004-06-15
EP1214660B1 (de) 2004-05-19
US6728845B2 (en) 2004-04-27
US6427196B1 (en) 2002-07-30
DE60010907T2 (de) 2005-07-21
EP1214660A1 (de) 2002-06-19
CA2391792A1 (en) 2001-03-08
AU6646100A (en) 2001-03-26
WO2001016769A1 (en) 2001-03-08
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US20030145159A1 (en) 2003-07-31
US7305500B2 (en) 2007-12-04

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