DE59509663D1 - Logischer Block für einen Viterbi-Decoder - Google Patents

Logischer Block für einen Viterbi-Decoder

Info

Publication number
DE59509663D1
DE59509663D1 DE59509663T DE59509663T DE59509663D1 DE 59509663 D1 DE59509663 D1 DE 59509663D1 DE 59509663 T DE59509663 T DE 59509663T DE 59509663 T DE59509663 T DE 59509663T DE 59509663 D1 DE59509663 D1 DE 59509663D1
Authority
DE
Germany
Prior art keywords
logical block
viterbi decoder
viterbi
decoder
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE59509663T
Other languages
English (en)
Inventor
Dr Ing Temerinac
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Entropic Communications LLC
Original Assignee
TDK Micronas GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Micronas GmbH filed Critical TDK Micronas GmbH
Application granted granted Critical
Publication of DE59509663D1 publication Critical patent/DE59509663D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
DE59509663T 1995-10-21 1995-10-21 Logischer Block für einen Viterbi-Decoder Expired - Lifetime DE59509663D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP95116616A EP0769853B1 (de) 1995-10-21 1995-10-21 Logischer Block für einen Viterbi-Decoder

Publications (1)

Publication Number Publication Date
DE59509663D1 true DE59509663D1 (de) 2001-11-08

Family

ID=8219737

Family Applications (1)

Application Number Title Priority Date Filing Date
DE59509663T Expired - Lifetime DE59509663D1 (de) 1995-10-21 1995-10-21 Logischer Block für einen Viterbi-Decoder

Country Status (5)

Country Link
US (1) US5887036A (de)
EP (1) EP0769853B1 (de)
JP (1) JP3784896B2 (de)
KR (1) KR100371950B1 (de)
DE (1) DE59509663D1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6530059B1 (en) * 1998-06-01 2003-03-04 Her Majesty The Queen In Right Of Canada, As Represented By The Minister Of Industry Through The Communication Research Centre Tail-biting turbo-code encoder and associated decoder
US6477680B2 (en) * 1998-06-26 2002-11-05 Agere Systems Inc. Area-efficient convolutional decoder
US6381271B1 (en) * 1998-08-17 2002-04-30 Telefonaktiebolaget Lm Ericsson (Publ) Low complexity decision feedback sequence estimation
US6597743B1 (en) 1999-12-07 2003-07-22 Ericsson Inc. Reduced search symbol estimation algorithm
DE102004038754A1 (de) * 2004-08-09 2006-02-23 Micronas Gmbh Decoder und Verfahren zum Durchführen eines Viterbi-Algorithmus
KR100594043B1 (ko) 2004-11-08 2006-06-30 삼성전자주식회사 고속 터보 디코더에서 병행방식의 디 래이트 매칭을수행하는 입력 버퍼 장치
US20080152044A1 (en) * 2006-12-20 2008-06-26 Media Tek Inc. Veterbi decoding method for convolutionally encoded signal
US8111767B2 (en) * 2007-05-31 2012-02-07 Renesas Electronics Corporation Adaptive sliding block Viterbi decoder
FR2946480B1 (fr) * 2009-06-09 2011-06-17 Thales Sa Recepteur equipe d'un decodeur de viterbi a treillis

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536878A (en) * 1982-09-20 1985-08-20 Sperry Corporation Bit serial convolutional decoder for VLSI implementation
DE3639753A1 (de) * 1986-11-21 1988-06-01 Inst Rundfunktechnik Gmbh Verfahren zum uebertragen digitalisierter tonsignale
US4998253A (en) * 1988-03-11 1991-03-05 Kokusai Denshin Denwa Co., Ltd. Syndrome sequential decoder
US5068859A (en) * 1989-06-19 1991-11-26 California Institute Of Technology Large constraint length high speed viterbi decoder based on a modular hierarchial decomposition of the deBruijn graph
WO1992009144A1 (fr) * 1990-11-19 1992-05-29 Fujitsu Limited Procede de decodage de vraisemblance maximale et dispositif relatif
KR930004862B1 (ko) * 1990-12-17 1993-06-09 삼성전자 주식회사 상태 평가량 기억장치
US5233629A (en) * 1991-07-26 1993-08-03 General Instrument Corporation Method and apparatus for communicating digital data using trellis coded qam
US5416787A (en) * 1991-07-30 1995-05-16 Kabushiki Kaisha Toshiba Method and apparatus for encoding and decoding convolutional codes
US5363408A (en) * 1992-03-24 1994-11-08 General Instrument Corporation Mode selective quadrature amplitude modulation communication system
US5432803A (en) * 1992-04-30 1995-07-11 Novatel Communications, Ltd. Maximum likelihood convolutional decoder
AU5550694A (en) * 1992-11-06 1994-06-08 Pericle Communications Company Adaptive data rate modem
JP3250363B2 (ja) * 1993-05-20 2002-01-28 松下電器産業株式会社 演算装置

Also Published As

Publication number Publication date
EP0769853A1 (de) 1997-04-23
US5887036A (en) 1999-03-23
EP0769853B1 (de) 2001-10-04
JPH09238086A (ja) 1997-09-09
KR970024635A (ko) 1997-05-30
JP3784896B2 (ja) 2006-06-14
KR100371950B1 (ko) 2003-04-10

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