DE59307261D1 - Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects' - Google Patents

Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects'

Info

Publication number
DE59307261D1
DE59307261D1 DE59307261T DE59307261T DE59307261D1 DE 59307261 D1 DE59307261 D1 DE 59307261D1 DE 59307261 T DE59307261 T DE 59307261T DE 59307261 T DE59307261 T DE 59307261T DE 59307261 D1 DE59307261 D1 DE 59307261D1
Authority
DE
Germany
Prior art keywords
semiconductor components
cmos technology
producing semiconductor
local interconnects
interconnects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE59307261T
Other languages
English (en)
Inventor
Klaus Wilmsmeyer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=6461038&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE59307261(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Priority to DE59307261T priority Critical patent/DE59307261D1/de
Application granted granted Critical
Publication of DE59307261D1 publication Critical patent/DE59307261D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
DE59307261T 1992-06-15 1993-06-09 Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects' Expired - Lifetime DE59307261D1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE59307261T DE59307261D1 (de) 1992-06-15 1993-06-09 Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects'

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4219529A DE4219529C2 (de) 1992-06-15 1992-06-15 Verfahren zur Herstellung von Halbleiterbauelementen in CMOS-Technik mit "local interconnects"
PCT/EP1993/001452 WO1993026042A1 (de) 1992-06-15 1993-06-09 Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects'
DE59307261T DE59307261D1 (de) 1992-06-15 1993-06-09 Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects'

Publications (1)

Publication Number Publication Date
DE59307261D1 true DE59307261D1 (de) 1997-10-09

Family

ID=6461038

Family Applications (2)

Application Number Title Priority Date Filing Date
DE4219529A Expired - Fee Related DE4219529C2 (de) 1992-06-15 1992-06-15 Verfahren zur Herstellung von Halbleiterbauelementen in CMOS-Technik mit "local interconnects"
DE59307261T Expired - Lifetime DE59307261D1 (de) 1992-06-15 1993-06-09 Verfahren zur herstellung von halbleiterbauelementen in cmos-technik mit 'local interconnects'

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE4219529A Expired - Fee Related DE4219529C2 (de) 1992-06-15 1992-06-15 Verfahren zur Herstellung von Halbleiterbauelementen in CMOS-Technik mit "local interconnects"

Country Status (5)

Country Link
US (1) US5387535A (de)
EP (1) EP0600063B2 (de)
JP (1) JP3249524B2 (de)
DE (2) DE4219529C2 (de)
WO (1) WO1993026042A1 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5621235A (en) * 1993-01-12 1997-04-15 Texas Instruments Incorporated TiSi2 /TiN clad interconnect technology
US5635426A (en) * 1993-08-26 1997-06-03 Fujitsu Limited Method of making a semiconductor device having a silicide local interconnect
US5482895A (en) * 1993-08-26 1996-01-09 Fujitsu Limited Method of manufacturing semiconductor devices having silicide electrodes
JP2677168B2 (ja) * 1993-09-17 1997-11-17 日本電気株式会社 半導体装置の製造方法
US5849634A (en) * 1994-04-15 1998-12-15 Sharp Kk Method of forming silicide film on silicon with oxygen concentration below 1018 /cm3
JPH08130244A (ja) * 1994-11-02 1996-05-21 Mitsubishi Electric Corp 局所配線の形成方法
JP2630290B2 (ja) * 1995-01-30 1997-07-16 日本電気株式会社 半導体装置の製造方法
KR960042947A (ko) * 1995-05-09 1996-12-21 김주용 고집적 반도체 소자 및 그 국부 연결 방법
US5780362A (en) * 1996-06-04 1998-07-14 Wang; Qingfeng CoSi2 salicide method
US5945350A (en) * 1996-09-13 1999-08-31 Micron Technology, Inc. Methods for use in formation of titanium nitride interconnects and interconnects formed using same
US5830775A (en) * 1996-11-26 1998-11-03 Sharp Microelectronics Technology, Inc. Raised silicided source/drain electrode formation with reduced substrate silicon consumption
JPH10189483A (ja) * 1996-12-26 1998-07-21 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
KR100440075B1 (ko) * 1996-12-31 2004-10-08 주식회사 하이닉스반도체 반도체소자의트랜지스터제조방법
US6153452A (en) * 1997-01-07 2000-11-28 Lucent Technologies Inc. Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure
US6221766B1 (en) 1997-01-24 2001-04-24 Steag Rtp Systems, Inc. Method and apparatus for processing refractory metals on semiconductor substrates
TW329553B (en) * 1997-02-04 1998-04-11 Winbond Electronics Corp The semiconductor manufacturing process for two-step salicide
US6458711B1 (en) * 1997-03-20 2002-10-01 Texas Instruments Incorporated Self-aligned silicide process
US6562724B1 (en) * 1997-06-09 2003-05-13 Texas Instruments Incorporated Self-aligned stack formation
KR100247933B1 (ko) 1997-08-22 2000-03-15 윤종용 버티드 콘택을 갖는 반도체 소자 및 그 제조방법
US5920796A (en) * 1997-09-05 1999-07-06 Advanced Micro Devices, Inc. In-situ etch of BARC layer during formation of local interconnects
US6153933A (en) * 1997-09-05 2000-11-28 Advanced Micro Devices, Inc. Elimination of residual materials in a multiple-layer interconnect structure
US6060328A (en) 1997-09-05 2000-05-09 Advanced Micro Devices, Inc. Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process
US6060404A (en) * 1997-09-05 2000-05-09 Advanced Micro Devices, Inc. In-situ deposition of stop layer and dielectric layer during formation of local interconnects
US6114235A (en) * 1997-09-05 2000-09-05 Advanced Micro Devices, Inc. Multipurpose cap layer dielectric
TW368731B (en) * 1997-12-22 1999-09-01 United Microelectronics Corp Manufacturing method for self-aligned local-interconnect and contact
US6156615A (en) * 1998-09-30 2000-12-05 Advanced Micro Devices, Inc. Method for decreasing the contact resistance of silicide contacts by retrograde implantation of source/drain regions
US6429124B1 (en) * 1999-04-14 2002-08-06 Micron Technology, Inc. Local interconnect structures for integrated circuits and methods for making the same
US6372668B2 (en) 2000-01-18 2002-04-16 Advanced Micro Devices, Inc. Method of forming silicon oxynitride films
US6365512B1 (en) * 2000-06-21 2002-04-02 Infineon Technologies Ag Method and apparatus for a direct buried strap for same level contact interconnections for semiconductor devices
US6765269B2 (en) * 2001-01-26 2004-07-20 Integrated Device Technology, Inc. Conformal surface silicide strap on spacer and method of making same
KR100465876B1 (ko) * 2002-07-25 2005-01-13 삼성전자주식회사 반도체 소자 실리사이드 배선 형성방법
US20080251878A1 (en) * 2007-04-13 2008-10-16 International Business Machines Corporation Structure incorporating semiconductor device structures for use in sram devices
US20080251934A1 (en) * 2007-04-13 2008-10-16 Jack Allan Mandelman Semiconductor Device Structures and Methods of Fabricating Semiconductor Device Structures for Use in SRAM Devices
CN109980011A (zh) * 2017-12-28 2019-07-05 无锡华润上华科技有限公司 一种半导体器件及其制作方法
CN111092123A (zh) * 2019-12-10 2020-05-01 杰华特微电子（杭州）有限公司 横向双扩散晶体管及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873204A (en) * 1984-06-15 1989-10-10 Hewlett-Packard Company Method for making silicide interconnection structures for integrated circuit devices
US5010032A (en) * 1985-05-01 1991-04-23 Texas Instruments Incorporated Process for making CMOS device with both P+ and N+ gates including refractory metal silicide and nitride interconnects
US4876213A (en) * 1988-10-31 1989-10-24 Motorola, Inc. Salicided source/drain structure
US5023201A (en) * 1990-08-30 1991-06-11 Cornell Research Foundation, Inc. Selective deposition of tungsten on TiSi2
EP0499855A3 (en) * 1991-02-21 1992-10-28 Texas Instruments Incorporated Method and structure for microelectronic device incorporating low-resistivity straps between conductive regions

Also Published As

Publication number Publication date
JPH07501426A (ja) 1995-02-09
US5387535A (en) 1995-02-07
EP0600063B1 (de) 1997-09-03
JP3249524B2 (ja) 2002-01-21
EP0600063A1 (de) 1994-06-08
EP0600063B2 (de) 2002-07-10
DE4219529C2 (de) 1994-05-26
WO1993026042A1 (de) 1993-12-23
DE4219529A1 (de) 1993-12-16

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8327 Change in the person/name/address of the patent owner

Owner name: MICRONAS INTERMETALL GMBH, 79108 FREIBURG, DE

8327 Change in the person/name/address of the patent owner

Owner name: MICRONAS GMBH, 79108 FREIBURG, DE

8366 Restricted maintained after opposition proceedings
8320 Willingness to grant licences declared (paragraph 23)