DE4419762A1 - Component with grown and deposited two-film gate oxide and method for its production - Google Patents

Abstract

The present invention discloses a method for forming an oxide thin film such as, for example, a gate oxide layer, on a semiconductor, which includes the use of thermal growth techniques for growing a lower oxide film on the semiconductor, and uses the deposition techniques for growing an upper oxide film on the lower, grown oxide film. The two oxide films are formed in an environment containing dinitrogen monoxide. Nitrogen is incorporated on the semiconductor/oxide interface, as a result of which the number of unpaired bonds on the interface is reduced. While a silicon-containing gas is fed during formation of the upper, deposited film, the temperatures and gases used to form the two films produce a desired interface at the junction of the films. The oxide films, arranged one above the other, are then annealed at a temperature similar to that used during the film production. An electrode such as, for example, a gate region, can then be produced on the two-film layer.

Description

The present invention relates generally to Method for producing a semiconductor component and especially on gate oxide layers.

In the manufacture of integrated circuit chips a thin dielectric layer on a semiconductor sub strat formed to the substrate electrically from the elec tread such. B. isolate the gate regions. With to increasing miniaturization of transistors and other construction elements of an integrated circuit to the number of Components within a group area of the semiconductor to increase the substrate, the layers with respect to their Thickness and with regard to their lateral dimensions redu graces. High quality thin dielectric layers play an important role in optimizing behavior VLSI and ULSI circuits (VLSI = Very Large-Scale Integration = very high degree of integration; ULSI = Ultra Large-scale integration = ultra high degree of integration).

Although sometimes dielectric materials to form one Gate oxide layer for a field effect transistor (FET) ver are used, typically silicon oxide (SiO₂) ver turns. Ideally, the gate oxide layer is the same moderate thickness. Finest holes and other defects will be However, adversely affect the behavior of the component, after even a small change in dielectric thickness will affect the gate capacitance.  

A phenomenon that can be described as trapping "hot carriers" is the quality of a gate oxide layer also assigned. Electrons in a silicon substrate can be generated by a component effect get enough energy to break the barrier between that To overcome silicon and the oxide layer, and are in trapped in the oxide layer, trapped charges are in a slow, long-term change in the threshold span of a FET device result. U.S. Patent No. 5,153,709 teaches that the threshold voltage change per is proportional to the charge / capacity captured, and teaches that the charge capture and those caused by defects dielectric breakthroughs the scaling limits for thin Adjust oxide layers. The component recovers the length of days at a rate that is of quality depends on the oxide layer.

It is the object of the present invention, a method to form a thin oxide layer, such as. B. a gate Oxides, which create reliability with regard to hotter Carrier and the time-dependent dielectric breakdown characteristics of such a layer improved, and a To create a semiconductor device according to this method is made.

This object is achieved by a method according to claim 1 and Claim 11, and by a semiconductor device according to An Proverb 16 solved.

The present invention forms a two-film oxide layer which is a thermally grown lower oxide, the stick material at a silicon / silicon oxide interface closes, and a deposited top substrate that the Increased thickness of the oxide layer to a usable range, includes.

In a first step, a silicon oxide film (SiO₂ film) on a semiconductor substrate in a nitrous oxide  containing environment grew up. "Grown up thermally" is defined here as the formation of the oxide in a way primarily from the oxidation of the silicon substrate itself depends. Traditionally, thermal oxidation performed by the silicon dry oxygen or Exposed to water vapor. The chemical reaction at the Silicon surface if dry oxygen is used reads:

Si + O₂ → SiO₂.

By using nitrous oxide N₂O a small Quantity of nitrogen installed at the Si / SiO₂ interface.

The thermally grown oxide is increased at an Temperature formed, preferably within the range from 800 ° C to 1000 ° C. The thermal growth takes place with increasing thickness of the silicon oxide with a steadily decreasing increasing rate.

The top oxide is "deposited", i.e. H. in a way does not form primarily from a chemical reaction the silicon surface is dependent. It is preferred the upper oxide using low pressure gas phases deposition techniques formed. A silicon-containing one Gas is introduced into an N₂O environment around a silicon to form oxide. The process preferably takes place at a temperature equal to or less than the temperature which used in the thermal growth of the lower oxide has been. A desirable silicon-containing gas is Dichlorosilane, so the chemical reaction is as follows:

SiH₂Cl₂ + 2N₂O → SiO₂ + 2HCl + 2N₂.

The stacked oxides are then cured, to reduce the frequency of defects. The healing temperature is preferably in a range that the when thermally growing and when separating  other arranged oxides is similar. The healing is in a nitrogen-containing environment, e.g. B. N₂O or N₂ reached, but it can also be used O₂. The over mutually arranged oxides can then be structured and a gate region can be on the patterned oxides be formed.

An advantage of the present invention is that by incorporating nitrogen at the Si / SiO₂ interface the number of loose ties can be significantly reduced can. The more stable SiO₂ film in the N₂O environment was compared to the oxides contained in O₂ or H₂O environments were raised, the number of Charge states. As a result, reliability is related Lich the hot carrier and the time-dependent dielectric Breakthrough characteristics improved.

The use of the N₂O-grown oxide is due to the The fact that the growth of such a film is self-evident is restrictive. In ULSI applications this can Oxide growth with a thickness in the range of 2-4 nm to be finished. The upper oxide layer is then removed divorced. A second advantage of the present invention is that the deposited oxide makes sense Thickness area created. With regard to ULSI applications, this can deposited oxide a thickness in the range of 4-10 nm to have. Another advantage is that the top, deposited oxide any defects in the lower one, up growing oxide caused by substrate defects or by Verun cleaning have been caused.

When the upper, deposited oxide is formed, the ver Ratio of nitrous oxide to dichlorosilane more preferred wise at least 2: 1 and optimally around 3: 1. Because nitrous oxide is predominant, the Oxide growth and deposition steps with respect to both the atmosphere as well as the temperature in a similar way executed. Another advantage of the present  Invention is that at the transition of the two oxide films a desirable interface is created.

A preferred embodiment of the present invention below is with reference to the accompanying Drawings explained in more detail. Show it

FIG. 1 is a cross-sectional view of a portion of a semiconductor wafer with field oxide regions;

FIG. 2 shows a cross-sectional illustration of the semiconductor substrate from FIG. 1 during the thermal growth of a lower oxide film;

Fig. 3 is a cross sectional view of the semiconductor substrate of Figure 2 during the deposition of an upper oxide film.

FIG. 4 shows a cross-sectional illustration of the semiconductor substrate from FIG. 3 with an electrically conductive region that is structured on the oxide film; FIG. and

FIG. 5 shows a cross-sectional illustration of the semiconductor substrate from FIG. 4, which has source / drain regions formed therein.

In Fig. 1, a semiconductor substrate 10 is shown, the field oxide regions 12 and 14 having the electrically insulating an island 16 from the rest of the substrate. The field oxide regions can be formed using a local oxidation of silicon (LOCOS) approach, or side wall masked isolation (SWAMI) approach, or any other approach known in the art. The island 16 is used to form an integrated circuit device, such as. B. a transistor, isolated.

The semiconductor substrate 10 is typically a silicon wafer. The electrodes of a transistor can be formed in the wafer or can be fabricated over the surface of the wafer. Conventionally, field effect transistors have source and drain regions in the semiconductor substrate and an electrode region formed on the top of the substrate. A dielectric layer is used to isolate the gate region from the substrate. This particular dielectric layer is referred to as a gate oxide layer, but the method described below can be used to form other dielectric layers on the substrate.

In the first step, which is shown in FIG. 2, a thermal oxide 18 is grown on the surface of the semiconductor wafer. In a preferred embodiment, the level of temperature associated with the thermal growth process is maintained within the range of 800 ° C to 1000 ° C. An oxygen-containing gas is introduced to start the oxidation. In order to incorporate nitrogen at the silicon / oxide interface 20 , N₂O is used as the gas containing oxygen. In Fig. 2 the level of temperature is represented by lines 22, while the flow of N₂O is represented by arrow 24 .

The installation of nitrogen at the silicon / oxide interface reduces the number of loose ties on the cut Job. Consequently, the reliability in terms of are called carriers and the time-dependent dielectric through fracture characteristics improved. With increasingly thinner who Oxides in VLSI and ULSI circuits generate the Hot-carrier effects a slow, long-term change in Threshold voltage of transistors. By reducing the loose bonds through the incorporation of nitrogen Long-term stability increased.

The thermal growth of silicon oxide, SiO₂, to form the thermal oxide film 18 is self-limiting. The process slows down as the thickness of the thermal oxide increases. A thickness in the range of 2-4 nm is sufficient to form the thermal oxide.

In Fig. 3, an upper silicon oxide film 26 is formed on the lower, thermally grown oxide 18 . In a preferred embodiment, the deposited oxide 20 is formed using the low pressure vapor deposition (LPCVD) at an elevated temperature that is less than or equal to the temperature used in growing the thermal oxide 18 . As a result, the temperature in the preferred embodiment would not exceed 1000 ° C. An acceptable pressure during the LPCVD process is 0.6 mTorr, but this is not a required feature.

Lines 28 show that the level of temperature is less than or equal to that used in the growth of thermal oxide 18 , while a first arrow 30 represents a flow of N₂O and a second arrow 32 a flow of silicon-containing gas represents. Although not a required feature, the silicon-containing gas is preferably dichlorosilane. The concentration of nitrous oxide 30 is preferably greater than the flow of dichlorosilane. A 2: 1 ratio of nitrous oxide to dichlorosilane is preferred, and a ratio of about 3: 1 is optimal. The flow rate 30 of nitrous oxide can be 210 cc / m, while the flow of dichlorosilane can be 70 cc / m.

Due to the fact that the nitrous oxide is the predominant gas and because the temperature used in forming the upper oxide film 26 is compatible with that for forming the thermal oxide 18 , the interface between the two silicon oxide films is desirable. The upper deposited oxide 26 increases the thickness of the resulting gate oxide structure to a reasonable range. The deposited oxide 26 can have a thickness in the range of 4-10 nm. In addition, the deposited oxide 26 is effective to shield the influences of the N₂O-grown thermal oxide 18 , which are caused by defects or contamination at the level of the semiconductor substrate 10 . With decreasing gate oxide thickness, such defects are typically more problematic with thermally grown oxides.

The superimposed oxides 18 and 26 are then cured in a N₂O, O₂ or N₂ environment in a temperature range that is similar to that in the formation of the oxides. Healing further reduces the likelihood of behavioral defects within the gate oxide layer. The curing is preferably carried out in one of the nitrogen-containing gases mentioned above.

In FIG. 4, a gate region 40 was fabricated on a two-film gate oxide layer 34 , which consists of the grown oxide 18 and the deposited oxide 26 . Typically, a polysilicon layer is deposited and structured to form the gate region 40 . The patterning of the gate region 40 can be accomplished using photolithographic techniques for exposing and developing a photo resist, the developed photoresist protecting the gate and the gate oxide layer from removal by a subsequent etching step. The developed photoresist is then removed. Ion implantation or other known techniques can then be used to dope the exposed regions of the semiconductor substrate 10 to form the source / drain regions 36 and 38 , as shown in FIG. 5.

Although the present invention has been described as such in which a gate oxide layer is formed, the two-film dielectric layer can be used in other applications in which a thin dielectric layer is to be formed on a semiconductor. In Fig. 4 z. B. a thin dielectric layer 4 , which comprises a grown oxide 18 and a deposited oxide 26 , who who to isolate a semiconductor substrate 10 from an electrical connection 40 .

Claims (18)

1. A method for forming an oxide layer ( 34 ) on a semiconductor, comprising the following steps:
Providing a silicon substrate ( 10 );
thermally growing a lower oxide film ( 18 ) on the silicon substrate ( 10 ) in an environment ( 24 ) containing nitrous oxide, thereby forming a nitrogen-containing silicon / oxide interface ( 20 ); and
Depositing an upper oxide film ( 26 ) on the lower oxide film ( 18 ) in a silicon-containing and nitrogen oxide-containing environment ( 30 , 32 ). 2. The method of claim 1, further comprising forming a gate region ( 40 ) on the top oxide film ( 26 ). 3. The method of claim 1 or 2, wherein depositing the top oxide film ( 26 ) is a step of depositing a silicon oxide film from the gas phase. 4. The method of any one of claims 1 to 3, further comprising annealing the upper and lower oxide films ( 18 , 26 ) after depositing the upper oxide film ( 26 ). 5. The method according to any one of claims 1 to 4, wherein the thermal growth of the lower oxide film ( 18 ) and the deposition of the upper oxide film ( 26 ) are carried out in an N₂O environment. 6. The method according to any one of claims 1 to 5, wherein the thermal growth of the lower oxide film ( 18 ) and the deposition of the upper oxide film ( 26 ) is carried out at a temperature in the range of 800 ° C to 1000 ° C. 7. The method of claim 6, wherein the thermal growth of the lower oxide film ( 18 ) and the deposition of the upper oxide film ( 26 ) are carried out to form a common thickness of less than 15 nm. 8. The method of claim 7, wherein the lower oxide film ( 18 ) has a thickness of less than 5 nm. 9. The method according to any one of claims 1 to 8, wherein the deposition of the upper oxide film ( 26 ) is a step which is carried out in a SiH₂Cl₂ gas flow and in an N₂O gas flow. 10. The method according to any one of claims 1 to 9, in which the Ratio of the SiH₂Cl₂ gas flow to the N₂O gas flow is at least 2: 1. 11. A method for forming a gate region on a semiconductor device, with the following steps:
Providing a silicon substrate ( 10 );
Applying thermal growth techniques to grow a first oxide ( 18 ) on the silicon substrate ( 10 ), including raising the temperature above the silicon substrate ( 10 ) to a first temperature and including introducing N₂O gas into the atmosphere;
Applying gas phase deposition techniques to deposit a second oxide ( 26 ) on the first oxide ( 18 ), including maintaining the atmosphere over the silicon substrate ( 10 ) at a maximum temperature that does not exceed the first temperature and including introducing N₂O gas and a silicon-containing gas into the atmosphere; and
Forming a gate ( 40 ) on the second oxide ( 26 ). 12. The method of claim 11, further comprising annealing the first and second oxides ( 18 , 26 ) prior to forming the gate ( 40 ), the annealing occurring at a maximum temperature that does not exceed the first temperature. 13. The method of claim 11 or 12, wherein the Si silicon-containing gas is dichlorosilane, the one Concentration that is less than the Kon concentration of the N₂O gas. 14. The method according to any one of claims 11 to 13, wherein the first and the second oxide ( 18 , 26 ) are formed with a common thickness of less than 15 nm. 15. The method according to any one of claims 12 to 14, in which healing in an environment of nitrogen ent holding gas is running. 16. Semiconductor component, with:
a silicon substrate ( 10 );
a thermally grown silicon oxide film ( 18 ) on the silicon substrate ( 10 ), an interface of the silicon substrate ( 10 ) with the thermally grown silicon oxide ( 18 ) having a concentration of nitrogen;
a deposited silicon oxide film ( 26 ) on the thermally grown silicon oxide film ( 18 ); and
a gate region ( 40 ) on the deposited silicon oxide film ( 26 ). 17. The component according to claim 16, wherein the silicon substrate ( 10 ) has source / drain regions ( 36 , 38 ) on opposite sides of the thermally grown silicon oxide ( 18 ). 18. The component according to claim 16 or 17, wherein the thermally grown and the deposited silicon oxide film ( 18 , 26 ) have a common thickness of less than 15 nm.