DE4404129C2 - Method of manufacturing a multi-pin conductive structure - Google Patents

Description

The present invention relates to a method for producing in high-density DRAM (Dynamic Random Access Memory) Arrangements) used three-dimensional stacked cell capacitors goals. In particular, the invention relates to a method of manufacturing one, multi-pin conductive structure on which exist the topography of a starting substrate.

In dynamic semiconductor memory devices, it is essential that the cell plates of the storage node capacitors are large enough to to maintain an adequate charge. As with most inte semiconductor semiconductor circuits is the case, the circuit density decreases at a fairly constant rate. The point of view of the Maintaining storage node capacity is particularly important tion, since the density of DRAM devices for future generations storage devices continues to increase.

The ability to pack memory cells tightly while doing the necessary Maintaining capacity levels is a key requirement Semiconductor manufacturing technologies when future generations expand terter storage devices are to be successfully manufactured.

A method of maintaining and increasing memory node size in densely packed storage devices is in the Use of the "stack memory cell" structure. With this technology two or more layers of a conductive material, such as. B. polycrystalline silicon (hereinafter referred to as polysilicon), about an access device is applied to a silicon wafer, wherein dielectric layers sandwiched between each polysilicon layer  to be ordered. A cell designed in this way is under the Designation stacked capacitor cell (STC) known. Such a cell uses the space above the capacitor plate access device, has a low soft error rate (SER) and can connect with high insulating layers between the plates Dielectric constant can be used.

However, it is difficult with a conventional STC capacitor to achieve sufficient storage capacity because the storage elec area on the limits of its own cell area is restricted. Also maintaining good dielectri dielectric strength between polysilicon layers in the STC capacitor becomes a big problem once the thickness of the isola tors is appropriately dimensioned.

A study by J.H. Ahn et al. submitted article entitled "Micro Villus Patterning (MVP) Technology for 256Mb DRAM Stack Cell ", 1992 IEEE, 1992 Symposium on VLSI Technology Digest of Technical Papers, pages 12 and 13, by reference to an ingredient of the present application discusses the technology of Micro villus patterning (MVP or Micro Villus Patterning) for Development of a three-dimensional stack capacitor in the Storage node cell plate built-in vertical villi-like bars or pens.

However, the use of the MVP technology can lead to splinter problems (or flaking) in the storage node polysilicon if the MVP technology is used to form three-dimensional stack capacitors in the manner described by the cited document. As shown in FIG. 5, parallel word lines 12 have been produced on a silicon wafer 10 in cross section. Storage nodes 13 (which make contact with active areas 11 ) have been formed from storage node polysilicon 14 and polysilicon micro villus rods or pins 15. As can be seen in this cross-section, the micro villi pins 15 are prone to splintering, which can result in overturning polysilicon chips, which could cause a short circuit to adjacent storage node polysilicon, thereby short-circuiting the adjacent memory cells and thereby rendering them unusable. When using hemispherical grain polysilicon, as is the case in Figure 8, the variable grain size also results in variable pin diameters, with a percentage of these pins having diameters less than 0.0100 µm which are even more susceptible to breakage and splintering .

If e.g. B. in a 64 Mb DRAM only one in 100,000 cells one Would have short circuit due to such splintering this results in 640 statistical errors in the 64 Mb DRAM, where these are more errors than could be repaired. As for the repair Only a limited number of redundant elements are available stands, the entire storage device would be unusable.

From the document DE-A1-42 22 584 is a process for the manufacture development of semiconductor devices known. This known method includes the following steps: applying one made of hemispherical particles existing layer with elevations and depressions towards a first one etching layer, the consisting of hemispherical particles Layer has a higher etching selectivity than the first layer; Off fill the wells of the hemispherical particles Layer with a second layer, which has a higher etching selectivity points as the layer consisting of hemispherical particles, and Etching off the elevations of which consist of hemispherical particles the layer using a second layer as a mask to cover the expose the first layer and then etch the first Layer. Due to the alternating increases and decreases in layer consisting of hemispherical particles can with the known method achieved a hyperfine structure of about 0.1 microns become.

Furthermore, the known method can be carried out in such a way that a semiconductor device with transistors and buried bit lines a nitride layer is applied, which is then etched off so that it partially preserved in the capacitor zones. Then the  known methods on the entire surface of a storage node Polysilicon layer applied to create a flat upper surface len. The storage node polysilicon layer is then etched to remove the parts of the nitride layer located in the capacitor insulation zones to expose. After that, one is placed on the entire exposed surface polysilicon layer consisting of hemispherical particles so applied brings that it has alternating ridges and valleys. The depressions of the hemispherical particles The layer is then filled with an insulating layer. Stick to it the tops of all the elevations of the best of hemispherical particles layer uncovered. After that, the exposed ones are raised Parts of the layer consisting of hemispherical particles and the Storage node polysilicon layer down to a predetermined depth etched, with the recessed portions of the hemispherical particles existing layer filled insulating layer is used as a mask. The nitride arranged in the capacitor insulation zones serves for this purpose layer as an etch stop. After removing the remaining insulation layer and the nitride layer are used to manufacture a capacitor a dielectric layer on the entire top surface one after the other and an overlay of polysilicon is applied.

From the essay by Kaga, T. et al .: "Crown-Shaped Stacked-Capacitor Cell for 1.5-V Operation 64-Mb DRAMs ", IEEE Transactions On Electron Devices, vol. 38, February 2, 1991, pages 255 to 260 a self-aligned stacked capacitor memory cell and an ent speaking manufacturing process known. This publication shows in particular manufacturing steps for a double wall electrode structure door.

Methods for forming are disclosed in U.S. Patents 5,162,248 and 5,061,650 of container-like storage node cells.

It is therefore an object of the invention to provide a method to Memory cell capacity using such technologies as MVP technology, while increasing that with the split  problems associated with the storage node polysilicon are.

This object is achieved by a method with the in Features specified claim 1 solved. The subordinate claims 2 to 4 are further developments of the subject matter of the claims to which they are related.

The present invention develops conductive structures that are suitable for Have storage node electrodes used for storage cells.

The invention and further developments of the invention are as follows based on the drawings of several embodiments explained in more detail. The drawing shows:

Figs. 1-4 are cross-sectional views showing the results of process steps performed in the second embodiment of the present invention;

Figure 5 is a cross-sectional view of a polysilicon storage node developed using micro villi technology.

The present invention is directed to maximizing the memory cell surface area in a manufacturing process for manufacturing high density / large volume DRAMs, as shown in FIGS. 1-4 .

A silicon wafer is manufactured using conventional manufacturing steps to the point where a capacitor cell is defined. At this point, the manufacture of word lines, associated active areas and optional digits completed for a capacitor over a digit line flow  sen (the invention can also be used in stacked capacitor cells with condensers gate under the digit line flows). The procedure steps of the various embodiments of the present invention are explained below.

Figs. 1 to 4 show an embodiment of method steps illustrating the present invention in a series of cross-sectional views through parallel word lines and starting from a cross-sectional view through the word lines.

In the embodiment, as shown in FIG. 1, word lines 25 extend between active regions 21 , which have been formed in a substrate 20 , to thereby form active transistors. The word lines 25 include a conductive layer 22 , which is covered with dielectric 24 and is surrounded by dielectric elements 23 from . A dielectric 27 has been applied and planar, after which a dielectric layer 28 is applied (with nitride being preferred). A layer of dielectric material 29 (oxide is preferred) is deposited and planar, followed by contact / container exposure and etching to create a contact / container opening 51 to thereby access the active one To create area 21 . After the contact / container opening 51 has been formed , a polysilicon layer 52 doped in place is applied such that the contact / container opening 51 is completely filled. The polysilicon 52 is then formed planar (preferably by chemical-mechanical planarization); in such a way that the adjacent storage nodes are separated from one another. Next, the polysilicon 52 is etched to form its planar surface recessed so that it lies under the planar surface of the oxide 29 . The next step is to apply an oxide layer 53 with a thickness of approximately 0.1 μm to cover the oxide 29 and the recessed polysilicon 52 .

Referring to Fig. 2A, a layer of hemispherical grain polysilicon 54 is deposited and then partially etched, with polysilicon plasma etching on the hemispherical grain polysilicon 54 so that 53 silicon remains with a jagged surface over the oxide.

Referring to Fig. 2B of the rugged surface to the underlying oxide layer 53 is used for transmitting an oxide plasma etch process performed. The oxide plasma etching process on the oxide layer 53 leads not only to the transfer of the fissured surface to the oxide 53 , but also to the formation of oxide spacers 55 .

Referring to FIG. 3, a timed polysilicon etch is performed for a sufficient length of time to sufficiently overhang an "archipelago" pattern on polysilicon 52 . It is important that the oxide etch is also timed prior to the timed polysilicon etch so that the oxide etch does not penetrate through the spacer oxide. The transfer of the "archipelago" pattern to the polysilicon around 52 leads to the production of very thin villi-like polysilicon pins 61 , which form a storage node polysilicon structure 63 having a multiplicity of pins. In addition, a continuous polysilicon can 62 is formed which surrounds the villous pins 61 and prevents any of the villous polysilicon pins from falling over and causing a short circuit with any adjacent cell of the present invention. Next, hydrofluoric acid-based etching may optionally be performed to gain the outer surface of the storage node for an increase in surface area.

As can be seen in FIG. 4, a cell dielectric 71 is applied over the storage node polysilicon 63 , followed by the application of polysilicon 72 to thereby form the second capacitor electrode. From this point on, conventional method steps are used to complete the semiconductor device.

Although the preferred cell dielectric is nitride, any material with a high dielectric constant, e.g. B. Ta ₂ O ₅ or SrTiO ₃ can be used. For the exemplary embodiment of the present invention described above and for any modifications thereof, the polysilicon deposited to form the second cell plate of the capacitor is doped conductively, either n-type or p-type, this being different from that for the active region 21 desired conductivity type is dependent. From this point, conventional method steps are carried out to complete the semiconductor device.

Claims (4)

1. A method for producing a conductive structure having several pins on the existing topography of an initial substrate, with the following steps:

• a) forming a full-surface first, second and third insulating layer ( 27 , 28 and 29 ) over the existing topography;
• b) patterning and etching an opening ( 30 ) in the first, second and third insulating layers ( 27 , 28 and 29 );
• c) forming and planarizing a conductive layer ( 52 ) while filling the opening;
• d) making a recess ( 51 ) in the planarized conductive layer ( 52 );
• e) forming a full-surface fourth insulating layer ( 53 ) over the recessed, planarized conductive layer ( 52 ) and the third insulating layer ( 29 );
• f) forming a rugged surface layer ( 54 ) over the fourth insulating layer ( 53 ) by depositing silicon with hemispherical grain;
• g) transferring a pattern over the rugged surface layer ( 54 ) to the recessed, planarized conductive layer ( 52 ) and forming a peripheral wall ( 55 ) around it; and
• h) Forming pins ( 61 ) to create the multiple pins on the conductive structure.

2. The method according to claim 1, characterized in that the formation of the conductive layer ( 52 ) includes the application of a locally doped polysilicon layer and the training of the fourth insulating layer ( 53 ) includes the formation of an oxide layer. 3. The method according to claim 1 or 2, characterized in that the transfer of the pattern to the planarized conductive layer ( 52 ) comprises the following steps:

• a) performing a polysilicon plasma etch on the polysilicon ( 54 ) with hemispherical grain;
• b) performing an oxide plasma etch on the fourth insulating layer ( 53 ); and
• c) performing a timed polysilicon etch on the planarized conductive layer ( 54 ).

4. The method according to any one of claims 1 to 3, characterized in that the planarization of the conductive layer ( 52 ) is carried out by chemical-mechanical planarization.