DE4302057C2 - Process for digitizing a band-limited analog signal and analog-digital processing unit - Google Patents

Description

The invention relates to a method for digitizing a band-limited analog signal and an analog-digital ver unit of work.

A method and a device are known from US Pat. No. 4,625,240 device known to process compressed audio signals, and by adaptive control of the gain of the device. A temporal mean of digital signals is also included compared to a reference value to gain control generate signal. An input video signal with a variable Am plitude is automatically created for a fixed analog-digital wall adapted to the learning area.

EP-A-492 578 describes a method for digital filtering indicated by digital signals, the digital signals with the filter coefficients in assigned storage units mul be duplicated and by addressing all memory units with a digital signal and time delay filing the values to a summation unit be tert.

The invention is more analogous in particular to processing Speech signals directed, for example for digitally working Hearing aids, and has the goal of a process for digitization a band-limited analog signal or an analog Specify digital processing unit in which an analog Digital quantizer with a reduced number of quantization stages  can be used, the dynamics of speech signals from un approximately 80 dB, the analog signal essentially retained is and despite the few quantization levels the Quantization error, based on the useful signal, small remains.

Due to the possibility of quantizing the quantizer To reduce the number of stages can be a significant reduction achieve the necessary services to be installed.

The solution according to the invention consists in a method for Digitization of the band-limited analog signal with the Features of claim 1 and an analog-digital processing specify unit with the features of claim 8. Before partial further training of the procedure and the processing tion unit according to the invention are in the subclaims specified.

The invention is described below based on the description of Embodiments and with reference to the accompanying the figures of the drawings explained.

This description also gives rise to other advantages of the lie invention in its various aspects.

Show it

Fig. 1 is a simplified functional block signal flow diagram of an analog-digital processing unit according to the invention;

Fig. 2 shows a preferred embodiment of the reinforcement control feedback, as used in the processing unit of FIG. 1;

Fig. 3a shows a first embodiment of the analog-digital processing unit shown in principle with reference to Figures 1 and 2 using a simplified func onsblock signal flow diagram.

Figure 3b is a further preferred embodiment of the processing unit according to Fig 1 as well as Figures 3a provided for storage and Skalie approximation unit in schematic form with reference to a functional block...;

Fig. 4 shows a preferred embodiment of a storage and conversion unit for analog-to-digital proces beitungseinheit according to Figs 1 and 2 using a simplified functional block signal flow diagram.

Fig. 5 is a simplified representation of the memory content of a memory device in the unit as shown in Fig. 4 and the function as a downstream, shift register-like unit;

Fig. 6 shows a quantizer characteristic of a quantizer processing unit preferably used in the inventive analog-to-digital proces;

FIG. 7 shows a preferred embodiment of the shift register like action unit according to Figures 4 and 5.

Fig. 8 shows a digital filter arrangement in the form of a simplified functional block signal flow diagram; and

Fig. 9 based on a simplified functional block signal flow diagram, a further embodiment of the analog-digital processing unit, in particular for use with audio signals, in particular with voice signals, the digital filter according to FIG. 8 being connected downstream of the unit according to FIG. 5.

In Fig. 1, a signal flow / functional block diagram of an embodiment of the analog-digital processing unit is provided.

The analog signal 1 is fed to an amplifier unit 3 , the gain G of which can be set in stages in a controlled manner. The amplified output signal of the amplifier unit 3 is fed to an analog-digital quantizer 5 , the digital output signal A _{5 of which leads} on the one hand to a storage and scaling unit 7 , and on the other hand to a storage device 9 for gain control data, for. B. in the form of the word GCW.

Basically, the digital output signals A _{5 of} the quantizer 5 are fed back to the memory device 9 as the actual value, the memory data for the gain G of the amplifier unit 3 being continuously adjusted such that the output values A _{5 of} the quantizer 5 , more precisely: their mean absolute value corresponds to a specifiable target value, with which the limited range of values of the quantizer 5 is optimally used. This is shown schematically in FIG. 1 with the difference forming unit 10 forming the rule difference Δ. The gain values G and their adjustment values ΔG are preferably calculated in dB.

In the storage and scaling unit 7 , all possible values of the output signal A _{5 are} stored in advance, and they are also predetermined, with all possible values of the inverse gain G, ie G ^-1 scaled. If the output signal A ₅ can therefore assume the number n _{a of} different values and the amplification G the number n _g , then the number n _a is in the storage and scaling unit. n _g values predefined, at least partially stored in advance, as represented by the input P. The output signals A _{5 of} the quantizer 5 are present as an address at the input E _{71 of} the storage and scaling unit 7 , and the GCW is also present at E ₇₅₂ . Corresponding to the current value of the signal A ₅ , the associated data set, scaled with the current inverse gain G ^-1 , is addressed at the unit 7 . From the output side A _{7 of} the storage and scaling unit 7 , the numerical value of the (unamplified or unattenuated) analog signal 1 appears .

Thanks to the input side reinforcement, prior to Digi capitalization, and the output side, taking place after the digitization gain compensation is a quantizer 5 with few quantization step the full dynamic range of the analog signal in the range of numbers displayed.

Due to the adjustment of the mean absolute value of the output signal A _{5 of} the quantizer 5 to a predetermined setpoint value, the available dynamics of the quantizer are fully utilized and thus the quantization error is minimized within the given number of quantization stages, regardless of the incoming analog signal level and persistent level fluctuations. The possibility of using a quantizer with relatively few stages and still an analog-digital conversion over the entire analog signal dynamics with always a sufficiently small relative quantization error results in significant advantages if one considers that the quantizer with regard to power consumption, along with anti-alia Filter, the critical circuit part in an analog / digital conversion.

FIG. 2 shows a preferred embodiment variant of the feedback of the output signal A _{5 of} the quantizer 5 to the gain G of the amplifier unit 3 from FIG. 1.

In a memory device 10 a, amplification change variables ΔG of both polarities are stored as a function of the absolute signal values on the output side of the quantizer 5 . By determining at which absolute value of the output signal A ₅ the gain changes ΔG change the sign, corresponding to the value A _5S entered in block 10 a, the TARGET value to be regulated of the mean absolute value of the output signal A _{5 of} the quantizer 5 is predetermined. At 13 , the absolute value generator for the signal A _{5 is} shown. The amplification changes output in function of the signal A ₅ from the table memory 10a ± ΔG are supplied to the memory device 9 with the gain control data, corresponding to the gain control word GCW, which increases or reduces the gain G accordingly.

In Fig. 3a, starting from Figs. 1 and 2, a possible embodiment of the storage and scaling unit 7 of Fig. 1 is shown. The position digits already used with reference to FIGS . 1 and 2 are used for the same functions or function blocks etc.

The gain G on the amplifier unit 3 is, in steps G _o . , ., G _n , adjustable by the control data in the storage device 9 . Corresponding to the number of possible gains n _g = n + 1, a number (n + 1) of memory sections 11 ₀ , 11 ₁ . ., 11 _n featured. All possible values of the output signal A ₅ are pre-stored in all memory sections 11 with 0 ≦ x vor n, as shown at P, but in each section 11 _x scaled with the inverse value of the associated gain G _x ^-1 , ie with G _o ^-1 , G ₁ ^-1 . ., G _n ^-1 . The memory sections 11 are all addressed jointly by the signal appearing at the output A _{5 of} the quantizer 5 , such that, in the case of a digital output signal value under consideration at A ₅ = A _5k , the associated data values are addressed to all memory _sections 11 , which, without restricting the generality , in section 1 ₀ , due to the choice G _o = 1, with the value A _5k at output A ₅ equivalent, in the remaining sections 11 _x each with the assigned inverse gain factor G _x ^-1 it seems.

On the output side of the sections 11 _x thus are the values A = A _{11k 5k.} G _x ^-1 (0 ≦ x ≦ n).

These called values A _11k , that is to say all the outputs of the sections 11 , are connected to a multiplexer unit 15 . The multiplexer unit 15 is, at the input E ₁₅ , corresponding to the input E ₇₂ to the storage and scaling unit 7 shown in FIG. 1, addressed or controlled with the gain control data GCW from the memory device 9 , so that prevailing instantaneous output signals A _11k and simultaneous prevalence of a momentary gain G _k that output A _{11k is} selected and switched through for which x = k applies, thus A _15k = A _5k . G _k ^-1 .

As can be seen, this approach makes the possible speed, without expensive multipliers compensation compensation.

A possible implementation variant of the storage and scaling unit 7 was shown in FIG. 3 a , which serves in particular for clarity.

As shown in Fig. 3b, however, the storage and scaling unit 7 is preferably designed as a storage unit 7 a, in which all possible values of the signal A ₅ , each multiplied by all inverse gain values G ^-1 , are stored. The addressing of the correct value with regard to quantization A _5k as well as gain G _k takes place, as can be seen in FIG. 3b, by addressing the memory unit 7 a by means of an address formed in both from the value of A _5k and from the value of G _k Analogous to the representation of Fig. 1, at the addressing inputs E ₇₁ from the output of the quantizer 5 and E ₇₂ from the output of the memory device 9 with the gain control word GCW. The multiplexer 15 shown in FIG. 3a is thus omitted.

The storage effort in the procedure according to FIG. 3b is particularly important for larger numbers n _g of amplification stages ΔG.

If one considers a 5-stage quantizer 5 plus separate consideration of the sign and therefore a possible number n _a of 64 (2 ⁵ × 2) and, for example, a gain control word in the storage device 9 of 5 bits, the procedure according to FIG. 3 would be a memory requirement for 64. 32 = 2048 values required.

In this regard, is described by the below Approach achieved a significant advantage.

It is assumed that the value ei ner binary number if, e.g. B. regarding one Floating point is shifted by one position by the Factor 2, corresponding to approximately 6 dB, changes.  

Based on this, the intended dynamic range is divided into a number of Z 6 dB steps. Without restricting the generality, G ₀ = 0 dB should be selected, as before, and thus the dynamic range should be equal to the maximum gain G _max

G _max = Z. 6 dB + R,

where R <6 dB denotes a residual quantity. If a gain gradation in ΔG steps of 6 dB is sufficient, looking back at FIGS . 3a, b, only all n _a values of A _{5 have to be} stored in advance, the compensation of the gain in the mentioned 6 dB steps can be done by corresponding Shift the binary number indicating a current value of A ₅ by a number of digits corresponding to the current gain. In this case, nothing would even have to be saved because the address and content of the memory match.

In most cases, a gradation of the gain G corresponding to ΔG steps in 6 dB is not sufficient. In order to solve this problem while at the same time pursuing the goal of reducing the memory expenditure, the 6 dB amplification steps are divided into k ₁ amplification steps 60, where k _{1 is} an integer. Corresponding to the number k ₁ subdivision steps of the 6 dB steps, there is a larger or smaller number of necessary storage space by storing all intermediate steps of the gain compensation contained between the 6 dB steps, each multiplied by all possible n _a values of the signal A ₅ are.

If k ₁ = 2, 128 values must be stored in advance, the ΔG gradation is 3 dB, for k ₁ = 3, 192 the ΔG = 2 dB etc. Without restricting generality, let k ₁ = 4 and therefore the ΔG corresponds to the scaling factor 2¼, i.e. ΔG approximately 1.5 dB. The storage effort is thus reduced to 4 data records, each correspondingly scaled with 0 dB, 1.5 dB, 3 dB, 4.5 dB n _a values of A ₅ and, according to the example above, to storing 256 values.

The current gain G _k can thus be written to

G _k = G _k1 + G _k2 = Z _k (6 dB) + L _k (1.5 dB)

with 0 ≦ L _k ≦ 3.

The following applies to inverse amplification

G _k ^-1 = G _k1 ^-1 + G _k2 ^-1 = -Z _k (6 dB) -L _k (1.5 dB).

FIG. 4 shows the function block / signal flow diagram of how the storage and scaling unit 7 according to FIG. 1 is implemented in a preferred manner.

All possible n _a output values A ₅ , which can occur at the output of the quantizer 5 , are stored in a memory block 7 b, each scaled with the values 1, -ΔG, -2. ΔG,. , ., - (k ₁ -1). ΔG. In the preferred choice of ΔG to 1.5 dB, corresponding to the n _a values A ₅ ; -1.5 dB. A ₅ ; -3 dB. A ₅ and -4.5 dB A ₅ . If an instantaneous value occurs at the output of quantizer A ₅ , this value is sent via addressing input E ₇₁ and, with a first part of the gain control word GCW, via addressing input E ₇₂₁ , with an inverse value -L _k ( ΔG) scaled, output to output A _7b .

In the case of a 5-bit gain control word GCW, the two LSBs from GCW are used for this, as indicated in, with which the L _k values 0, 1, 2, 3 are addressed.

The remaining bits of the gain control word GCW, in the example of such a 5-bit word the three MSB, are fed to a slide unit 7 c, whereupon the number read out from the memory block 7 b, referring to floating point, by the number indicated by the control input E ₇₂₂ Z _k digits is pushed.

In order to explain this further, the maximum value of the memory block 7 b is shown in FIG. 5, for example. From this it can be seen for the time being that in the memory block 7 b 21 bit wide words are stored, the left seven bits being sign extension bits, the eighth bit being a sign bit, the ninth to thirteenth bits for L _k = 0 one Correspond to the value at output A ₅ , and also for L _k = 0, bits 15 to 21 are filled with zeros. For L _k = 0, the fourteenth bit is also always set to 1, which has to do with the special quantizer characteristic curve, which is shown in FIG. 6. As can be seen from FIG. 6, the assignment corresponds to this quantization

m. Δ ≦ x <(m + 1). Δ → y = (m + 1/2),

where x is the analog input signal, d is a fixed Quantization level and y in units of this Quantization level mean measured digital value. This means that m only takes integer values.

Of course, the relationships described above do not apply to L _k not equal to zero, but the values scaled as previously explained are then stored.

With the frame A ₇ , the word given with the slider 7 c is shown. From this it can be seen that in function of the control at input E ₇₂₂ , for example with the three remaining MSB of the 5-bit gain control word GCW, a value is output at the output of slider 7 b, which is one of eight options with regard to the floating point GK is moved. Progressing downwards, each results in -Z _k . 6 dB attenuated values. In the example he explained, the slide unit 7 c results in a possible gain compensation of max. 42 dB (7.6 dB).

The slider unit 7 c is preferably a shift register 8 , as shown in FIG. 7, which is clocked between 14 and 21 times in the event that, as in a preferred manner, a serial loading of the register is provided is.

If Z _k = 0, 14 bits of the 21 right word in memory 7 b are clocked into the shift register 8 by the 14 right bits. At output A ₇ , the 14 bits corresponding to the A ₇ frame position in FIG. 5 appear for Z _k = 0.

If Z _k = 1, from the 21 bit word in memory 7 b by 15 clocks, the right 15 bits are clocked into the shift register 8, the rightmost bit of the 21 bit word is lost at 8a. At output A ₇ , the 14-bit word appears corresponding to the A ₇ frame position in FIG. 5 for Z _k = 1 etc.

In any case, only sign extension bits are read out of the 21-bit word after the 14th bar, that is from the 15th bar. After the 14th cycle, the sign bit is already in the MSB memory of the shift register. Thus, the content of the MSB stage is preferably no longer changed from the 15th cycle, as shown in FIG. 4c, but is only fed to the following stages of the shift register. But that can also use the sign-extension bits 7 VE b dispensed in the memory 7, it becomes smaller by 1/3.

In the example shown with a 5 bit + sign-bit quantizer and a 5 bit gain control word GCW is therefore, with the two LSB of GCW and the output value of the quantizer as an address, in the memory block 7 b, correspondingly with -L _k ΔG scaled A ₅ value is selected, and it is, by means of the slide unit 7 c, this selected value, in function of the remaining three MSB from the GCW, with -Z _k . 6 dB further scaled.

The described analog-digital processing unit is particularly suitable for processing Au diosignals, in particular speech signals. For this will be described in a manner to be described already described arrangement filter before and after switched, the downstream digital filter, or the chosen procedure for digital filtering, considered individually and for other applications can be used.

In FIG. 8, the basic configuration is illustrated a digital filter. When it is explained, the calculation theory of digital filters is not dealt with, about which, as is known to the person skilled in the art, there is a large body of literature.

The digital signal to be filtered is, as shown at 20, a memory unit 21 outlined with dashed lines. With a number of filter coefficients b _k determined depending on the selected filter, a corresponding number of memory sections M ₀ to M _{k are} provided in the memory unit 21 . In each of the memory sections M ₀ to M _k , all possible values of the supplied digital signal 20 , as shown at P, are pre-stored or predetermined. These values are scaled in section M ₀ with the filter coefficient b ₀ , in section M ₁ with the filter coefficient b ₁ etc.

The outputs of the memory sections M ₀ to M _k are supplied to a time delay unit 23 , in which, based on the clock period T _{a of} a clock generator 24 which clocks the digital processing, the output of the section M _{0 is} delayed by a number k clock intervals to the Output A _{230 is} given.

Correspondingly, the outputs of the section M ₁ to M _k , as indicated with a time delay, are output. The outputs of the delay unit 23 are all performed on egg nen adder 25 .

With the digital input data 20 , the pre-stored values corresponding to the respective value of the input data 20 , scaled with the associated filter coefficients, are retrieved from the memory sections M and fed to the addition unit 25 via the time delay unit 23 . In this way, a linear-phase transversal filter is implemented, which does not use complex multipliers.

Such a filter is excellently suitable in combination with the above-described analog-digital processing unit, which is already readily apparent from the fact that, both on the output side of the mentioned analog-digital processing unit and on the input side of the one explained with reference to FIG. 8, he inventive filter, partially pre-stored values are used according to the possible values of the digital signal to be treated.

In Fig. 9, a preferred embodiment egg ner analog-digital processing unit for voice signals is shown, which results from a combination of the unit shown in FIGS . 1 to 7 and the digital filter explained in principle with reference to FIG. 8 with further additional units .

The audio signal, in particular the voice signal, is fed via a microphone 30 to a high-pass filter 32 of the first order, with a cut-off frequency of approximately 1 kHz. This filter flattens the spectrum of the speech signal, which on average has an increase in the range of 500 Hz, so that the signal-to-quantization-to-noise ratio is more even over the entire bandwidth. The resulting change in sound can be compensated for in a simple manner in an analog-digital processing unit that follows the digital signal processing.

It is the analog-digital processing on the input side no anti-aliasing filter provided.

On the output side of the high-pass filter 32 , the analog signal is fed to the amplifier 33 , which, in analogy to the amplifier 3 described above, has a gain G which can be adjusted in 1.5 dB steps. The amplified analog signal is fed to the above-described quantizer 5 analog quantizer 35 , therein, via a rectifier unit 34 , a 5-bit quantizer 36 and, in parallel structure, a sign detector unit 37 . Apart from the sign information VZ occurring on the output side of the unit 37 , in analogy to the above-described output A ₅ , the output A _{36 of} the 5-bit quantizer 36 via the gain change table 40 , in analogy to the above-described 10 a, via a Memory device not shown here, analogous to FIG. 9 , as described above, fed back to the amplifier 33 .

The gain control data GCW, the sign information VZ and the output A _{36 of} the quantizer 36 are fed to a storage and scaling unit 42 . This is divided into four identically constructed storage and scaling sections M ₀ , M ₁ , M ₃ , M ₅ . The section M _{0 of} the storage and scaling unit 42 is, as shown in FIG. 4 at 7 and explained in connection with FIGS. 5 to 7, constructed and is in accordance with the explanations of FIG. 5, in 2 ^-1/4 -Increments, however, additionally scaled with a filter coefficient b ₀ .

Section M ₁ is also constructed as shown in FIG. 4 under 7. However, the data records previously stored in section M ₁ are not scaled like those in M ₀ with b ₀ , but with a filter coefficient b ₁ . The same applies to M ₃ and M ₅ .

On the output side of the storage and scaling unit 42 , assigned to each of the sections M ₀ , M ₁ , M ₃ , M ₅ , digital signals appear which correspond to the following:

From M ₀ : the instantaneous value at output A ₃₆ , controlled by the gain control data GCW - corresponding to the inverse instantaneous gain at amplifier 33 - and additionally scaled with b ₀ .

From M ₁ : As for M ₀ , but additionally scaled with b ₁ instead of b ₀ .

The same applies to M ₃ and M ₅ .

The gain G on the amplifier 33 can be adjusted between 0 and 46.5 dB in steps of 1.5 dB, matched to the 2 ^-1/4 scales in M ₀ and thus M ₁ to M ₅ .

The slide units assigned to these sections, according to 7c of FIG. 4, further FIG. 7, generate 14 bit words. Selection of the scaling and the reading on the slide units 7 b is controlled by the gain control word GCW.

In order to get by without an analog anti-aliasing filter, a sampling rate of preferably 32 kHz is used on the analog-digital processing unit, and a low-pass digital filter, basically constructed according to FIG. 8, is provided on the output side of the storage and scaling unit 42 . This filter is designed in such a way that signal components above 8 kHz are sufficiently attenuated so that the sampling rate can be reduced to 16 kHz without generating disturbing aliasing components. Furthermore, the filter is also designed in such a way that the filter coefficients b _k for all even numbers k nonzero disappear. This significantly reduces the implementation effort. Only four filter coefficients are used, namely for k = 0, ± 1, ± 3 and ± 5. As has been mentioned, the data values in the sections M ₀ , M ₁ , M ₃ , M _{5 are} stored scaled or multiplied by the associated filter coefficients just mentioned.

At the mentioned sampling rate of preferably 32 kHz, the signal components of the sound source above 16 kHz are, as is familiar to the person skilled in the art, to the frequency range 0. , , 16 kHz folded down (alia sing effect). The digital low-pass filter dampens the signal components of the sound source in frequency range 8. , , 16 kHz, as well as those from the frequency range 16. , , 24 kHz in the range 8. , , 16 kHz were folded. For input signals with only vanishing signal components above 24 kHz, i.e. for electrically converted acoustic signals, the aliasing effect by oversampling (f ₁ = 32 kHz) and subsequent digital low-pass filtering, a reduction in the sampling rate is finally avoided.

The digital filter can be operated at the reduced sampling rate of 16 kHz. The arrangement of the time delay elements 44 , designed according to half the clock frequency 1/2 f _{1 used} , is readily apparent from FIG. 6 with a corresponding signal division for each section M for b _{+ k} and b- _k . The delayed signals F ₀ to F ₅ , each for b _{± k} and each from one of the sections M ₀ to M ₅ , as explained on the occasion of FIG. 5, are fed to an addition unit 45 , at whose output A ₄₅ per cycle a digital value appears as the output value of the analog-digital processing unit according to the invention with built-in anti-aliasing processing.

Claims (20)

1. A method for digitizing a band-limited, ana logen signal, wherein

• - The analog signal ( 1 ) is amplified ( 3 ) in a controlled manner,
• - The amplified analog signal is digitized ( 5 ) with a predetermined number of quantization stages,
• - With the digitized analog signals, the gain (G) of the analog signal ( 1 ) is set so that the time average of the amount of the digitized analog signal (A ₅ ) is regulated to a target value,
• - All values of the digitized analog signal (A ₅ ) which are possible in accordance with the number of quantization stages are pre-stored ( 7 ), and
• - With the respective digitized analog signal (A ₅ ) and the prevailing gain (G), the pre-stored ( 7 ) signal corresponding to the digitized analog signal (A ₅ ), amplified with the gain (G ^-1 ) inverse to the prevailing gain (G) , is retrieved.

2. The method according to claim 1, characterized in that with the digitized analog signal (A ₅ ) gain change values (ΔG) are retrieved and the SET value by choice at which value of the digitized analog signal (A ₅ ) a sign change of the retrieved Ver strength change values (ΔG) takes place, is specified. 3. The method according to any one of claims 1 or 2, characterized in that, to take into account the prevailing gain (G), all possible values of the digitized Analogsi gnals (A ₅ ) each pre-stored with all inverse values (G ^-1 ) of the gain ( P) and addressed by a prevailing, digitized analog signal (A ₅ ) and a prevailing gain control value (GCW) (E ₇₁ , E ₇₂ ) and called up. 4. The method according to any one of claims 1 or 2, characterized in that by means of a prevailing value of the digitized th analog signal (A ₅ ) the corresponding, pre-stored ( 7 b) value addressed (E ₇₁ ) and at least partially taking into account the prevailing Gain (G) the addressed value with respect to a floating point (GK), shifted by an amount (E ₇₂₂ ) specified by at least one factor of the prevailing gain control value (GCW), is output. 5. The method according to claim 4, characterized in that all possible values of the digitized analog signal (A ₅ ), each scaled with predetermined, first inverse amplification factors, are pre-stored ( 7 b) and, to take into account the prevailing gain, with the prevailing value of the digitized analog signal (A ₅ ) and a first factor of the prevailing gain control value (GCW) call up a pre-stored value (E ₇₁ , E ₇₂₁ ) and, by a further factor of the prevailing gain control value (E ₇₂₂ ) number of digits with respect to the Floating point (GK) is shifted, is output. 6. The method according to any one of claims 1 to 5, characterized, that the gain in stages according to a factor according to the basic value of the digital representation of the digita lized analog signal is adjustable. 7. The method according to claim 6, characterized in that the stages are further divided, preferably in stages according to factors corresponding to approximately 1.5 dB or 2 ^1/4 . 8. Analog-digital processing unit, with

• - an amplifier unit ( 3 ), to which an analog signal ( 1 ) is fed and whose gain (G) can be adjusted in steps (G ₀ -G _n , AG),
• - Downstream of the amplifier unit ( 3 ), an ana log digital quantizer ( 5 ),
• - Downstream of the analog-digital quantizer ( 5 ), a storage and scaling unit ( 7 ),

in which:

• - The output of the quantizer (A ₅ ) is fed back via a comparison unit ( 10 ) in a regulating sense to a gain control input ( 9 ) on the amplifier unit ( 3 ) and
• - The output of the quantizer ( 5 ) and the output of the comparison unit ( 10 ) on output control inputs (E ₇₁ , E ₇₂ ) on the storage and scaling unit ( 7 ) we effect.

9. Processing unit according to claim 8, characterized in that the comparison unit ( 10 ) comprises a table memory (10a), the input side at least the absolute value of the digital analog signal from the output (A ₅ ) of the quantizer ( 5 ) is fed and which output side to the gain control input ( 9 ) works. 10. Processing unit according to claim 8 or 9, characterized in that the storage and scaling unit comprises a memory device ( 7 a, 11 _x , 15 ) and both the output of the quantizer ( 5 , 35 ) and that of the comparison unit ( 10 a) act on address inputs (E ₇₁ , E ₇₂ ) on the memory device ( 7 a, 11 _x , 15 ). 11. Processing unit according to claim 8 or 9, characterized in that
that the storage and conversion unit (7) chereinrichtung a SpeI (7 b) and a shift register-like ar beitende, the memory means (7 b) downstream unit (7 c) comprises
and that the output of the quantizer ( 5 ) on address inputs (E ₇₁ ) on the memory device ( 7 b) and at least part of the output of the comparison unit ( 10 a) on control inputs (E ₇₂₂ ) on the shift register-like unit ( 7 c ) are guided and preferably another part of the output of the comparison unit ( 10 a) is also routed to addressing inputs (E ₇₂₁ ) on the storage device ( 7 b). 12. Processing unit according to claim 11, characterized in that
that the device ( 7 c) comprises a shift register ( 8 ), which is preferably loaded serially from the memory device ( 7 b),
and that the input-side register stage (MSB) can be switched to its input on the output side from a predetermined number of read-in cycles. 13. Processing unit according to claim 9, characterized in that an output word (A ₅ ) of the quantizer ( 5 ) on the comparison unit ( 10 ) with positive and negative Ver gain changes (ΔG) acts on the gain control input ( 9 ). 14. Processing unit according to one of claims 8 to 12, characterized in that the digital processing is carried out in binary form and the gain (G) is graded in steps of 2 ^1/4 , essentially corresponding to 1.5 dB. 15. Processing unit according to one of claims 8 to 14, for the processing of band-limited analog signals, in particular special speech signals, characterized in that the quantizer ( 5 , 35 ) is a 6-bit quantizer, including a sign bit, which preferably an absolute value generator ( 34 ) with a downstream 5-bit quantizer ( 5 ) and a sign detector ( 37 ). 16. Processing unit according to claim 15, characterized, that he digital processing at a clock frequency follows, which is higher than twice the cutoff frequency of the Analog signal band, preferably at about four times Fre quenz. 17. Processing unit according to one of claims 8 to 16, characterized in that the amplifier unit ( 33 ) has a high-pass filter ( 32 ) connected in front, in the processing of speech signals, preferably a first order filter with a limit frequency of approximately 1 kHz. 18. Processing unit according to one of claims 8 to 17, characterized in that the storage and scaling unit ( 42 ) is followed by a digital low-pass filter ( 44 , 45 ). 19. Processing unit according to claim 18, characterized in that a plurality of storage and scaling units (M ₀ , M ₁ ,...) Are provided, the pre-stored values of which are scaled with the filter coefficients (b _k ), and that the outputs of the storage and scaling units for forming the digital filter, specifically over time delay elements ( 44 ), are fed to an addition unit ( 45 ). 20. Processing unit according to claim 19, characterized, that the digital filter at lower, preferably half Frequency is operated as the upstream Verar processing unit.