DE4232532A1 - Ion-sensitive field effect transistor mfr. for higher reliability - involves electrostatic protection by diodes within well and substrate of CMOS structure in conjunction with pseudo-reference electrode - Google Patents
Ion-sensitive field effect transistor mfr. for higher reliability - involves electrostatic protection by diodes within well and substrate of CMOS structure in conjunction with pseudo-reference electrodeInfo
- Publication number
- DE4232532A1 DE4232532A1 DE19924232532 DE4232532A DE4232532A1 DE 4232532 A1 DE4232532 A1 DE 4232532A1 DE 19924232532 DE19924232532 DE 19924232532 DE 4232532 A DE4232532 A DE 4232532A DE 4232532 A1 DE4232532 A1 DE 4232532A1
- Authority
- DE
- Germany
- Prior art keywords
- ion
- field effect
- sensitive field
- arrangement
- effect transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
- G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
- G01N27/403—Cells and electrode assemblies
- G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
- G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing
Abstract
Description
Die Erfindung betrifft eine Anordnung und ein Verfahren zur Erhöhung der Zuverlässigkeit bei der Herstellung von ionensensitiven Feldeffekttransistoren.The invention relates to an arrangement and a method to increase reliability in the manufacture of ion sensitive field effect transistors.
Die Erfindung findet in der Elektronikindustrie, vorzugs weise in der Halbleitertechnik, bei der Herstellung von ionensensitiven Feldeffekttransistoren Anwendung.The invention takes place in the electronics industry, preferably wise in semiconductor technology, in the manufacture of ion-sensitive field effect transistors application.
Es ist bekannt, daß ionensensitive Feldeffekttransistoren ein offenes Gategebiet haben, das mit einer zu messenden Lösung in Kontakt gebracht wird. Wegen der geringen Isola torschichtdicken und der geringen Eingangskapazitäten ist eine große Empfindlichkeit auf elektrostatische Ladungen festzustellen, wie diese auch im Patent DD 2 75 958 beschrie ben wird.It is known that ion sensitive field effect transistors have an open gate area that is to be measured Solution is brought into contact. Because of the low isola gate layer thicknesses and the low input capacities great sensitivity to electrostatic charges determine how this also described in the patent DD 2 75 958 will.
Dieser negative Effekt tritt gleichermaßen während des Her stellungsprozesses, beim Sensorhandling und im Meßbetrieb auf.This negative effect occurs equally during the heart position process, in sensor handling and in measuring operation on.
Bekannt ist weiterhin, daß wegen der kleinen Nutzsignale im Millivoltbereich auf eine ausreichende elektrische Sta bilität des Gateisolatoraufbaues Wert gelegt wird. Darüber hinaus ist bekannt, daß bei Isolatorschichtungen z. B. bei der Verwendung von üblichen Isolatoren wie Silium-Nitrid (Si3N4), Aluminiumoxid (Al2O3) und Tantalpentoxid (Ta2O5), die auf dem Siliziumdioxid (SiO2) abgeschieden werden, sich daraus hinsichtlich der Stabilität komplizierte Verhältnisse ergeben.It is also known that because of the small useful signals in the millivolt range to a sufficient electrical sta value of the gate insulator structure. About that It is also known that z. B. at the use of common insulators such as silicon nitride (Si3N4), aluminum oxide (Al2O3) and tantalum pentoxide (Ta2O5), which are deposited on the silicon dioxide (SiO2) from this complicated relationships in terms of stability surrender.
Nachteilig sind die dabei entstehenden Isolatorübergänge, die zu Isolatorhaftstellen führen und die bei Umladung zu Instabilitäten der Schwellspannung beitragen.The resulting insulator junctions are disadvantageous, that lead to insulator detention and that to reloading Threshold voltage instabilities contribute.
Weiterhin können Probleme bei der Zuverlässigkeit hinsicht lich der Chippassivierung und Chipverkappung auftreten.Furthermore, reliability problems may arise Lich passivation and chip capping occur.
Der Erfindung liegt die Aufgabe zugrunde, ionensensitive Feldeffekttransistoren mit hoher Zuverlässigkeit hinsicht lich der Handhabungssicherheit und im Lebensdauerverhalten herzustellen.The invention is based, ion-sensitive the task Field effect transistors with high reliability handling safety and durability to manufacture.
Die Erfindung bezieht sich insbesondere auf den Waferpro zeß und ist für ein großes Sensorenkollektiv einsetzbar.The invention relates in particular to the wafer pro zeß and can be used for a large sensor collective.
Nachstehend soll die Erfindung beispielhaft erläutert wer den.The invention will be explained below by way of example the.
Erfindungsgemäß wird der elektrostatische Schutz in Verbin dung mit einer leitfähigen Pseudoreferenzelektrode auf dem Chip realisiert. Die Pseudoreferenzelektrode ist mit zwei Schutzdioden elektrisch verbunden, wobei eine Diode in der Wanne und die andere Diode im Substrat einer CMOS-Schal tung liegt.According to the invention, the electrostatic protection in Verbin with a conductive pseudo reference electrode on the Chip realized. The pseudo reference electrode is two Protective diodes electrically connected, with a diode in the Well and the other diode in the substrate of a CMOS scarf tung lies.
Im spannungslosen Zustand werden elektrostatische Aufla dungen entweder zum Bulk oder zur Wanne abgeleitet. Im Be triebszustand kann sich das Potential infolge von elektro statischen Aufladungen maximal um die Flußspannung der in tegrierten Dioden über die angelegte Betriebsspanung erhö hen. Damit ist in jedem Zustand des Sensors ein wirksamer Schutz möglich. Weiterhin wird erfindungsgemäß der geschich tete Gateisolator mit einer zusätzlichen Isolatorkombination belegt, so daß sich eine Schichtfolge auf dem Siliziumsub strat mindestens der Art I1, I2, I3 und I4 ergibt.In the de-energized state, electrostatic charges drafts either to the bulk or to the tub. In Be drive state, the potential due to electro static charges up to the forward voltage of the in Increase the integrated diodes above the applied operating voltage hen. It is effective in every state of the sensor Protection possible. Furthermore, according to the invention, the history tated gate insulator with an additional insulator combination occupied, so that a layer sequence on the silicon sub strat results at least of the types I1, I2, I3 and I4.
Der Isolator I3 funktioniert als Barriere zur Unterdrückung von elektronischen Isolatorströmen und bewirkt somit eine deutliche Stabilitätsverbesserung des Isolatorsystems. Die Möglichkeit einer zusätzlichen Chippassivierung am Ende des Waferprozesses wird dadurch geschaffen, in dem bei der Strukturierung des metallischen Leibahnsystems zunächst das ionensensitive Feldeffekttransistoren-Gate mit Metall be deckt bleibt und sich noch nicht vom identischen Feldeffekt transistor mit Metallgate unterscheidet. Nach Abscheidung der Zusatzpassivierung erfolgt deren Strukturierung derart, daß nicht nur wie üblich die Kontaktinseln frei geätzt wer den, auch das noch mit Metall abgedeckte ionensensitive Feldeffekttransistoren-Gate. Nach Abdeckung der Kontaktbe reiche des ionensensitiven Feldeffekttransistors wird in einem zweiten Ätzschritt am fertigen Sensorenaufbau (inclu sive Verkappung), das Metall vom ionensensitiven Feldeffekt transistor entfernt. Damit liegt der ionensensitive Feldef fekttransistor wie üblich, ohne Gateabdeckung, präpariert vor. Zur Abgrenzung der Fensteröffnung um das ionensensitive Feldeffekttransistoren-Gate herum, wird ein Lacksteg präpa riert, der bis zur Verkapselung des Chips erhalten bleibt und bei dem Umgießen der Fensteröffnung als Lackstoppkante dient.The isolator I3 functions as a barrier to suppression of electronic isolator currents and thus causes a significant improvement in the stability of the isolator system. The Possibility of an additional chip passivation at the end of the Wafer process is created in which at Structuring the metallic body tooth system first of all ion-sensitive field effect transistor gate with metal be remains covered and does not yet differ from the identical field effect transistor with metal gate differs. After separation the additional passivation is structured in such a way that not only the contact islands are etched freely as usual den, also the ion-sensitive still covered with metal Field effect transistor gate. After covering the contact area range of the ion sensitive field effect transistor is in a second etching step on the finished sensor assembly (incl capping), the metal from the ion-sensitive field effect transistor removed. This is the ion-sensitive field fect transistor prepared as usual, without gate cover in front. To delimit the window opening around the ion sensitive Field effect transistor gate around, a paint bar is prepared that remains until the chip is encapsulated and when casting around the window opening as a paint stop edge serves.
Das Ausführungsbeispiel in (Fig. 1) zeigt eine mögliche Aus führungsvariante eines ionensensitiven Feldeffekttransistors in p-Wannentechnologie in einem n-Si-Substrat 1. Dieser ionensensitive Feldeffekttransistor befindet sich mit seinen Diffussionsgebieten 3 in der p-Wanne 2. Der Gate aufbau besteht aus einem thermischen Oxid 7 und einem zwei ten Isolator 8 bestehend aus Si3N4.The exemplary embodiment in (FIG. 1) shows a possible embodiment variant of an ion-sensitive field effect transistor in p-well technology in an n-Si substrate 1 . This ion-sensitive field effect transistor with its diffusion regions 3 is located in the p-well 2 . The gate structure consists of a thermal oxide 7 and a two insulator 8 consisting of Si3N4.
Erfindungsgemäß wird zusätzlich eine dünne Zwischenschicht 9 präpariert, bevor der obenliegende Isolator 10 bestehend aus wahlweise Si3N4, Ta2O5, oder Al2O3 abgeschieden wird.According to the invention, a thin intermediate layer 9 is additionally prepared before the insulator 10 on top, consisting of optionally Si3N4, Ta2O5, or Al2O3, is deposited.
Die auf dem Feldoxid liegende Pseudoreferenzelektrode steht im Meßbetrieb über den Flächen 12 mit der Meßlösung 17 in Kontakt.The pseudo reference electrode lying on the field oxide is in contact with the measuring solution 17 in the measuring mode over the surfaces 12 .
Zum elektrostatischen Schutz wird über eine Al- Verbindung die Pseudoreferenzelektrode 12 mit den Schutzdioden 4 und 5 verbunden, die erfindungsgemäß elektrostatische Aufladungen ableiten sollen.For electrostatic protection, the pseudo reference electrode 12 is connected to the protective diodes 4 and 5 via an Al connection, which are intended to discharge electrostatic charges according to the invention.
Erfindungsgemäß wird bei der Ätzung des Aluminiums das Alumi nium auf dem ionensensitiven Feldeffekttransistor-Isolator 10 zwecks Strukturierung der Zusatzpassivierung 13 zu nächst stehen gelassen, um es nach dem vollständigen Aufbau des ionensensitiven Feldeffekttransistor-Chips inclusive Abdeckung 15 wieder zu entfernen.According to the invention, the aluminum on the ion-sensitive field-effect transistor insulator 10 is left to stand next to the etching of the aluminum for the purpose of structuring the additional passivation 13 , in order to remove it again after the complete build-up of the ion-sensitive field-effect transistor chip including cover 15 .
Weiterhin wird erfindungsgemäß, um das aktive ionensensitive Feldeffekttransistorgebiet herum, eine Lackstoppkante mit zum Teil überhängendem Seitenprofil 14 präpariert, um das Ver laufen der Abdeckmasse 15 an der beabsichtigten Stelle zu stoppen und damit eine definierte Öffnung in der Abdeckmasse, zu erhalten.Furthermore, according to the invention, around the active ion-sensitive field effect transistor area, a lacquer stop edge with partially overhanging side profile 14 is prepared in order to stop the covering compound 15 from running at the intended location and thus to obtain a defined opening in the covering compound.
BezugszeichenReference numerals
1 n-Si-Substrat
2 p-Wanne
3 ionensensitiver Feldeffekttransistor-Drain/Source
4 n+p-Schutzdiode für Pseudoreferenzelektrode
5 p+n-Schutzdiode für Pseudoreferenzelektrode
6 Feldoxid
7 thermisches Oxid
8 Silizium- Nitrid
9 dünnes thermisches Oxid
10 Silizium-Nitrid, Aluminiumoxid, Tantalpentoxid
11 Al-Kontakte zu den Schutzdioden und zur Pseudoreferenzelektrode
12 freiliegender Teil der Pseudoreferenzelektrode kontaktiert
den Elektrolyten
13 Zusatzpassivierung
14 Lackstopp-Kante
15 Vergußharz/Verkappung
16 vorübergehend stehengelassene Al-Schicht
17 Meßlösung (Elektrolyt) 1 n-Si substrate
2 p-tub
3 ion-sensitive field effect transistor drain / source
4 n + p protection diode for pseudo reference electrode
5 p + n protection diode for pseudo reference electrode
6 field oxide
7 thermal oxide
8 silicon nitride
9 thin thermal oxide
10 silicon nitride, aluminum oxide, tantalum pentoxide
11 Al contacts to the protective diodes and to the pseudo reference electrode
12 exposed part of the pseudo reference electrode contacts the electrolyte
13 Additional passivation
14 paint stop edge
15 potting resin / capping
16 Al layer left temporarily
17 measuring solution (electrolyte)
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE19924232532 DE4232532A1 (en) | 1992-09-29 | 1992-09-29 | Ion-sensitive field effect transistor mfr. for higher reliability - involves electrostatic protection by diodes within well and substrate of CMOS structure in conjunction with pseudo-reference electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE19924232532 DE4232532A1 (en) | 1992-09-29 | 1992-09-29 | Ion-sensitive field effect transistor mfr. for higher reliability - involves electrostatic protection by diodes within well and substrate of CMOS structure in conjunction with pseudo-reference electrode |
Publications (1)
Publication Number | Publication Date |
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DE4232532A1 true DE4232532A1 (en) | 1994-04-28 |
Family
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DE19924232532 Withdrawn DE4232532A1 (en) | 1992-09-29 | 1992-09-29 | Ion-sensitive field effect transistor mfr. for higher reliability - involves electrostatic protection by diodes within well and substrate of CMOS structure in conjunction with pseudo-reference electrode |
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DE (1) | DE4232532A1 (en) |
Cited By (35)
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EP0749632A1 (en) * | 1994-01-19 | 1996-12-27 | Honeywell Inc. | Electrostatic discharge protection of isfet sensors |
DE19856885A1 (en) * | 1998-12-10 | 2000-06-29 | Robert Bischoff | Measuring probe and method for measuring the concentration of agents in gases and / or liquids |
WO2003056322A1 (en) * | 2001-12-21 | 2003-07-10 | Forschungszentrum Jülich GmbH | Fet sensor with a specially configured gate electrode for the highly sensitive detection of analytes |
WO2005073706A1 (en) * | 2004-01-21 | 2005-08-11 | Rosemount Analytical Inc. | Ion sensitive field effect transistor (isfet) sensor with improved gate configuration |
WO2010112324A1 (en) * | 2009-03-31 | 2010-10-07 | Endress+Hauser Conducta Gesellschaft Für Mess- Und Regeltechnik Mbh+Co. Kg | Ion-sensitive sensor having a multilayer structure in a sensitive region |
WO2011018310A1 (en) * | 2009-08-12 | 2011-02-17 | Endress+Hauser Conducta Gesellschaft Für Mess- Und Regeltechnik Mbh+Co. Kg | Ion-sensitive sensor having multilayer construction in the sensitive region |
DE102012104770A1 (en) * | 2012-06-01 | 2013-12-05 | Endress + Hauser Conducta Gesellschaft für Mess- und Regeltechnik mbH + Co. KG | Method for checking protective circuit of e.g. P-channel transistor to measure concentration of hydrogen ion in process automation field, involves outputting error message if measured values lie outside of tolerance range |
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US9239313B2 (en) | 2010-06-30 | 2016-01-19 | Life Technologies Corporation | Ion-sensing charge-accumulation circuits and methods |
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