DE4018615A1 - Frequency converter for quadrature modulator or demodulator - Google Patents

Frequency converter for quadrature modulator or demodulator

Info

Publication number
DE4018615A1
DE4018615A1 DE4018615A DE4018615A DE4018615A1 DE 4018615 A1 DE4018615 A1 DE 4018615A1 DE 4018615 A DE4018615 A DE 4018615A DE 4018615 A DE4018615 A DE 4018615A DE 4018615 A1 DE4018615 A1 DE 4018615A1
Authority
DE
Germany
Prior art keywords
signal
amplifier
quadrature
oscillator signal
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE4018615A
Other languages
German (de)
Inventor
Erfinder Wird Nachtraeglich Benannt Der
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Conti Temic Microelectronic GmbH
Original Assignee
Licentia Patent Verwaltungs GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Licentia Patent Verwaltungs GmbH filed Critical Licentia Patent Verwaltungs GmbH
Priority to DE4018615A priority Critical patent/DE4018615A1/en
Publication of DE4018615A1 publication Critical patent/DE4018615A1/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0064—Pulse width, duty cycle or on/off ratio
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0078—Functional aspects of oscillators generating or using signals in quadrature

Abstract

The frequency converter for a quadrature modulator or demodulator uses a heterodyne signal genreator (TG). An associated regulating circuit stabilises the 90 degrees phase shift between the 2 quadrature heterodyne signals (TI,TQ). Pref. the heterodyne signal generator (TG) contains an amplifier, controlled by an oscillator signal (LO), a further regulating circuit containing a symmetry detector for the pulse ratio of the amplifier output signals, for maintaining a pulse ratio of 0.5. A quadrature phase divider pref. uses a frequency doubler and a master slave flip-flop in series, the outputs of the master stage and the slave stage providing here 2 quadrature signals (TI,TQ).

Description

Die Erfindung betrifft eine Schaltungsanordnung zur Aufbe­ reitung eines Oszillatorsignals.The invention relates to a circuit arrangement for Aufbe riding an oscillator signal.

In der Kommunikationstechnik werden häufig, z.B. zur Modu­ lation oder Demodulation von Signalen zur Nachrichtenüber­ mittlung, Signale bestimmter Frequenz benötigt. Diese wer­ den in Oszillatoren erzeugt und den entsprechenden Bau­ gruppen zugeleitet. Die Oszillatorsignale erfüllen aber insbesondere bei hohen Frequenzen häufig nicht die Anfor­ derungen hinsichtlich Verzerrungsfreiheit, die für ein­ wandfreien Betrieb der nachfolgenden Baugruppen notwendig sind.In communication technology, e.g. to the mod lation or demodulation of signals for message transfer averaging, signals of certain frequency required. This who the generated in oscillators and the corresponding construction groups forwarded. However, the oscillator signals fulfill especially at high frequencies often not the requirement changes regarding freedom of distortion, which are necessary for a Wall-free operation of the following modules is necessary are.

Aufgabe der vorliegenden Erfindung ist daher, eine vor­ teilhafte Schaltungsanordnung zur Aufbereitung eines Os­ zillatorsignals, insbesondere zur Erzielung eines Tastver­ hältnisses von 0,5 im aufbereiteten Oszillatorsignal an­ zugeben.The object of the present invention is therefore one before partial circuit arrangement for processing an Os zillatorsignal, in particular to achieve a Tastver ratio of 0.5 in the conditioned oscillator signal admit.

Die Erfindung ist im Patentanspruch 1 beschrieben. Die Un­ teransprüche enthalten vorteilhafte Ausgestaltungen der Erfindung.The invention is described in claim 1. The Un Claims contain advantageous refinements of Invention.

Die Erfindung ist insbesondere auch bei unsymmetrisch zu­ geführten Eingangssignal und symmetrisch abgenommenen Aus­ gangssignal vorteilhaft einsetzbar.The invention is also particularly asymmetrical guided input signal and balanced off can be used advantageously.

Die Erfindung ist nachfolgend anhand eines Beispiels unter Bezugnahme auf die Abbildung noch veranschaulicht.The invention is described below using an example Reference to the picture still illustrated.

Das Oszillatorsignal LO ist unsymmetrisch an den Eingang einer aus mehreren Verstärkerstufen LV1, LV2, LV3, von denen die letzte (LV3) vorzugsweise in die Begrenzung ge­ steuert ist, aufgebauten Verstärkeranordnung LV gelegt.The oscillator signal LO is unbalanced to the input of an amplifier arrangement LV constructed from a plurality of amplifier stages LV 1, LV 2, LV 3, of which the last one (LV 3 ) is preferably controlled in the limitation.

Das Ausgangssignal der letzten Verstärkerstufe LV3 ist ei­ nem Detektor SD zugeführt, der fortlaufend das Tastver­ hältnis des begrenzten Ausgangssignals detektiert und bei von 0,5 abweichendem Tastverhältnis über einen Regelver­ stärker HRV ein Regelsignal LR für die erste Verstärker­ stufe LV1 erzeugt, das der Unsymmetrie entgegenwirkt, bei­ spielsweise durch eine Gleichspannungs-Pegelveschiebung des Eingangs- oder Ausgangssignals der ersten Verstärker­ stufe, wodurch sich der Schaltzeitpunkt des Verstärkers ändert. Durch den externen Kondensator C1 ist die Regel­ zeitkonstante der Regelschleife einstellbar. Das Ausgangs­ signal der letzten Verstärkerstufe LV3, für welches durch die Regelschleife mit SD und HRV Halbwellensymmetrie (Tastverhältnis 0,5) gewährleistet ist, ist beispielsweise an den Eingang einer Frequenzverd opplungsschaltung FD ge­ legt, die ein Signal doppelter Frequenz abgibt. Bei guter Halbwellensymmetrie des Signals am Eingang von FD ist die Grundwelle im Ausgangssignal von FD weitestgehend unter­ drückt.The output signal of the last amplifier stage LV 3 is fed to a detector SD, which continuously detects the duty ratio of the limited output signal and generates a control signal LR for the first amplifier stage LV 1 at a duty cycle that deviates from 0.5 via a control amplifier HRV Counteracts asymmetry, for example by a DC level shift of the input or output signal of the first amplifier stage, which changes the switching time of the amplifier. The control time constant of the control loop can be set by the external capacitor C 1 . The output signal of the last amplifier stage LV 3, for which half-wave symmetry (duty cycle 0.5) is ensured by the control loop with SD and HRV, is for example at the input of a frequency doubling circuit FD, which emits a signal of double frequency. With good half-wave symmetry of the signal at the input of FD, the fundamental wave in the output signal from FD is largely suppressed.

Eine andere, besonders bedeutsame Verwendung des aufgear­ beiteten Ausgangssignals ist in der Ansteuerung einer Mi­ scheranordnung, z.B. eines Gegentaktmischers zur Fre­ quenzumsetzung zu sehen. Die Schaltungsanordnung zur Auf­ bereitung des Oszillatorsignals ist vorzugsweise mit ande­ ren Baugruppen, insbesondere der von dem aufbereiteten Si­ gnal direkt angesteuerten Baugruppe monolithisch inte­ griert.Another, particularly significant use of the aufear processed output signal is in the control of a Mi shear arrangement, e.g. a push-pull mixer to Fre to see quenz conversion. The circuit arrangement for on Preparation of the oscillator signal is preferably with others ren assemblies, especially that of the prepared Si gnal directly controlled module monolithic inte freezes.

Der Detektor SD kann als einfacher RC-Integrator ausge­ führt sein. Zu beachten ist, daß der Detektor nicht unmit­ telbar das Ausgangssignal verfälscht, weshalb vorzugsweise das Regelsignal LR nicht aus dem Ausgangssignal selbst, sondern aus einem diesem proportionalen Signal abgeleitet ist.The detector SD can be a simple RC integrator leads. It should be noted that the detector is not immediately telbar falsifies the output signal, which is why preferably the control signal LR not from the output signal itself, but derived from a signal proportional to this is.

Die skizzierte Anordnung stellt lediglich eine Ausfüh­ rungsform der Erfindung dar, ohne diese darauf einzu­ schränken. Insbesondere braucht der Verstärker LV nicht mehrstufig ausgeführt sein und das Oszillatorsignal kann je noch Anwendungsfall auch linear verstärkt oder nur schwach begrenzt werden.The arrangement outlined is only an example tion form of the invention, without this restrict. In particular, the amplifier does not need LV be designed in several stages and the oscillator signal can depending on the application, also linearly reinforced or only to be weakly limited.

Claims (3)

1. Schaltungsanordnung zur Aufbereitung eines Oszillator­ signals, dadurch gekennzeichnet, daß das Oszillatorsignal an die Eingänge eines Verstärkers gelegt ist, an dessen Ausgang das aufbereitete oszillatorsignal abnehmbar ist, daß ein Regeldetektor aus dem aufbereiteten Oszillatorsi­ gnal oder einem dazu proportionalen Signal ein Regelsignal derart ableitet und auf ein Signalweg vor dem Verstärker­ ausgang liegende Stellmittel leitet, daß das aufbereitete Oszillatorsignal ein Tastverhältnis von 0,5 aufweist.1. Circuit arrangement for processing an oscillator signal, characterized in that the oscillator signal is connected to the inputs of an amplifier, at the output of which the processed oscillator signal can be removed, that a control detector derives a control signal from the processed oscillator signal or a signal proportional thereto and on a signal path in front of the amplifier output control means that the conditioned oscillator signal has a duty cycle of 0.5. 2. Schaltungsanordnung nach Anspruch 1, dadurch gekenn­ zeichnet, daß die Stellmittel eine Verschiebung des Gleichspannungspegels an einen Punkt im Signalweg bewir­ ken. 2. Circuit arrangement according to claim 1, characterized records that the adjusting means a shift of the Cause DC voltage level at a point in the signal path ken.   3. Schaltungsanordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Verstärker ein Begrenzerverstärker ist.3. Circuit arrangement according to claim 1 or 2, characterized characterized in that the amplifier is a limiter amplifier is.
DE4018615A 1989-06-09 1990-06-11 Frequency converter for quadrature modulator or demodulator Ceased DE4018615A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE4018615A DE4018615A1 (en) 1989-06-09 1990-06-11 Frequency converter for quadrature modulator or demodulator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3918829 1989-06-09
DE4018615A DE4018615A1 (en) 1989-06-09 1990-06-11 Frequency converter for quadrature modulator or demodulator

Publications (1)

Publication Number Publication Date
DE4018615A1 true DE4018615A1 (en) 1990-12-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE4018615A Ceased DE4018615A1 (en) 1989-06-09 1990-06-11 Frequency converter for quadrature modulator or demodulator

Country Status (1)

Country Link
DE (1) DE4018615A1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995022202A1 (en) * 1994-02-15 1995-08-17 Rambus, Inc. Amplifier with active duty cycle correction
US5808498A (en) * 1995-05-26 1998-09-15 Rambus, Inc. At frequency phase shifting circuit for use in a quadrature clock generator
WO1999012259A2 (en) * 1997-09-05 1999-03-11 Rambus Incorporated Duty cycle correction circuit using two differential amplifiers
DE19720017B4 (en) * 1996-05-13 2004-06-03 NEC Compound Semiconductor Devices, Ltd., Kawasaki 90 ° phase shifter
US6833743B2 (en) 2002-10-29 2004-12-21 Gong Gu Adjustment of a clock duty cycle
US7893667B2 (en) 2005-08-05 2011-02-22 Rohm Co., Ltd. PWM power supply apparatus having a controlled duty ratio without causing overall system oscillation
DE112013002433B4 (en) * 2012-05-11 2020-12-24 Analog Devices Inc. Clock generator for crystal or ceramic oscillator and filter system for this

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1479516A (en) * 1973-12-27 1977-07-13 Burroughs Corp Pulse generator with automatic timing adjustment
GB2079084A (en) * 1980-06-17 1982-01-13 Sony Corp Wave-shaped circuits for digital signals
DE3514155A1 (en) * 1985-04-19 1986-10-23 Dr. Johannes Heidenhain Gmbh, 8225 Traunreut METHOD AND DEVICE FOR REGULATING THE KEY RATIO AT LEAST ONE ELECTRICAL SIGNAL
DE3816973A1 (en) * 1987-05-21 1988-12-22 Pioneer Electronic Corp PULSE WIDTH INTERFERENCE CORRECTION
EP0343899A2 (en) * 1988-05-23 1989-11-29 Advanced Micro Devices, Inc. Circuit for generating pulses having controlled duty cycle

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1479516A (en) * 1973-12-27 1977-07-13 Burroughs Corp Pulse generator with automatic timing adjustment
GB2079084A (en) * 1980-06-17 1982-01-13 Sony Corp Wave-shaped circuits for digital signals
DE3514155A1 (en) * 1985-04-19 1986-10-23 Dr. Johannes Heidenhain Gmbh, 8225 Traunreut METHOD AND DEVICE FOR REGULATING THE KEY RATIO AT LEAST ONE ELECTRICAL SIGNAL
DE3816973A1 (en) * 1987-05-21 1988-12-22 Pioneer Electronic Corp PULSE WIDTH INTERFERENCE CORRECTION
EP0343899A2 (en) * 1988-05-23 1989-11-29 Advanced Micro Devices, Inc. Circuit for generating pulses having controlled duty cycle

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995022202A1 (en) * 1994-02-15 1995-08-17 Rambus, Inc. Amplifier with active duty cycle correction
US5572158A (en) * 1994-02-15 1996-11-05 Rambus, Inc. Amplifier with active duty cycle correction
US5808498A (en) * 1995-05-26 1998-09-15 Rambus, Inc. At frequency phase shifting circuit for use in a quadrature clock generator
USRE37452E1 (en) 1995-05-26 2001-11-20 Rambus Inc. At frequency phase shifting circuit for use in a quadrature clock generator
DE19720017B4 (en) * 1996-05-13 2004-06-03 NEC Compound Semiconductor Devices, Ltd., Kawasaki 90 ° phase shifter
WO1999012259A2 (en) * 1997-09-05 1999-03-11 Rambus Incorporated Duty cycle correction circuit using two differential amplifiers
WO1999012259A3 (en) * 1997-09-05 1999-06-03 Rambus Inc Duty cycle correction circuit using two differential amplifiers
US6833743B2 (en) 2002-10-29 2004-12-21 Gong Gu Adjustment of a clock duty cycle
US7893667B2 (en) 2005-08-05 2011-02-22 Rohm Co., Ltd. PWM power supply apparatus having a controlled duty ratio without causing overall system oscillation
DE112013002433B4 (en) * 2012-05-11 2020-12-24 Analog Devices Inc. Clock generator for crystal or ceramic oscillator and filter system for this

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Legal Events

Date Code Title Description
OR8 Request for search as to paragraph 43 lit. 1 sentence 1 patent law
8181 Inventor (new situation)

Free format text: TRAENKLE, GUENTHER, DIPL.-PHYS., 7910 NEU-ULM, DE

8105 Search report available
8127 New person/name/address of the applicant

Owner name: TEMIC TELEFUNKEN MICROELECTRONIC GMBH, 74072 HEILB

8110 Request for examination paragraph 44
8131 Rejection