DE3939191A1 - Multibeam one-way light barrier - uses diodes transmitting pulse-gap modulated pulses with route marking characteristic to monitor protected area - Google Patents

Abstract

Contactless monitoring of a protected area is achieved by a transmitter (1) consisting of a series of i.r. diodes (2,3,4) periodically and cyclically switched on in sequence to transmit modulated light. The receiver has a corresp. number of photodiodes operated periodically and cyclically and assigned to their own sender diodes. A multichannel evaluating unit in the receiver generates a signal meaning "Area not free", when at least one light beam is interrupted. Pref., the photodiodes are clocked by a free-wheeling oscillator. Pref., the evaluating unit synchronises the cyclical activation of the photodiodes on the basis of the light pulses received from a selected i.r. diode (2). ADVANTAGE - Max. security even if one or several components develop a fault or there is external interference.

Description

The invention relates to a multi-jet One-way light barrier according to the preamble of the patent saying 1. Such a light barrier is made of one Company brochure with the name Honeywell "FF-SB14 series one-way photoelectric safety barriers" (Device information E215) known. They are from each other separate transmitters and receivers are provided, which have a separate synchronization beam the periodic activation synchronize the transmit and receive diodes. The The synchronization beam has the opposite direction towards the light rays, so it runs from the "receiver" to the "transmitter".  

From a company brochure by Reer S.A.S. with the Title "Sicurprocessor" is a two-way light grid known, with the transmitter and receiver in one housing are housed and the light from the transmitter on the Protective field to a reflector and from there back to the Recipient is directed. There are also individual broadcast and Receiving diodes provided by a common one Central unit are controlled, these central units Unit 2 output channels to control two separate Relay. The infrared emitted by the LEDs Light is modulated to interfere with extraneous light avoid.

From a company brochure by Fasnacht entitled "Light curtain accident protection" (P1141 / 1) is a one-way light grid with transmitter and receiver known, in which also sequentially on the transmitter side one light pulse per transmitter element is triggered. Transmitter and receiver are based on a common evaluation and Switchgear coupled together. The evaluation works with two criteria:

• a) The last receiver signal must coincide with the last transmitter pulse coincide; and
• b) The sum of the received signals must be the number of rays of the light grid.

If the beam is interrupted, at least one of the two Criteria no longer met. The evaluation takes place there over two separate channels. So it becomes security concept of redundancy applied.

The object of the present invention is to disposable light barrier of the type mentioned at the beginning even more securely shape so that with all possible interruptions one of the rays of light and with any possible Errors, whether due to the failure of one or more Components or be it due to other external interference optimal safety is always achieved.  

This task is carried out in the characterizing part of the Features specified claim 1 solved. Beneficial Refinements and developments of the invention are can be found in the subclaims.

In general, the signal is transmitted from the transmitter to Receiver only by light pulses. Evaluated be the time behavior of the impulses and / or their Number of bars. Each light emitting diode preferably sends double im pulse that clearly against extraneous light, such as. B. Stroboscopic lamps, starting neon lamps etc., different can be. A selected one (preferably the first) LED sends one of them differently larger number of pulses required for synchronization between Sender and receiver is used.

The LEDs are controlled via an as feedback shift register acting chain from D flip-flops through which a single logical "1" is pushed becomes. Should have more than a "1" in the shift register included, this is recognized as an error. To further increase in security are two in the receiver independent channels available, each also have their own clock. Every channel synchronized independent of the other channel on the transmitter. A "Handshake" mode checks whether both channels are the same Show result. Only if this is the case a release. To that extent, for the security concept redundancy is applied due to the dual-channel nature. The Both channels are linked via a "fail-safe" - Comparator in contact technology, one each (Relay) contact of one channel in the evaluation circuit of the other channel. Only if both channels at the same time report a release, there will be a release signal at the output generated. In contrast, reports one channel at a time an undisturbed operation while the other is still there does not report, it is blocked and it can also, if the other channel reports a release a little later,  no output enable signal can be generated. To Contacts can also further increase security external relay looped into the evaluation circuit be, so that in addition a contact monitoring takes place.

The receive diodes in the amplifier are discrete Switch controlled, the signals from the receiving diodes switch through on bus lines of the individual channels. Because these switches are constructed discretely, there is no risk of intercom. The flip-flop The chain in the sender and receiver is one step at a time longer than the number of diodes. So that can be monitored whether all discrete switches are open.

The individual diodes are of a relatively high Clock frequency activated one after the other. Because with very fast Microcontrollers frequently experience errors, which occurs Evaluation of the rapidly successive signals fast comparators and fast monostable flip Flops that route the signals to fast counters. The The counting results of the individual light pulses then stand for longer at the output of the meter and can then in the slower microcontroller can be adopted.

Further advantageous configurations and features of the Invention can be found in the following description men.

The invention based on an embodiment example in connection with the drawing in more detail explained. It shows:

Fig. 1 The principle of operation of the transmitter;

Fig. 2 The principle of operation of the receiver;

Fig. 3 is a block diagram of the transmitter;

Fig. 4 is a detailed circuit diagram of the transmitter;

Fig. 5 is a block diagram of the control unit of the transmitter with the first sliding space;

Fig. 6 is a detailed circuit diagram of the control unit of the transmitter;

Fig. 7 pulse diagrams for explaining individual functions of the transmitter;

Fig. 8 is timing charts for explaining other functions of the transmitter;

Fig. 9 is a block diagram of the receiver;

Fig. 10 is a detailed circuit diagram of the receiver;

Fig. 11 is a block diagram of a control unit of the receiver;

Fig. 12 is a detailed circuit diagram of a control unit of the receiver;

Fig. 13 is a block diagram of the input / output unit of the receiver including a comparator according to a first embodiment;

Fig. 14 is a detailed circuit diagram of the input / output unit of the receiver;

Fig. 15 is a block diagram of the analog switch ter of the receiver;

Fig. 16 is a detailed circuit diagram of the analog switches of the receiver;

Fig. 17 is a flowchart showing the rough structure of the function of the microcontroller;

Fig. 18 is a block diagram of the receiver (similar to Fig. 2) according to a second embodiment of the invention;

FIG. 19 is a block diagram of the input / output unit of the receiver including comparisons (., Similar to Figure 13) in accordance with a second exporting approximately example of the invention;

FIG. 20 is a detailed circuit diagram of a part of the input / output unit of the receiver (similar to Fig 14 but without clocking.) According to a second embodiment of the invention;

Fig. 21 A circuit diagram (similar to Fig. 20) with fixed wiring for external device monitoring, operating mode and restart interlock;

Fig. 22 is a circuit diagram (similar to Fig. 20) with operating mode selector;

Fig. 23 is a detailed circuit diagram of the clock controller according to the second embodiment of the invention.

Fig. 1 shows the principle of operation of the transmitter. In the transmitter 1 , a number of LEDs 2 , 3 , 4 is arranged in a row at a predetermined distance. The light emitting diode 2 is the first of this row, the light emitting diode 3 , the second and the light emitting diode 4 the last of this row. The electrical control of the light emitting diodes is built up of one channel from digital circuits and consists essentially of a switching mechanism 5 for control signal generation and a ring shift register 6 with a number n of shifting positions, this number n being 1 greater than the number (n-1) of the LEDs 2-4 . Each Leuchtdi ode is assigned to a sliding space 7 , 8 , 9 and is activated by this. Since the ring shift register 6 has a sliding place 10 more than connected light-emitting diodes, no light-emitting diode is connected to the last sliding place 10 . The last sliding place 10 is connected to the entrance of the first sliding place 7 by a return line 11 . In the ring shift register 6 , a "1" is pushed through in cycles and, after the register has passed through completely, is returned to the first shifting position. This activates the individual LEDs 2 ... 4 one after the other. Each activated light emitting diode sends out coded light pulses with a specific identifier. The identifier of a selected light-emitting diode, here the first light-emitting diode 2 , differs from the identifier of the other light-emitting diodes, which each have the same identifier. The identifier of the first light-emitting diode 2 here consists of four pulses 12 , while the identifier of the other light-emitting diodes 3 ... 4 consists of two pulses 13 each. The identifier 12 of the first light-emitting diode 2 is used to synchronize the receiver.

The last shift location 10 of the ring shift register 6 serves to generate a delay time which is used by the receiver to carry out a test.

After applying the mains voltage, the ring shift register 6 is completely deleted. Then a "1" is placed by the switching mechanism 5 in the first sliding space 7 and then pushed further in a circle. This shifting process is carried out continuously as long as the mains voltage is present. As soon as a "1" is pushed into a sliding position 7 ... 9 , the LED 2 ... 4 connected there sends its pulse group.

Fig. 2 shows the principle of operation of the receiver 15. It has one of the number of light emitting diodes 2 ... 4 corresponding number of photodetectors 16 ... 18 , each photodetector 16 ... 18 being assigned to a certain light emitting diode 2 ... 4 .

For safety reasons, the receiver 15 - with the exception of the photodetectors 16 ... 18 - has a two-channel structure with homogeneous redundancy and a fail-safe comparator. The individual channels essentially consist of a power supply unit (not shown), a microcontroller 19 , 20 , an amplifier 21 , 22 , a fail-safe comparator 23 assigned to both channels, a relay output 25 and a ring shift register 26 , 27 with n Sliding places 28 ... 31 , 32 ... 35 . The number n corresponds to the number of sliding positions in register 6 of the transmitter. Here, too, a "1" is shifted through the shift registers 26 and 27 in a manner similar to that of the transmitter, with only that photodetector 16 , 17 and 18 being activated whose associated shift location 28 ... 30 or 32 ... 34 which leads "1". This "activation" is carried out by separate analog switches 121 ... 123 ( FIG. 9), through which the output signal of the activated photodetector is switched through to a common bus line 36 and 37 for the two channels. The signals on these collecting lines 36 , 37 are fed to the microcontrollers 19 , 20 via the amplifiers 21 , 22 and evaluated there. If there is a match between the received signal and an expected signal, the microcontrollers 19 , 20 generate signals with which the shift registers 26 and 27 are switched on. The last shift location 31 or 35 of the shift registers 26 or 27 also serves to generate a delay time during which certain tests are carried out. Therefore, the outputs of the last places 31 and 35 of the shift registers 26 and 27 are connected to the assigned microcontroller 19 and 20 via return lines 40 and 41, respectively. The inputs of the first sliding spaces 28 and 32 are also connected to the assigned microcontroller 19 and 20 via data lines 38 and 39 .

During a test phase, the collecting lines 36 and 37 can be disconnected from the amplifiers 21 , 22 , which is indicated by start and test switches 42 , 43 , which can be controlled by a signal on a control line 44 .

A “watchdog” circuit 45 and 46 is also assigned to the microcontrollers 19 and 20 , with which certain functions of the microcontrollers can be monitored.

Both receiving channels work completely independently of one another, with only the photodetectors being shared by both channels. This means that the safety-relevant part of the circuit is designed as a two-channel function logic with homogeneous redundancy. The fail-safe comparator 23 compares the agreement of the signals of the two channels.

Fig. 3 shows a more detailed block diagram of the transmitter. The ring shift register 6 ( FIG. 1) is here made up of a chain of D flip-flops, each of which represents one of the shift locations 7 ... 10 . All clock inputs of the flip-flops are connected to a common clock line 47 . The D input of the first sliding place 7 is connected to the switching mechanism 5 ( FIG. 1) via the line 14 . For the functional representation of an activation function (enable function), the Q outputs of the sliding positions 7 to 10 are each connected to a controllable switch 53 , 54 , 55 , 56 , the outputs of which - with the exception of the enable switch 56 of the last flip-flop Level - are connected to control inputs of controllable switches 57 , 58 and 59 . The switches 57 to 59 are connected with their one connection to a common line 50 which leads to pulses for driving the light-emitting diodes 2 , 3 , 4 . The other connections of the switches 57 , 58 , 59 are connected to the input of the associated light-emitting diode 2 , 3 or 4 . Furthermore, all LEDs are connected to a common power supply line 49 .

The control inputs of the enable switches 53 ... 56 are connected to a common control line 48 , which carries an inverted "enable" signal (enable across). By means of a control signal on line 48 , the ring shift register can be separated from the LEDs. If the enable switches 53 to 56 are closed, the output signal of the sliding position 7 ... 9 which is currently carrying a "1" closes the assigned switch 57 , 58 or 59 , so that the pulses arriving on the line 50 the Activate selected transmission diode 2 ... 4 .

Since the ring shift register 6 is reset when the device is such that all shift places cause a "0", it is necessary to start the first shift position 7 (Fig. 5) are set to a "1", which is done by signals from the switching unit 5. In the illustrated embodiment, a line 51 branches off from line 14 , which line is connected to the control input of switch 57 and continues to the D input of second sliding space 8 . In this case, the output of the enable switch 53 of the first stage 7 ( FIG. 3) is not connected to the control input of the switch 57 . Thus, the first sliding place of the chain is ineffective. Since the components of FIG. 3 are each arranged on a circuit board and these circuit boards are cascadable to form longer shift registers, the same structure has been provided for all cascade stages, with the individual circuit board being able to be configured using "jumpers" (switchable switches) . A first jumper 52 is provided in line 51 . This jumper 52 is set for the first stage of a cascade, so that line 51 is connected through. In contrast, the jumper 52 is removed for further cascade stages, so that the line 51 is interrupted. Conversely, a jumper 60 is provided in the connecting line between the output of the enable switch 53 and the transmitter diode switch 57, which jumper 60 is removed for the first sliding position, but is set against it in the subsequent cascade stages. The last sliding location 10 also has a jumper 61 in a line 62 connected to the output of the enable switch 56 , which is only set at the last stage of the ring sliding register, so that only the last sliding location of a ring sliding register composed of any number of stages is included the line 11 is connected. If several circuit boards are built in cascade to form a longer ring slide gate, the output of the penultimate slide slot, here the enable switch 55, is connected via a line 63 to the D input of the first slide slot of the subsequent stage.

The outputs of the enable switches 53 , 54 , 55 are connected via lines 64 , 65 and 66 to the D input of the next sliding area 8 , 9 and 10 , respectively.

Fig. 4 shows a detailed circuit diagram of the transmitter unit of Fig. 3. The ring shift register 6 is realized here by two integrated flip-flop circuits 6 'and 6 ''of the type HEF 40374B. These are 8-stage D flip-flops with buffered outputs, which can have three states. Data at the D inputs of each stage are transferred to the memory of the respective stage during a "LOW" - "HIGH" transition at the clock input. The output buffers of the stages are queried by a "low" signal at the input EO (output enable input) activated. A "HIGH" signal at this input puts all eight outputs in a switched-off state with high impedance. The flip-flop outputs downstream resistors 72 ... 74 cause the high-resistance outputs to assume a logic "0". A logical "0" at this input causes the data in the registers to appear at the outputs. The last output 07 of the first integrated circuit 6 'is connected to the first D input D 0 of the second integrated circuit 6 ''. Furthermore, the output of each sliding space is connected to the input of the next sliding space with certain exceptions for the first and last sliding space of the ring shift register. As mentioned in connection with Fig. 3, the first shift space of the ring shift register is unused and replaced by an additional flip-flop in the switching mechanism 5 , which takes over its function. This ensures that the first effective shift location of the ring shift register is not switched off by a signal on the enable line 48 . The output signal of the effective first sliding space therefore passes directly via line 14 and the set jumper 52 and line 64 to input D 1 of the second sliding space. In contrast, the jumper 60 is not set in this case, so that the state of the first stage of the integrated circuit 6 '(output "0 zero") does not affect the second stage.

In the present exemplary embodiment, twelve (N-1 = 12) transmitter diodes 2 , 3 ... 4 are arranged on a circuit board. Therefore, only n = 13 register stages are required, so that in the modules used here with eight stages each, the second integrated circuit 6 '' has only five active register locations. The last three register positions are therefore deactivated by connecting inputs D 5 , D 6 and D 7 to a ground line 67 . The output 03 of the penultimate sliding area controls the last transmitter diode switch 59 ; the output 04 of the last register stage is connected to line 11 via line 62 and jumper 61 .

All transmitter diodes 2 , 3 ... 4 are connected with their anode to a common line 68 , which in turn is connected via two series resistors 69 and 70 to line 49 , which supplies the energy for the transmitter diodes. At the common connection point of the resistors 69 and 70 , a capacitor 71 connected to ground is connected. The cathodes of the transmitter diodes 2 , 3 ... 4 are each connected to the drain terminal of the transmitter diodes designed as a field effect transistor 57 , 58 ... 59 . The source terminal of each transmitter diode switch is connected to line 50 , which carries the drive pulses. The gate connections of the transmitter diode switches 57 , 58 ... 59 are connected to the assigned output of the respective shift register locations and via pull-down resistors 72 , 73 ... 74 to a common ground line 75 .

The lines 47 , 48 and 14 are each connected via pull-up resistors 76 , 77 and 78 with positive supply voltage.

Are boards connected with transmitter units of FIG. 4 in cascade one after the other, they can be constructed identically in principle, only the jumper 52, 60 and 61 are set differently, and wherein the pull-up resistors 76 and 77 only on one of the boards must be present, preferably on the last board, to force a defined current flow. Otherwise, the boards are only connected to each other on lines 48 , 47 , 49 , 11 , 75 and 50 and in addition the output of the effective penultimate sliding space (output 03 ) of the second circuit 6 '' with the input D 0 of the first circuit of the next Board connected. This allows shift registers of any length and chains of LEDs of any length to be constructed.

Fig. 5 shows a block diagram of the switching mechanism 5 which controls the transmitter. An oscillator 79 generates pulses at a first frequency. These pulses are divided down in a downstream counter 80 . The counter 80 here is a binary counter, the plurality of binary outputs of which are connected to inputs of decoders 81 , 82 , 83 and 84 . In the exemplary embodiment shown, 1 out of 16 decoders are used which have 16 output lines, of which only one is activated at its input depending on the 4-digit binary code.

These four decoders 81-84 generate pulse-shaped signals which are explained in detail in connection with FIG. 7. The decoder 81 is connected with its inverting enable input E across to the inverted output Q-across of the first shift location 7 of the ring shift register (line 85 ). This ensures that a signal appears at the output of the decoder 81 only when the first shift location 7 of the ring shift register 6 has a logical "1". As a result, this signal is used to design the coding of the first transmitter diode 2 differently from that of the other transmitter diodes. The other decoders 82 , 83 and 84 , on the other hand, operate independently of an enable signal, so that they work continuously. The outputs of all four decoders 81 to 84 are connected to the input of an OR gate 86 , the output of which is connected to an input of an AND gate 87 . The other input of the AND gate 87 is connected to an output of the counter 80 , specifically to its lowest bit position, which therefore has the highest frequency. This latter signal determines the pulse duration of the infrared pulses, while the output signal of the OR gate 86 determines the time (and the number) of the individual pulses for the control of the transmitter diodes. The output of the AND gate 87 is connected via an amplifier 88 to the control input of a controllable switch 89 . The output of switch 89 is connected to line 50 .

The output of the decoder 82 is additionally connected to the clock line 47 and to a counter input of a counter 90 , the output of which is connected to the clock input of a flip-flop 91 . The flip-flop 91 is a D flip-flop, the D input of which is constantly connected to the potential of a logic "1". The non-inverted output Q of the flip-flop 91 is connected to an input of an OR gate 92 , the other input of which is connected to the line 11 , which in turn is connected to the output of the last stage 10 of the ring shift register 6 . The output of the OR gate 92 is connected to the D input of the flip-flop 7 , which forms the first shift location of the ring shift register, but is not integrated in the integrated circuit 6 '( Fig. 4), but as a separate, of signals independent component is realized on the enable line 48 . The non-inverted output Q of the flip-flop 7 is connected to the line 14 and to the reset input MR of the flip-flop 91 . The clock input of the flip-flop 7 is connected to the clock line 47 . As mentioned, the inverted output Q across of the flip-flop 7 is connected via line 85 to the enable across input of the decoder 81 . A detection circuit 94 , which generates an output signal a short time after the supply voltage has been switched on for the first time, is connected to an input of a NAND gate 93 , the other input of which is connected to line 85 . The output of the NAND gate 93 is connected to a reset input of the counter 90 . Another detection circuit 94 ', which is constructed in accordance with the detection circuit 94 , is connected to an input of an AND gate 95 , the other input of which is fed via a driver 96 to the output signal of the decoder 84 . The output of the AND gate 95 is connected to the enable cross line 48 .

The operation of the rear derailleur of FIG. 5 is explained below. Immediately after switching on the mains voltage, the oscillator 79 begins to work and generate pulses which are divided down in the counter 80 . The detection circuit 94 'causes the enable cross line 48 to assume the state "1" for a short time. As a result, the outputs of the D flip-flops of the ring shift register 6 are switched to the high-resistance state and are pulled to ground potential by the pull-down resistors 72 , 73 ... 74 , so that the entire ring shift register is erased at the next clock pulse. The binary counter 90 is cleared by a pulse generated by the detection circuit 94 and then clocked with the clock signal. After 128 clock pulses, its output changes to a "1", as a result of which the flip-flop 91 takes over this signal on the next clock edge. A "1" is thus inserted into the first flip-flop 7 of the transmission shift register and the first transmission diode is released for activation. At the same time, this "1" in the first flip-flop 7 resets the flip-flop 91 , so that no ones can be written into the flip-flop 7 with further clock pulses. When a "1" is written into the first flip-flop 7 , a "0" appears at its inverted output Q-across, which activates the decoder 81 and permits the generation of a pulse. The other decoders 82 , 83 and 84 also continuously generate pulses, the pulses of the four decoders 81 to 84 being out of phase with one another. (See pulse trains I 84 , I 83 , I 81 and I 48 of FIG. 7). It should be emphasized that a pulse only appears at decoder 81 when the first flip-flop 7 of the ring shift register is set to a "1". Thus, when the first flip-flop of the ring shift register is set, four pulses appear at the output of AND gate 87 (see pulse train I 50 of FIG. 7), so that the first light-emitting diode 2 , activated by flip-flop 7 , emits four pulses . With the next clock pulse, the first flip-flop 7 is reset and the second flip-flop 8 is set. The decoder 81 is switched off. Only three pulses then appear on line 50 , specifically the first, second and fourth pulses, based on the activation of the first transmitter diode, while the third pulse is suppressed because the decoder 81 is switched off. This fourth pulse coincides with the enable quer signal on line 48. With this signal, the outputs of the ring shift register - with the exception of the first flip-flop 7 - are switched to high resistance, so that the transmit diode switches 57 , 58 ... 59 are blocked by the pull-down resistors 72 , 73 ... 74 and none Current can flow through the transmitter diodes. The fourth pulse on line 50 is thus also effectively suppressed. If one of the transistors 57 , 58 ... 59 working as a transmitter diode switch is alloyed, a current flows against it and a light pulse is generated. This pulse is detected by the receiver and leads to the switching command "Protective field not free". On the other hand, when the first light beam is triggered, this pulse is deliberately generated and is a necessary component of the identifier in order to synchronize the receiver with the transmitter.

With each further pulse on the clock line 47 , the ring shift register is advanced by one step and the next following light-emitting diode is activated. If the chain is switched through, the last flip-flop stage 10 is activated; a "1" appears on line 11 . This feedback signal leads to a new setting of the first flip-flop 7 via the OR gate 92 . As a result, the decoder 81 is released again and a new run begins. Each time the first flip-flop 7 is set , the counter 90 and the flip-flop 91 are forcibly reset, so that during normal operation the first flip-flop 7 receives the "1" only from the last flip-flop 10 . If for some reason the ring shift register 6 does not contain "1", the counter 90 will set the flip-flop 91 after a predetermined number of clock pulses (for example 128 or 256), which then results in a "1" in the first Flip-flop 7 of the ring shift register 6 is inscribed ben.

Fig. 6 shows a more detailed circuit diagram of the Schaltwer kes 5th In the exemplary embodiment in FIG. 6, most of the components are implemented by integrated circuits. Decoder 81 is a 1-out-of-16 decoder demultiplexer of the type HEF 4514B. The three decoders 82 , 83 and 84 are realized by a single module of the same type, the different outputs of which A 82 (Q 0 ), A 83 (Q 1 ) and A 84 (Q 3 ) the pulses I 82 , I 83 and I, respectively 84 of FIG. 7 lead.

The oscillator 79 and the binary counter 18 are realized by an integrated circuit of the type HEF 4060 B, which to set the desired frequency of, for example, 9.216 MHz with an external crystal 95 ', external capacitors 96 ' and 97 and external resistors 98 and 99 is.

Counter 90 is an integrated circuit of the type HEF 4040 B. It is a 12-stage binary counter with clock input, an overwriting, asynchronous master reset input (MR) and twelve buffered outputs "0 zero" to "0 11 ". A logical "1" at the MR input clears all counter levels and brings all outputs to "0" regardless of the clock input.

The flip-flops 91 and 7 are D-type flip-flops of the type HEF 4013 B. The gates 86 and 92 are components of the type HEF 4072 B. The gates 87 , 93 , 95 and 96 are Nand gates of the type HEF 4011 B. where gate 96 is used here to invert the drivers. Driver 88 is a type HEF 4049 B device which is an inverting driver so that gates 87 and 88 in combination act as an AND gate. In the same way, the inverting driver 96 and the NAND gate 95 act as AND gates. The output of the flip-flop 7 as well as the clock line 47 and the enable line 48 still contain non-inverting drivers 100 , 101 and 102 , which are implemented by an integrated circuit of the type HEF 4050 B.

The detection circuits 94 and 94 'are realized by a voltage divider between the supply voltage and ground from a series circuit of resistors 103 and 105 and capacitors 104 and 106 , respectively. After switching on the supply voltage, the capacitors 104 , 105 are charged with a time delay, so that the subsequent gate 93 or 95 only switches when the respective capacitor is charged to a certain voltage value.

The line 11 is connected to ground via a pull-down resistor 107 . The driver transistor 89 is connected as follows: its gate connection is connected to the output of the driver 88 and via a resistor 107 'to ground. Its drain connection is connected to line 50 and to ground via a capacitor 108 . Its source connection is connected directly to ground.

FIGS. 7 and 8 show timing diagrams of the various inputs and outputs of the devices. The reference symbols on the individual pulse trains correspond to the reference symbols of the components on which these pulse trains occur. The pulse train designated "I-Red-Pulse Current" in FIG. 7 shows the light pulses actually emitted by the respectively activated light-emitting diodes. From this it can be seen that the first light emitting diode emits four consecutive pulses, while all the others emit only two pulses. It can also be seen that only groups of three pulses are generated for the light-emitting diodes 2 to n-1, the fourth pulse being suppressed by the enable signal I 48 . The third pulse is not generated at all since the pulse train I 81 has a zero at this time.

Fig. 8 shows further pulse trains on a different time scale. When the supply voltage is switched on, it rises gradually instead of suddenly due to various capacities. The detection circuit 94 follows the rising edge with a certain delay and thus forms the master reset signal for the counter 90 .

The detection circuit 94 'has a larger Zeitkonstan te, so that the enable signal initially formed when switching on (I 48 ) is suppressed longer, but is subsequently formed by the decoder 84 . In the switch-on phase, the counter 90 must first have counted a predetermined number of here 128 pulses before a pulse (I 90 ) is present at the counter output. The rising edge of this pulse sets the flip-flop 91 . The next clock pulse (I 47 ) then sets the output of the first flip-flop 7 , the output of which in turn sets the second flip-flop 8 on the next rising clock edge, but its output is briefly paused by the enable signal I 48 has to suppress the fourth pulse.

Figure 9 shows a more detailed block diagram of the receiver. Basically, the receiver is constructed similarly to the transmitter, but with the essential difference that the receiver is largely implemented in two channels. Both channels work completely independently of one another and are only linked to one another by the comparator 23 ( FIG. 2). However, both channels share the photo detectors 16 ... 18 . To select the signals generated by the photodetectors 16 to 18 , ring shift registers 26 and 27 are also used here, analogously to the transmitter, which also have one more shifting location than the photodetectors available. A "1" inserted into lines 28 and 32 via lines 38 and 39 is pushed through the ring shift register by a clock signal on lines 109 and 110, respectively. An enable switch 111 to 114 or 115 to 118 is assigned to each sliding position 28 to 31 and 32 to 35 . All enable switches of a channel are controlled via a common enable cross line 119 or 120 . A separate analog switch 121 , 122 or 123 is assigned to each photodetector 16 to 18 . Each analog switch has two control inputs that are connected to the assigned enable switches of the two channels. Furthermore, each analog switch has two signal outputs, each of which is connected to one of the two received signal lines 36 and 37 of the two channels. Finally, each analog switch has a signal input which is connected to the associated photodetector. A control signal at a control input of the analog switch causes the signal input to be switched through to the signal output. As a result, the output signal of that photodetector whose assigned sliding position has a "1" is given to the respective signal line 36 or 37 . If a "1" is pushed through the ring shift registers 26 and 27 , only one photodetector is activated as a result. The outputs of the enable switches 111 to 113 and 115 to 117 are each connected via lines 124 , 125 , 126 , 128 , 129 and 130 to the D input of the next sliding place. The output of the last enable switch 114 and 118 is connected to the data line 40 and 41 via a line 127 and 131, respectively. A jumper 137 or 141 is inserted in each of the lines 127 and 131 at the actually last sliding place. In this way, boards can also be cascaded with the circuit according to FIG. 9, so that chains of any length can also be built here. For this purpose, the lines 40 , 109 , 119 , 36 , 37 , 120 , 110 and 41 of similar boards are interconnected. In addition, the outputs of the penultimate sliding places 30 , 113 and 34 , 117 are led to lines 132 and 133 , these lines 132 and 133 being connected to lines 38 and 39 of the next board.

Here, too, the last sliding area has a special function. It does not control an analog switch. If it is controlled, it can be checked whether all analog switches are switched off. It should also be emphasized that the analog switches 121 to 123 are each separate components and are not housed in a single integrated circuit. As a result, the individual photodetectors are decoupled well, so that no interference from side talk occur. Also, the other analog switches could not be affected by a defect in an analog switch.

Fig. 10 shows a more detailed circuit diagram of the receiver according to Fig. 9. Similar to the transmitter, here too the ring shift registers 26 and 27 are each by two integrated circuits 26 ', 26 ''and 27 ', 27 '' of the type HEF 40374 B realized.

The analog switches 121 to 123 are explained in more detail in connection with FIGS. 15 and 16. Since each analog switch is in principle also largely constructed in two channels, two independent power supplies via lines 142 and 143 are also provided and a common line 144 for both channels.

The clock lines 109 , 110 and the enable cross lines 119 , 120 of both channels are each connected via pull-up resistors 134 , 135 , 138 , 139 to the supply voltage. If several boards are connected in cascade, these resistors are only present on the last board, so that lines 119 , 109 , 110 , 120 have a defined termination and a current flow is forced until the end of the cascade. In addition, the D input of the first flip-flop of each board can be connected to supply voltage by means of resistors 136 , 140 , which has the purpose of forcing a defined current flow when using plug connections between different boards.

Fig. 11 shows a block diagram of the control unit of a channel of the receiver. As can be seen from FIG. 2, separate control units with the same structure are provided for each channel. The lines 40 , 109 , 38 and 119 of FIGS. 9 and 10 are connected to the lines of the same name in FIGS. 11 and 12. The microcontroller 19 is used to generate control signals on lines 119 , 38 and 109 , to evaluate the signals arriving from the receiver on lines 36 and 40 and to control an input / output unit, which is explained in connection with FIGS. 13 and 14 becomes. Pulses on line 36 pass through a controllable switch 42 and a two-stage amplifier 21 ', 21 ''to two comparators 146 and 149 , which are set to different switching thresholds. The respective comparator only responds if its input signal is above this switching threshold. The output signals of the comparators 146 and 149 are each fed to a non-retriggerable monostable flip-flop 147 and 150, respectively. The rising edge of the signals output by the comparators 146 and 149 triggers these monostable flip-flops 147 , 150 , which generate pulses of constant duration (approx. 2 μs pulse width). The pulses arising at the monoflop outputs are each counted in a binary counter 148 and 151 and fed via the controllable switches 42 ', 42 ''inputs of the microcontroller 19 .

The purpose of the two comparators 149 and 146 is to evaluate the amplitude of the received light pulses in order to determine whether the photodetectors or the light emitting diodes are dirty. If there is no contamination, both comparators will generally respond to every light pulse. With increasing pollution of the light path, the amplitude of the received light signals decreases until only the comparator 149 responds with the lower threshold. The light grid is still working properly. However, an output signal is generated which indicates that contamination is beginning.

The purpose of the monoflops 147 , 150 and the counters 148 , 151 is as follows: Very short pulses or high frequencies are used on the light transmission path. However, microcontrollers for such high frequencies are susceptible to interference and are also extremely expensive. Thanks to the monoflop and a fast counter, you can use microcontrollers that work much slower. In the present exemplary embodiment, the cycle time of a light pulse is approximately 1.6 µs. The microcontroller 19 used , on the other hand, takes approximately 5 to 8 microseconds to correctly evaluate an edge. Since there is as much time available for evaluating the light pulses received by a single photodetector as there is the pause length between the pulses of successive light-emitting diodes, the fast counter can count the individual pulses and the significantly slower microcontroller can then still correctly count the result evaluate. This switching principle for evaluating pulses with a high frequency by means of a significantly slower microcontroller can also be easily applied to other areas.

As already mentioned, the microcontroller has various output lines, of which lines 109 , 38 and 119 drive the receiver. An amplifier 152 , 153 and 154 is switched on in each of these lines.

After switching on the voltage supply, the microcontroller first carries out a self-test and then generates a signal on line 119 which switches the outputs of the ring shift registers to high resistance, so that all register stages are reset via pull-down resistors on the next clock pulse on line 109 , with which all analog switches and thus effectively all receiving diodes are switched off. The first shifting location is then set via a signal on line 38 in connection with the next clock pulse and the first receiving diode is thus activated. Light pulses received by this activated receiving diode are then evaluated on the way up to the counters 148 and / or 151 . The microcontroller 19 then checks whether the count content of the counters 148 and / or 151 corresponds to the identifier of the first light beam, that is to say four pulses have been received here. The counters 148 and 151 are then reset by a signal on a line 155 from the microcontroller. If the check of the count contents of the counters reveals that the correct identifier was not received, the first receiving diode remains activated until the identifier for the first beam has been received. Only then are the transmitter and receiver synchronized with each other. As soon as the first receiving diode has received the identifier of the first beam, the next clock signal is generated on the clock line 109 , with which the ring shift registers are advanced and the first receiving diode is switched off and the next is activated. In a corresponding manner, the next receiving diode is then queried and checked whether the corresponding identifier, in this case two light pulses, has been received. If this is the case, it is checked whether a signal on line 40 indicates that all the receiving diodes have been scanned. If the test result is negative, the last activated receiving diode is switched off and the next one is activated. This cycle is repeated until all of the receive diodes have been scanned. Only then does the microcontroller generate the "Protective field free" switching command. Then a new cycle begins with the activation of the first receive diode. If a check of the identification of the second to last light beam gives an error, the switching command "protective field not free" is generated and the program of the microcontroller goes back to the initial self-test. This program flow is shown in detail in FIG. 17.

During an external test request, the switches 42 , 42 'and 42 ''are switched off, for example by a corresponding signal on a control line 157 , so that no light pulses are evaluated during this phase. This state simulates an "object in the protective field" for the microcontroller.

Both microcontrollers 19 and 20 ensure mutually whether the microcontroller of the other channel has also carried out a complete run with the correct received signal. For this purpose, the microcontroller 19 sends a corresponding signal to the microcontroller 20 via a line 162 and in turn receives the corresponding signal from the microcontroller 20 via a line 165 . Only when this "hand shake" was successful is a dynamic output signal to an input / output unit ( FIG. 13) given via an output line 158 and an amplifier 159 . This dynamic output signal consists of pulses with a fixed clock frequency (e.g. 18 kHz) that are generated as long as both microcontrollers recognize the "protective field free" state. Due to the dynamic signal, all types of static errors of the microcontroller are recognized by the comparator circuit and do not lead to an incorrect display "protective field free". The line 162 is connected to the input / output unit via an amplifier 163 and is connected there to a light-emitting diode which indicates the state "protective field free" or "not free" determined by one channel. Another output line 160 of the microcontroller is connected via an amplifier 161 to a further light-emitting diode which is used for service purposes.

To monitor the microcontroller, a "watchdog circuit" 45 is provided, which is connected to an input line 166 and an output line 167 of the microcontroller 19 . To generate the clock pulses, an oscillator 168 is connected to the microcontroller 19 , which generates the required clock frequency under quartz control.

A comparator 156 connected to the switch 42 also serves, as will be explained in detail in connection with FIG. 12, to monitor the state of the analog switches 121 ... 123 during the activation of the last sliding place 31 . The control input of switch 42 is therefore connected to line 40 . While the last sliding place 31 or 35 is activated, the pull-up resistor on line 36 is disconnected via controllable switch 42 . This enables the microcontroller to use comparator 156 to check whether all the analog switches have switched off.

Finally, a line 164 is also shown, which serves as a selection input for activating or querying the hand shake lines 162 and 165 .

Fig. 12 shows a more detailed circuit diagram of the control unit of a channel according to Fig. 11. The light implus on line 36 are capacitively coupled via a capacitor 169 to the input of an inverting amplifier 21 '. For this purpose, an amplifier module of the type LM 318, which is externally connected in the usual way, is used, which causes low distortions with a short rise time and a relatively large bandwidth. The first amplifier stage 21 'has an amplification of approximately 25. The subsequent amplifier stage 21 ' is also constructed as an inverting amplifier with an amplification of approximately 20. The output of the second amplifier stage 21 'is fed to the inverting inputs of the comparators 146 and 149 . These comparators are modules of the type LM 311. The reference inputs of both comparators are located at different points of a voltage divider, which consists of resistors 170 to 174 and is between ground and a supply voltage. In this context, it should be noted that the supply voltages marked with an asterisk (*) come from a different voltage source than the supply voltages marked without an asterisk (*). These two supply voltage sources are completely independent of one another. Another tap of the voltage divider 170-174 leads to the non-inverting inputs of the two amplifier stages 21 'and 21 ''. As a result, both non-inverting inputs are connected to the same potential. The outputs of the two comparators 146 and 149 are connected to positive voltage via pull-up resistors 175 and 176, respectively, and to an input of the monoflops 147 and 150, respectively. These two monoflops are arranged in an integrated module of the type 74 HC 123, which is externally connected by capacitors and resistors to adjust the pulse time in the usual way. The outputs of the two monoflops 147 and 150 are connected to counter inputs of the counters 148 and 151 , which are also implemented in a module of the type 74 HC 4520. The binary outputs of the two counters 148 and 151 are connected to a driver circuit 42 ', 42 '', which is a module of the 74 HC 365 type. The signal outputs of the driver circuit are each connected to ground via a pull-down resistor 177 and to signal inputs of the microcontroller 19 . Steuerereingän ge of the driver 42 ', 42 ''are connected to line 157 . An external test request on this line means that all driver outputs, regardless of the inputs, assume the high-impedance state. As a result, the pull-down resistors 177 take effect and produce the state “0” at the inputs of the microcontroller 19 . This is interpreted by the microcontroller as the counter reading of counters 148 and 151 and evaluated as an "object in the protective field".

As already mentioned above, the last sliding position of the ring shift registers 40 , 41 does not control an analog switch. A "1" at the output of this sliding space reaches line 40 and a base resistor 178 and a transistor 179 , the collector of which is connected via a resistor 180 to a supply voltage and at the same time to an input of microcontroller 19 . The emitter of transistor 179 is connected to ground and via a resistor 181 to its base. Finally, the collector of the transistor 179 is connected to the gate electrode of the switch 42 designed as an FET transistor, which in turn is connected to ground via a resistor 182 . The drain electrode of the transistor 42 is connected to the supply voltage via a resistor 183 . The source of transistor 42 is connected to line 36 upstream of capacitor 169 and to ground via resistor 184 . Resistors 183 and 184 form a voltage divider. As long as there is no pulse on line 40 , transistor 179 is blocked and transistor 42 is turned on via resistor 180 . Thus, the voltage divider 183 , 184 is effective. If the last shift place of the ring shift register leads to a "1", the transistor 179 becomes conductive and the transistor 42 blocks. The voltage divider 183 , 184 is thus disconnected. Resistor 184 acts as a pull-down resistor and connects high-resistance line 36 to ground potential. The inverting comparator 156 connected to line 36 reacts to this level with a positive output signal which is fed to an input of microcontroller 19 . It is then checked whether all analog switches have switched off at this time. Should an analog switch z. B. because of an alloyed transistor have not switched to high resistance, line 36 assumes the potential of a low-impedance impedance converter output. The output of the comparator 156 switches to "0". For all sliding spaces except the last one, the comparator 156 must show the level "0". At the last sliding place, however, it must change to "1". The effectiveness and function of the shutdown control can thus be checked by the microcontroller.

The microcontroller is an 8-bit 1-chip microcontroller of type 80 C 51. In addition to a 4 K byte program memory, it also has 128 byte RAM and 32 I / O ports. When using a 12 MHz crystal 168 for the oscillator, the command execution time is approximately 1 µs. The MAX 693 module is used as the "watchdog" 45 . Further details of the external wiring of the individual modules can be found in FIG. 12 and in the data sheets for these modules. These external circuits are irrelevant for explaining the principle of operation of the invention.

Fig. 13 shows a block diagram of the input / output unit of the receiver, which contains the fail-safe comparator 23 and two relays as essential components.

The dynamic output signals of the microcontrollers of both channels reach the comparator 23 via lines 158 and 158 'and amplifiers. The output signals of the comparator 23 each control a transformer converter 185 or 186 , which operates when a dynamic signal is present in a predetermined frequency range at its input. These transformer converters provide the energy required to drive relays with electrical isolation between the primary and secondary side, control signals being applied to the primary side and the energy source also being connected on the primary side. In the illustrated embodiment, the transformer converter is a flyback converter. But it can also other types of transducers such. B. flux converters are used. Each transformer converter 185 , 186 controls a relay 187 , 188 assigned to it. The function of the comparator 23 is carried out in relay contact technology by relay contacts 189 , 190 , 191 , 192 of the two relays' 187 and 188 . In the first channel of the comparator, a normally open contact 191 of the relay 187 and a normally closed contact 189 of the relay 188 is arranged in parallel. Correspondingly, a normally closed contact 190 of the relay 187 and a normally open contact 192 of the relay 188 are present in the second channel of the comparator. The respective contacts 189 , 191 and 190 , 192 switch through the energy supply for the associated transformer converters 185 and 186 , the status of the relay contacts being indicated by display elements 199 , 200 , 201 , 202 . Further display elements te 203 to 206 are connected to lines 160 , 162 , 160 'and 165 , respectively. The output signal of the transformer converters 185 , 186 is supplied to the assigned relay 187 , 188 via rectifiers 197 , 198 and per channel via two controllable switches 207 , 208 and 209 , 210 in series.

Both relays 187 , 188 have additional contacts 193 , 194 and 195 , 196 , of which one is a work contact and the other is a normally closed contact. With these contacts 193 to 196 machine functions are controlled, in particular if the light curtain is interrupted the machine is switched off. All contacts of the relays are positively driven, so that "sticking" of individual contacts cannot lead to a malfunction.

For the description of the mode of operation it is first assumed that the controllable switches 207 ... 210 are closed. It is also assumed that all relay contacts are initially in their rest position. If a dynamic signal arrives on line 158 , the transformer converter 185 can begin to work via the (still) closed normally closed contact 189 of the relay 188 of the other channel. After rectification in rectifier 197, its output signal excites relay 187 . The normally open contact 191 thus closes and the relay 187 remains energized as long as dynamic signals are present on the line 158 .

By pulling the relay 187 , however, the normally closed contact 190 in the second channel is opened. Thus, the transformer converter 186 is completely disconnected from the power supply and can no longer start to work. From this it can be seen that both relays 187 and 188 can only pick up when the dynamic control signals on lines 158 and 158 'occur approximately simultaneously. If, on the other hand, one of the transformer converters 185 or 186 has started to work and the other one has not yet started, the other can then no longer start its work. If, on the other hand, the dynamic output signals of both channels occur simultaneously (within a "time window"), both transformer converters 185 and 186 start their work simultaneously and can continue this through their own normally open contacts 191 and 192 even if the other transformer Converter has opened its normally closed contact in the other channel.

To monitor a machine, the relay contacts 193 to 196 are switched so that the machine can only work when both relays 187 and 188 are energized. If these relay contacts are, for example, in the power supply of the working machine, the two working contacts 194 and 196 will be connected in series, so that the working machine is only connected to the mains voltage when both contacts are closed. In the case of multi-channel machine controls, one work contact must be looped into the corresponding channel.

The controllable switches 207 to 210 are controlled by the clock controller 24 . For simple monitoring tasks, this clock control together with the controllable switches 207 to 210 can be omitted. For certain monitoring tasks, on the other hand, a "protective field free" signal should only be able to be generated after the protective field has been interrupted twice. The clock control contains a shift register 218 , the two outputs Q 1 and Q 0 of which are each connected to an input of an OR gate 219 and 223 . The output of the OR gate 219 drives the two switches 207 and 209 . The output of the OR gate 223 drives the two switches 208 and 210 . The other input of the OR gate 219 is connected to a line 221 via an opto-coupler 220 . In a corresponding manner, the other input of the OR gate 223 is connected to a line 225 via an opto-coupler 224 . The clock input of the shift register 218 is connected via an optocoupler 229 and a line 228 to the rectifier 197 of the first transformer converter 185 . To select different operating modes, the lines 221 and 225 can be connected to a voltage source 227 , which is done via switches or connectors 222 and 226 . In a first operating mode "protection operation" the connector 222 is set so that both lines 221 , 225 are connected to the voltage source. The outputs of the OR gates 219 and 223 thus always have a "1", so that the switches 207 to 210 are always closed.

In a second operating mode "clock control", however, only the line 225 is connected to the voltage source 227 via the plug connection 226 , while the line 221 is potential-free. The shift register 218 thus determines whether the OR gate 219 carries a "1" or a "0". With every first response of the transformer converter 185 , the shift register 218 is switched on by the positive edge at the output of the rectifier 197 . At the first count pulse, its output Q 0 has a "1", so that switches 207 and 209 are closed via OR gate 219 unless they are already closed by a voltage on line 221 . Only at the second count pulse does the output Q 1 of the shift register 218 lead a "1", as a result of which the switches 208 and 210 are closed via the OR gate 223 . Thus, since the transformer converter are 185 closed the switches 208 and 210 only in the second response, the relay can attract so even in the second response of the transformer converter 185 187 and 188th The shift register 218 is inserted a "1" each time the transformer converter 185 responds. For this purpose, the data input, not shown, of the shift register 218 is constantly connected to a "1", while the clock input of the shift register 218 is connected to the output of the opto-coupler 229 . In "single-ended operation", the plug connection 226 is set, so that the output Q 0 receives a "1" with each incoming clock and the switches 207 and 209 are thus closed with each clock.

In contrast, both connectors 222 and 226 are removed in two-stroke operation. Both OR gates 223 and 219 are thus only driven by the shift register 218 . After every second cycle, both outputs Q 0 and Q 1 simultaneously carry a "1".

Two-stroke operation is provided, for example, when the molding is removed and inserted manually in a press. In this case, the shift register 218 is reset by pressing a remote control after each pressing operation, so that its two outputs have a "0". For this purpose, a further voltage source 211 is provided, which is connected to the reset input of the shift register 218 via a start button 212 , a mode switch 213 of a remote control and an opto-coupler 214 .

The output of the opto-coupler 214 is also connected via an OR gate 215 to the line 157 , which transmits a start and test signal to the two microcontrollers. To generate a test signal when the power supply is initially switched on, a detection circuit 216 is provided, the output of which is connected to the reset input MR of a flip-flop 217 . The inverted Q-output of flip-flop 217 is connected to the other input of OR gate 215 . If the voltage rises when the electrical power supply is initially switched on, the detection circuit 216 resets the flip-flop 217 , so that a "1" appears at its inverted output Q-cross, which reaches line 157 . With the first actuation of the start button 212 , the flip-flop 217 is set so that a "0" is present at the inverted input. The corresponding test pulse thus passes directly from the opto-coupler 214 via the OR gate 215 to the line 157 .

Fig. 14 shows a more detailed diagram of the input / - output unit shown in FIG 13. The two transformer converters 185 and 186 are constructed on the primary side are identical, so that only the transformer converter 185 of the first channel is explained in detail.. Line 158 , which carries the dynamic output signal of the first channel, is connected via a capacitor 250 to the gate electrode of a transistor 251 , the drain-source path of which lies between the primary winding 252 of a transformer 253 and ground. A zener diode 254 and a capacitor 255 lie parallel to the drain-source path of the transistor 251 . The gate electrode is connected to ground via a parallel circuit comprising a Zener diode 256 and a resistor 257 . Line 158 is connected to a positive supply voltage via a pull-up resistor 262 . The other connection of the primary side 252 is connected to supply voltage via a resistor 258 , a diode 259 and the relay contact 189 . Furthermore, the common connection point between the resistor 258 and the diode 259 is also connected to the supply voltage with a series circuit comprising a resistor 260 , a diode 261 and the relay contact 191 .

To indicate the switching position of the relay contacts 189 and 191 , their connections connected to the diodes 259 and 261 are connected to the LEDs 199 and 200 via resistors 263 and 264, respectively. If the diode 199 lights up , this means that the relay 188 has dropped out. If it has gone out, relay 188 is energized. If the diode 200 lights up, the relay 187 has picked up. If it has gone out, relay 187 has dropped out.

Effectively, the primary side of the transformer converter is driven by transistor 251 when a dynamic signal arrives on line 158 and one of the two relay contacts 189 and 191 is closed. This signal is increased in energy and galvanically isolated on the secondary side 252 'of the transmitter 253 , rectified by the diode 197 and passed to a connection of the relay 187 . The other connection of the relay is connected via the series-connected opto-couplers 208 and 207 to the other connection of the secondary side 252 '. The opto-couplers act as controllable switches, the control of which is galvanically isolated from the switch. Parallel to the transistors acting as switches of the opto-couplers 208 and 207 are Zener diodes 265 and 265 '. Furthermore, parallel to the series circuit from the secondary side 252 'and the rectifier 197 are a capacitor 266 and a series circuit comprising a resistor 267 and a diode 268 . Parallel to the diode 268 is the input side of the opto-coupler 229 , which thus taps the excitation signal for the relay 187 . The transistor acting as a switch on the output side of the opto-coupler 229 is connected to a positive supply voltage via a collector resistor 269 and also as a signal output to a Schmitt trigger 270 . The output of the Schmitt trigger 270 is connected to the clock input of the shift register 218 .

The capacitor 266 acts as a time delay element for the response and dropout of the relay 187 , so that a certain phase shift between the dynamic output signals on lines 158 and 158 'of the two channels can still be compensated for and that when switching the relay contacts 189 and 191 the relay 187 does not fall off immediately. (Function of the "time window") The secondary side of the transformer converter 186 for the second channel also essentially corresponds to the structure of the transformer converter 185 for the first channel, with the exception of the opto-coupler 229 , which is not required in the second channel. Instead of the opto-coupler 229 there is a light emitting diode 229 ', which simulates the load of the opto-coupler 229 , so that both transformer converters have the same possible response. To the extent that the components of the second transformer converter 186 are identical to those of the first transformer converter and do not have a different function, they are not provided with special reference symbols in FIG. 14.

The shift register 218 , which performs the essential function of the clock control, is a module of the type HEF 4015 B. Its D input (data input) is permanently connected to a positive supply voltage, so it always carries a logical "1". With each clock signal from the Schmitt trigger 270 , a further "1" is thus written into the shift register 218 . Its first output Q 0 controls the input side of the two opto-couplers 209 and 207 via a driver 271 . Its second output Q 1 controls the opto-couplers 210 and 208 in a corresponding manner via a driver 272 . The light-emitting diodes on the input side of these opto-couplers 210 and 208 or 207 and 209 are each connected in series and are each connected to positive supply voltage via light-emitting diodes 273 and 274 and resistors 275 and 276 . The light-emitting diodes 273 and 274 indicate the switching position of the assigned opto-couplers 208 , 210 and 209 , 207 , respectively.

Whether the relays 187 and 188 can pick up when the protective field is free depends on the contents of the shift register 218 in the "single-ended" (connector 226 set, connector 222 removed) and "two-cycle" (both connectors 226 and 222 removed) operating modes. The input of the shift register is statically set to "1". As soon as the protective field state changes from "not free" to "free", a positive edge is created at the clock input of the shift register 218 by the oscillation of the transformer converter 185 , the opto-coupler 229 and the Schmitt trigger 270 . A shift process is triggered and thus a clock signal is stored. In single-ended operation, the opto-couplers 21 53232 00070 552 001000280000000200012000285915312100040 0002003939191 00004 531130 and 208 are constantly activated by the voltage source 227 , so that with each cycle via the output Q 0 of the shift register 218 the other opto-couplers 209 and 207 switch through. In the timing mode, only after the second cycle both shift register outputs Q 0 and Q 1 have a "1", so that all opto-couplers 207 , 208 , 209 and 210 have switched through only in the second cycle.

The components for the selection of the operating mode are constructed as follows: The supply voltage source 227 , buffered via a capacitor 277 , can be connected to line 225 via plug connector 226 or to line 221 and 225 via plug connector 222 . The line 225 is via an opposing stand 278 and a light-emitting diode 279 for the operating mode display with the input (light-emitting diode part) of the opto-coupler 224 connected. The other input is on ground. A parallel circuit comprising a Zener diode 280 and a capacitor 281 is located between the line 225 and ground. The switching transistor part of the opto-coupler 224 is connected to a positive supply voltage via a collector resistor 282 and also to the control input of the opto-coupler 210 via two drivers 283 and 284 . The outputs of the driver 284 and the driver 272 are electrically connected to one another, whereby the OR function 223 is obtained as a "wired-OR".

The line 221 is connected to components in the same way as the line 225 , so that they no longer have to be described separately. The last driver in line 221 is connected to the output of driver 271 , so that here too a wired-OR circuit 219 is created for the control of opto-couplers 209 and 207 .

The input for the opto-coupler 214 (remote start, test) is switched in the same way as for the opto-couplers 220 and 224 . The output of the opto-coupler 214 is connected to the clock input of the flip-flop 217 via a series circuit comprising a resistor and three drivers 286 . As soon as the start button 212 is pressed with the switch 213 closed, a pulse appears at the clock input of the flip-flop 217 . The inverted output of flip-flop 217 is connected to line 157 via a diode 287 . Furthermore, the output of the driver 286 is connected to the line 157 via the series circuit comprising a driver 288 and a diode 289 , which likewise realizes a “wired-OR function” of the OR gate 215 . The D input of flip-flop 217 is always at a positive supply voltage. The reset input "CLR" of the flip-flop is connected to a voltage divider consisting of a capacitor 290 and a resistor 291 , this voltage divider being between the positive supply voltage and ground. When the supply voltage is switched on, the capacitor 290 is charged, so that the flip-flop 217 is reset a short time after the supply voltage has been switched on, in accordance with the time constant of the voltage divider. This signal on line 157 causes the outputs of the drivers in the control units to assume the high-impedance state. Due to the connection with pull-down resistors, this is assessed by the microcontrollers as an "object in the protective field". Interrupting the circuit 211 , 212 , 213 causes the flip-flop 217 to tilt. The drivers of the control unit become conductive. The simulation "Object in the protective field" is thus canceled. After this initial start or remote start after switching on, the status "object in protective field" is simulated in the control units for each external test request.

Fig. 15 shows a block diagram of an analog switch 121 ... 123 of Figs. 9 and 10. Each analog switch has a "data" input 292 which is connected to the anode of the respective photodiode. This input 292 is connected to the inputs of two operational amplifiers 293 and 294 , which have a very high-resistance input and a low-resistance output resistance. The outputs of the operational amplifiers are each connected to lines 36 and 37 ( FIGS. 9 and 10) via a controllable switch 295 or 296 . The control inputs 297 and 298 of the switches 295 and 296 are connected to the assigned outputs of the ring shift registers 26 and 27 ( FIGS. 9 and 10).

Fig. 16 is a detailed circuit diagram of the analog switch shown in Fig. 15. As the amplifier 293 and 294 are here operational amplifier of type TL 081 used with JFET input. The non-inverting inputs of these operational amplifiers are connected via a coupling capacitor 299 to the input 292 . Furthermore, the two non-inverting inputs of the operational amplifiers 293 and 294 are connected to a voltage divider made up of resistors 300 and 301 , the voltage divider lying between the positive supply voltage and ground. The inverting inputs of the operational amplifiers 293 and 294 are fed back to the respective output. Furthermore, the outputs of the operational amplifiers 293 and 294 are connected to the output lines 36 and 37 via the controllable switches 295 and 296 which are designed as transistors. In the specific case, the outputs of the operational amplifier are connected to the collector of the transistors, so that the collector gate-emitter path represents the switch. The base of transistors 295 and 296 is connected to a voltage divider consisting of resistors 302 , 303 and 304 , 305 , respectively, these voltage dividers being connected to ground on the one hand and to control connections 297 and 298 on the other hand. The input of the coupling capacitor 299 is finally connected to ground via a resistor 307 .

An output signal of the connected photodiode passes through the input 292 and the coupling capacitor 299 to the two operational amplifiers 293 and 294 . If the two transistors 295 and / or 296 are turned on by a signal at the inputs 297 and 298 , the output signal of the operational amplifiers reaches lines 36 and 37 .

It should also be emphasized that the two operational amplifiers 293 and 294 are connected to independent voltage sources, the voltage of the one voltage source being identified by a "*".

FIGS. 18 to 23 show modifications of the receiver and in particular the input / output unit of receptions and seminars gers. Insofar as the individual parts correspond in terms of circuitry or function to the parts described so far, they have the same reference numerals as in the figures described so far. The modifications are additional functions such as contact monitoring of the relay contacts (external device monitoring), restart interlock and setting of various operating modes.

Accordingly, a line 308 leading to the comparator 23 for the external device monitoring is shown in FIG . Furthermore, a restart interlock 309 , which can be controlled by two lines 310 and 311, is inserted between the clock controller 24 and the output line 25 to the relays. Finally, a line 312 leads to the clock control 24 , with which the operating mode can be set and a line 313 branching off from the line 44 for a clock clearing. Otherwise, FIG. 18 corresponds completely to FIG. 2.

Fig. 19 shows a block diagram of the input / output unit of the receiver according to the modification of the invention. The modifications compared to FIG. 13 become clear from FIG. 19.

The two lines 158 and 158 ', which carry the dynamic output signals of the two channels, are here via additional optocouplers 314 and 315 to the comparator 23 . In the input circuit of the comparators of both channels to the normally closed contact of the other channel there is a controllable switch 316 or 317 , with which the function of the restart interlock is implemented. Details of this are explained in connection with FIG. 23. Furthermore, a further controllable switch 318 and 319 is provided in both channels in the same input circuit, via which the function of the contactor monitoring is implemented. Should relay contacts of the contactors actuated by the operating relays 187 , 188 stick, this is recognized, which the switches 318 and 319 do not close and prevent the transformer converters 185 and 186 from working.

Furthermore, controllable switches 320 and 321 are provided in the control for the relays 187 and 188 , which are integrated in the function of the mode selection. These switches 320 and 321 are controlled by an OR gate 322 and only enable relays 187 and 188 to respond if one of the three inputs of OR gate 322 has a logic "1". The three inputs come from:

• a) the optocoupler 220 (line 221 ) for an operating mode;
• b) an optocoupler 338 which provides a signal on each clock of the clock controller;
• c) an AND gate 323 .

The two inputs of the AND gate 323 are connected to the operating mode selection (optocoupler 224 ; line 225 ) and to the clock control (optocoupler 338 ). The output of the AND gate 323 carries an output signal only when the "single-ended" mode is selected and the clock control indicates that a clock has expired.

The output circuits contain controllable switches 324 , 327 , 328 and normally open contacts 325 , 326 , or normally closed contacts 329 , 330 of the two relays 187 , 188 . Other monitoring circuits (lines 331 , 332 ) control the switches 318 and 319 . Controllable switches 316 and 317 are controlled via an OR gate 334 with two inputs. A short signal from a timer 333 is supplied to one input to release a restart interlock. A signal is fed to the other input via line 335 when the restart interlock is switched off. The input / output unit also includes a line 337 which serves for signals for a remote-controlled start, a test and for deleting a cycle, an optocoupler 336 also being provided in this line.

Finally, the rectifier 197 also emits a signal which is supplied to the clock control via an optocoupler 340 and which in each case carries the edge of a signal which excites the relay 187 .

Fig. 20 is a more detailed diagram of the input / output unit shows the receiver according to the modification of the invention. Insofar as individual components match the circuit diagram in FIG. 14, they have the same reference numerals.

In principle, two transformer converters 185 and 186 are also provided for the two channels. By means of various external circuits which are shown in FIGS. 21 and 22, however, additional functions can be implemented. The transformer converters 185 and 186 work - in the same way as explained in connection with FIG. 14 - if they are connected on the primary side (windings 252 ) to the voltage source 227 via relay contacts 189 or 190 or 191 or 192 , and if the respective transistor 251 with the dynamic output signal (lines 158 , 158 ', optocouplers 314 and 315 ) are applied. Here too, the same principle is applied that the two transformer converters can only start to work within a limited time window, otherwise the converters are blocked by contacts 189 to 192 .

Both relays 187 and 188 can only be excited when the controllable switch 320 designed as a transistor is closed. The two leads to the counter potential of the excitation of the relays 187 and 188 are together ruled out to the collector of the transistor 320 , the emitter of which is connected to the secondary side of both transformer converters via a common line. Only when the transistor 320 is conductive, the relays receive the counter potential required to respond. The transistor 320 is operationally involved in the clock control. The transistor 320 is turned on by the following signals:

• 1. Supply voltage on line 221 , which arrives at the base of transistor 320 via optocoupler 352 . If the operating mode "guard-only mode" is selected, the transistor 320 is always switched on.
• 2. A signal coming from the clock controller via the optocoupler 339 and appearing on the second cycle;
• 3. A third clock control signal. This signal is only generated if both series-connected optocouplers 353 and 338 are activated. The optocoupler 353 is activated via the line 225 when the operating mode "one cycle" is set; the optocoupler 338 receives a cycle signal at the first clock of the clock control. The AND gate 323 realizes the series connection of the two optocouplers 353 and 338 . The common connection point of the emitters of the two optocouplers 352 and 339 is realized by a wired-OR gate 322 . A third relay 351 is provided for the contactor control and restart inhibit functions, which only briefly picks up and then drops again due to external circuitry with a capacitor 333 . A normally open contact 354 of this relay is connected upstream of the two normally open contacts 191 and 192 of relays 188 and 187 and receives a supply voltage via a connection 348 , depending on the external circuitry. External wiring is via connections 341 to 350 . The connection 341 is the connection for the voltage source 227 . The connection 342 is provided for the energy supply of the first transformer converter, the connection 343 for that of the second transformer converter. The connections 344 and 345 are used for operating mode selection. Terminal 346 carries potential to pull-up resistor 262 of the first and second transformer flyback converters. The connection 349 brings the energy supply via the connection 347 to the relay 351 ; Finally, the connection 350 brings potential for the signal on the lines 337 (via an optocoupler 336 ).

Depending on the different external wiring of the connections 341 to 350 , different functions are selected which are explained in connection with FIGS. 21 and 22.

The activation of the status display diodes 199 to 202 is also somewhat different from FIG. 14. The four diodes are supplied with power via connection 346 . It is controlled via the optocouplers 355 and 356 . The optocoupler 355 is activated via the working contact 192 of the relay 187 , whereby the diode 200 is activated. If this is the case, the diode 199 is deactivated on account of the zener diode connected in series with it. If, on the other hand, the optocoupler 355 is not energized, the Zener voltage has been reached and the diode 199 lights up. The same applies to the diodes 201 and 202 .

Connections 357 , 358 and 359 are shown on the right-hand side of the circuit diagram in FIG. 20 and are connected to the connections of the same name in FIG. 23. A signal is present at connection 357 which identifies the working state of the first transformer converter 185 . Terminals 358 and 359 are inputs that receive signals from the clock controller.

Further contacts of the three relays 187 , 188 and 351 , which are looped into the circles of machines to be monitored, are generally referred to here with the reference symbol 360 .

Figs. 21 and 22 show various external Beschaltun gen the circuit of FIG. 20. In general, here are the functions "mode", "Contactor monitoring" and "reinvestment backstop" of importance. These functions are first briefly summarized.

External device monitoring

If the switching capacity of the relay contacts or the number of contacts is not sufficient for an application, one of the two channels must be controlled by a positively driven electromagnetic switching element. The inputs 342 and 343 are used to monitor these switching elements. A normally closed contact 365 of the switching element 367 controlled by the first channel is to be connected to the input 342 (contactor control I). A normally closed contact 366 of the switching element 368 controlled by the second channel is to be connected to the input 343 (contactor control II).

External start-up testing / cyclical testing / cycle cancellation

This input 350 is used to take over an external test request to the light grid. When the button 369 is opened, an intervention in the protective field is simulated in the light grid. The start-up test can thus be carried out by operating a command device connected to this input (e.g. 381 '). When used on metalworking presses, this input is used to take over the cyclical test after the dangerous closing movement of each press stroke. The third function of this input is to clear the clock of the clock memory when the light grid is used as a protective and control device for manual intervention in the protective field. A distinction is made between the operating modes "single-stroke" and "two-stroke".

In single-cycle operation, the clock control is released once Interruption and release of the protective field the startbe out of the machine. Example: A workpiece is in put a shape and the machine throws the machined  Workpiece automatically.

In "two-stroke mode", the start command is only issued after the protective field has been interrupted twice. Example: Removing the machined and inserting the new workpiece. After the dangerous closing movement has ended, the internal clock memory must be deleted by briefly opening the circuit connected to input 350 (button 369 ) in order to be ready for a new storage. No safety requirements are imposed on the entire cycle control. The protective effect of the light curtain is ensured at all times even if this module fails.

Internal restart interlock

The integrated restart function is switched on or off with a bridge at input 348 . If the internal restart interlock function is activated by the unconnected input, the internal restart interlock is locked after the light curtain is switched on, after changing the operating mode and after each entry and exit of the protective field. The switching command "Protective field not free" inevitably appears at the signal output regardless of the physical protective field status. The signal output remains in this state until a command device connected to input 350 (button 364 with make contact) is operated by hand or foot.

Operating mode

The connections 344 and 345 are used to select the operating mode. If the light curtain is only to be used for accident protection, the "Protection" operating mode must be set. If the light curtain is also to be used as a control device, the operating mode "one-stroke" or "two-stroke" must be set. If the operating mode is selected using an external selector switch, the selector switch must be used when the contacts open when changing the switch position and when the contacts do not overlap. If the operating mode is changed using an operating mode selector switch ( 370 , 371 ), the internal clock memory is cleared, so that an uncontrolled triggering of a machine operating cycle after the operating mode is selected is prevented. In addition, when changing the operating mode at the signal output of the light curtain, the switching command "Protective field not free" is generated. If the downstream control contains a restart interlock or if the internal restart interlock is activated, this is locked. The initiation of a dangerous movement is only possible after pressing the "restart interlock" command device (push button 364 ). In applications with a fixed operating mode ( Fig. 21), inputs 344 and 345 are connected with a bridge ( 262 , 263 ).

In Fig. 21, certain operating modes are permanently set by external bridges. A first bridge 361 connects the connections 341 and 346 and thus applies a constant supply voltage to the inputs of the two normally open contacts 191 and 192 , supplies the supply voltage for the diodes 199 to 202 and provides the potential for the pull-up resistor 262 .

For pure protection operation, the connections 341 and 344 are connected by a bridge 362 . As a result, the line 221 is connected to the supply voltage, so that the transistor 320 is always conductive, so that the clock control is ineffective as a result.

In contrast, in single-ended operation, the bridge 362 is removed and the connections 341 and 345 are connected by a bridge 363 . As a result, the line 225 is connected to the supply voltage, so that the optocoupler 353 is conductive. The AND gate formed by the two series-connected optocouplers 353 and 338 thus responds when a pulse appears at terminal 359 after the first clock of the clock control. In this way, the transistor 320 is turned on with each clock of the clock control.

In two-stroke mode, both bridges 362 and 363 are removed. The opto-couplers 352 and 353 block, so that the transistor 320 can only be turned on by the opto-coupler 339 . This is done by the clock control after the second clock.

The relay contacts 189 and 190 responsible for the start of work of the transformer converters 185 and 186 are not directly connected to the power supply 227 here. Rather, you get operating voltage via the Arbeitskon contact 354 of the third relay 351 and via normally closed contacts 365 or 366 external relays 367 or 368 . The relay 367 is excited by a normally open contact 325 of the first relay 187 and a normally closed contact 324 of the third relay 351 . Relay 368 is excited via a normally open contact 326 of second relay 188 and a normally closed contact 327 of third relay 351 .

A restart interlock is implemented by the normally open contact 354 of the third relay 351 . The voltage supply (connection 347 ) of the third relay 351 is connected via a button 364 which bridges the connections 347 and 349 and is connected to the voltage source 227 by the bridge 361 between the connections 364 and 341 . If the button is actuated, the relay 351 picks up briefly for a period of time which is determined by the capacitor 333 and the coil resistance of the relay 351 . This closes the normally open contact 354 , so that when the contacts 365 and 366 are closed, both relay contacts 189 and 190 are connected to the voltage source 227 , so that the two transformer converters 185 and 186 can start to work when they receive the dynamic output signals on the lines 158 and 158 'received. If both transformer converters 185 and 186 are working, then the normally open contacts 191 and 192 are closed and the further energy supply to the converters takes place via the bridge 361 and thus independently of the relay contact 354 , which is opened again a short time after the push button 364 has been pressed. If the light barrier is interrupted or the relays 187 , 188 drop out due to another error, the contacts 191 and 192 open, so that a new "restart" can only take place by closing the normally open contact 354 , that is to say by pressing the button 364 . A restart interlock is thus implemented.

The relay contacts 365 and 366 control the external relays. When the light barrier is operating properly, these relays must be energized, which is done by closing contacts 325 and 326 of relays 187 and 188 (when operating steadily, relay 351 has dropped out, so that contacts 324 and 327 are closed). Then the contacts 365 and 366 are open, so that starting the transformer converters 185 and 186 is not possible. If the external relay 367 or 368 gets stuck due to a fault despite the excitation being switched off, the contact 365 or 366 is open, so that a restart of the transformer wall is not possible. This measure monitors the switching position of the external relays and prevents sticking relay contacts that the machine to be supervised works despite a disturbed light path.

A further button 369 is provided for a manual test, which is designed as an interrupter and is located between the connections 349 and 350 . By interrupting this button 369 , a signal at the connection 337 is switched off, as a result of which a clock memory in the clock control is erased and the "object in the protective field" is reported to the microcontrollers 19 and 20 .

FIG. 22 shows another external circuit with an operating mode selector switch instead of the bridges 361 , 362 and 363 of FIG. 21. In this exemplary embodiment the contactor control and the internal restart interlock are removed. The operating mode selector switch has two mechanically parallel switches 370 and 371 , which can each take four switching positions. The switches are designed so that the distance between the input and output of the switches is interrupted when changing from one switch position to the next. This feature is important because it ensures that when the operating mode is switched, both transformer converters stop working and then have to restart. The center contacts of both switches 170 and 171 are jointly connected to connection 341 of voltage source 227 . The four contacts of switch 371 are connected as follows:

• - First position ("OFF"): contact 372 open;
• - second position ("single-ended"): contact 373 connected to terminal 345 ;
• - third position ("two-stroke"): third contact 374 open;
• - fourth position ("protective operation"): contact 375 connected to connection 344 .

The contacts of switch 370 are connected as follows:

• - First position ("OFF"): contact 376 open;
• - Second, third and fourth position: contacts 377 , 378 and 379 connected together via a line 380 to the connector 346 .

Furthermore, the connections 342 and 343 are connected via a bridge 381 to the connection 346 or via the line 380 to the three contacts 377 , 378 and 379 of the switch 370 . In the "OFF" position, the connections 342 , 343 and 346 are disconnected from the voltage supply. The transformer converters cannot start to work. In the remaining positions (second, third and fourth position), the connections 342 , 343 and 346 are connected to the voltage source 227 ; the transformer converters can work if the other conditions are met. Switch 371 selects the operating mode. In the first position, the contact 373 is set to operating voltage, the optocoupler 353 is in standby and can be switched on by the clock controller by means of a signal at connection 359 via the optocoupler 338 .

In the third position (two-stroke), the optocouplers 352 and 353 are deactivated. The transistor 320 can only be switched through by the clock controller (connection 358 ) via the optocoupler 339 .

In the fourth position (protective operation), the connection 344 and the line 221 are at the supply voltage; optocoupler 352 is conductive; transistor 320 is always conductive. The clock control is thus deactivated.

Each time switches 370 and 371 are switched , the voltage supply is interrupted, as a result of which the energy supply to transformer converters 185 and 186 is interrupted and transistor 320 is blocked. A restart cannot take place until the switch 370 connects one of the contacts 377 , 378 or 379 to the voltage source 277 . An external controller 381 'is connected to the connections 349 and 350 and to the three circuits 360 . Through the bridge 381 , the relay contact 354 of the third relay 351 is bridged. Via the connection 349 , the external control 381 'and the operating mode selector switch are connected to the voltage source 227 , so that the external control is also switched off when the operating mode selector switch is switched.

Fig. 23 shows the clock control. The centerpiece is the shift register 218 , which corresponds to the shift register 218 in FIG. 14. Its clock input CP is connected to connection 357 ( FIGS. 20 to 22) and receives a "shift clock" whenever the first transformer converter 185 begins to work. The first binary output Q 0 is connected to the connection 359 . Its second output Q 1 is connected to connection 358 and changes its state after two shift cycles. Its reset input R is connected to connection 337 . The shift register 218 is thus cleared by a signal at the connection 337 . The connections 357 , 337 , 359 and 358 are connected to the connections of the same name in FIGS. 20, 21 and 22.

The two inputs CP and R of the shift register 218 and the two outputs Q 0 and Q 1 are connected to the corresponding connections via inverting amplifiers 382 , 383 , 388 and 391 . A π circuit comprising a pull-down resistor 384 , a series resistor 385 and a capacitor 386 is connected between the input of the amplifier 382 and the connection 357 . The same circuit is also provided between the input of amplifier 383 and terminal 337 . Between the output of the amplifiers 388 and 391 and the connections 359 and 358 there is a series connection of a diode 389 and 392 and a resistor 390 and 393, respectively. Diodes 389 and 392 are light emitting diodes which signal the state of the clock control.

Finally, the terminal R of the shift register 218 is connected to the control units ( FIG. 12) via a further inverting amplifier 394, via which the "test" signal is supplied. The clock input CP is still connected to a positive supply voltage via a pull-up resistor 394 .

All in the claims, the description and the technical details shown in the drawing  can be used both individually and in any combination be essential to the invention with each other.  

Reference numerals

1 transmitter
2 transmitter diode 1
3 transmitter diode 2
4 transmitter diode n-1 (last)
5 rear derailleurs
6 ring shift registers
7 sliding space 1 transmitter
8 sliding space 2 transmitters
9 sliding space n-1 transmitter
10 sliding space n transmitter
11 return line
12 light pulses 1st diode
13 light pulses further diodes
14 Incoming line 1. Transmitter sliding area
15 recipients
16 photodetector 1
17 photodetector 2
18 photodetector n-1 (last)
19 Microcontroller channel 1
20 microcontroller channel 2
21 Reinforced channel 1
22 Reinforced channel 2
23 comparators (both channels)
24 cycle control
25 relay output
26 ring shift register receiving channel 1
27 ring shift register receiving channel 2
28 Sliding space 1 receiving channel 1
29 Sliding space 2 receiving channel 1
30 sliding space n-1 receiving channel 1
31 Sliding space n receiving channel 1
32 Sliding space 1 receiving channel 2
33 Sliding space 2 receiving channel 2
34 sliding space n-1 receiving channel 2
32 sliding space n receiving channel 2
36 Receive signal line channel 1
37 Receive signal line channel 2
38 Data line receiving channel 1
39 Data line receiving channel 2
40 return line
41 return line
42 Start and test switch channel 1
43 Start and test switch channel 2
44 Start and test signal line
45 Watchdog channel 1
46 Watchdog channel 2
47 Transmitter clock line
48 Enable line transmitter
49 IR power supply line transmitter
50 IR pulse line transmitter
51 Line 1st pulse
52 jumpers
53 Enable switch 1 transmitter
54 Enable switch 2 transmitters
55 Enable switch n-1 transmitter
56 Enable switch n transmitter
57 Transmitting diode switch 1
58 transmitter diode switch 2
59 transmitter diode switch n-1
60 jumpers
61 jumpers
62 line (last register stage output)
63 line (exit penultimate sliding area
64 line (register advance) transmitter
65 Line (register advance) transmitter
66 Line (register advance) transmitter
67 ground line
68 line (anodes)
69 resistance
70 resistance
71 capacitor
72 pull-down resistor
73 pull-down resistor
74 pull-down resistor
75 ground line
76 pull-up resistor
77 pull-up resistor
78 pull-up resistor
79 oscillator
80 counters
81 decoders
82 decoders
83 decoders
84 decoders
85 Line inv. Output 1. Sliding space 7
86 OR gate
87 AND gate
88 amplifiers
89 Controllable switch
90 counters
91 flip-flop
92 OR gates
93 NAND gates
94 detection circuit
95 AND gate 95 ′ quartz
96 driver 96 ' capacitor
97 capacitor
98 resistance
99 resistance
100 drivers
101 drivers
102 drivers
103 resistance
104 capacitor
105 resistance
106 capacitor
107 pull-down resistor
108 capacitor
109 Clock line channel 1 receiver
110 clock line channel 2 receiver
111 Enable switch 1 receiver channel 1
112 Enable switch 2 receiver channel 1
113 Enable switch n-1 receiver channel 1
114 Enable switch n Receiver channel 1
115 Enable switch 1 receiver channel 2
116 Enable switch 2 receiver channel 2
117 Enable switch n-1 receiver channel 2
118 Enable switch n Receiver channel 2
119 Enable switch n Receiver channel 1
120 Enable line receiver channel 2
121 analog switch 1
122 analog switch 2
123 analog switch n-1
124 Line (register advance) receiver
125 Line (register advance) receiver
126 Line (register advance) receiver
127 line (last register stage output) K
128 line (register advance) receiver
129 Line (register advance) receiver
130 line (register advance) receiver
131 line (last register stage output) K
132 Line Data Out channel 1
133 Head of Data Out Channel 2
134 Resistance channel 1
135 Resistance channel 1
136 Resistance channel 1
137 Jumper resistor channel 1
138 Resistance channel 2
139 Resistance channel 2
140 resistance channel 2
141 Jumper resistor channel 2
142 Power supply channel 1
142 Power supply channel 2
144 ground line
145
146 comparator
147 mono flop
148 counters
149 comparator
150 mono flop
151 counters
152 amplifiers
153 amplifiers
154 amplifiers
155 reset line
156 comparator
157 Start and test line
158 Dynamic Out line
159 drivers
160 Head of display service
161 drivers
162 Head of LG-II-State
163 drivers
164 line
165 LG-II-State line
166 Reset controller cable
167 line
168 oscillator
169 capacitor
170 resistance
171 resistance
172 resistance
173 resistance
174 resistance
175 resistance
176 resistance
177 pull-down resistor
178 resistance
179 transistor
180 resistance
181 resistance
182 resistance
183 resistance
184 resistance
185 Transformer converter channel 1
186 Transformer converter channel 2
187 Relay channel 1
188 Relay channel 2
189 relay contact R 2
190 relay contact R 1
191 relay contact R 1
192 relay contact R 2
193 Relay contact R 1
194 relay contact R 1
195 relay contact R 2
196 relay contact R 2
197 Rectifier channel 1
198 Rectifier channel 2
199 red II LED
200 green I LED
201 red I
202 green II LED
203 Service I LED
204 LG-I-State LED
205 Service II LED
206 LG-II-State LED
207 controllable switch channel 1
208 controllable switch channel 1
209 controllable switch channel 2
210 controllable switch channel 2
211 voltage source
212 buttons
213 Start and test switches
214 Impedance converter electrical isolation
215 OR gate
216 detection circuit
217 flip-flop
218 shift registers
219 OR gate
220 impedance converter galvanic isolation
221 line
222 connector
223 OR gate
224 Impedance converter galvanic isolation
225 line
226 connector
227 voltage source
228 line
229 Impedance converter electrical isolation
229 ′ LED
250 capacitor
251 transistor
252 primary winding
253 transformers
254 zener diode
255 capacitor
256 zener diode
257 resistance
258 resistance
259 diode
260 resistance
261 diode
262 pull-up resistor
263 resistance
264 resistance
265 zener diode
266 capacitor
267 resistance
268 diode
269 collector resistance
270 Schmitt triggers
271 drivers
272 drivers
273 light emitting diode
274 light emitting diode
275 resistance
276 resistance
277 capacitor
278 resistance
279 light emitting diode
280 zener diode
281 capacitor
282 collector resistance
283 drivers
284 drivers
285 286 drivers
287 diode
288 drivers
289 diode
290 capacitor
291 resistance
292 entrance
293 amplifier
294 amplifiers
295 controllable switch
296 controllable switch
297 control input
298 control input
299 coupling capacitor
300 resistance
301 resistance
302 resistance
303 resistance
304 resistance
305 resistance
307 resistance
308 Contactor control line
309 restart interlock
310 Command device line
311 Head of internal restart interlock
312 Operating mode line
313 Test to test control line
314 Optocoupler Dynamic Out I
315 Dynamic Out II optocoupler
316 controllable switch
317 controllable switch
318 controllable switch
319 controllable switch
320 controllable switch
321 controllable switch
322 OR gate
323 AND gate
324 controllable switch
325 make contact relay I
326 make contact relay II
327 controllable switch
328 controllable switch
329 break contact relay I
330 break contact relay II
331 control line to 318
332 control line to 319
333 timer
334 OR gate
335 control line to 334
336 Optocoupler remote start
337 Remote start line
338 1st cycle optocoupler
339 1st cycle optocoupler
340 cycle edge optocoupler
341 Power supply connection
342 Converter 1 connection
343 Converter 2 connection
344 Guard Only Mode connection
345 Cycle mode connection
346 Connection pull-up converter 1 and contact R
347 Relay 3 connection
348 Connection contact RS 3
349 Connection pull-up converter 2
350 Remote start connection
351 relay 3
352 Guard Only mode optocoupler
353 One Cycle Mode optocoupler
354 make contact RS 3
355 Optocoupler converter 1
356 Optocoupler converter 2
357 Cycle edge connection
358 2nd cycle connection
359 1st cycle connection
360 relay contacts
361 Bridge operating mode fixed
362 Bridge protection operation
363 Single-ended operation bridge
364 buttons
365 break contact
366 break contact
367 external relay
368 external relay
369 buttons
370 switches (operating mode)
371 switch (operating mode)
372 contact from 371
373 contact of 371
374 contact of 371
375 contact of 371
376 contact of 370
377 contact of 370
378 contact of 370
379 contact of 370
380 line
381 bridge
381 ′ external control
382 inverting amplifier
383 inverting amplifier
384 pull-down resistor
385 series resistance
386 capacitor
387 388 inverting amplifier
389 light emitting diode
390 resistance
391 inverting amplifier
392 light emitting diode
393 resistance
394 inverting amplifier
395 pull-up resistor

Claims (30)

1. Multi-beam through-beam sensor for contactless monitoring of a protective field with
a transmitter ( 1 ) which has a row arrangement of periodically and cyclically successively switched on infrared transmitter diodes ( 2 , 3 , 4 ) which emit modulated light,
a receiver ( 15 ), which has a corresponding row arrangement of periodically and cyclically activated photodiodes ( 16 , 17 , 18 ), each of which is assigned to one of the infrared transmitter diodes ( 2 , 3 , 4 ) and
with a multi-channel evaluation unit ( 19 , 20 ) in the receiver ( 15 ) which generates a "protective field not free" signal when at least one light beam from the transmitter ( 1 ) to the receiver ( 15 ) is interrupted,
characterized,
that the infrared transmitter diodes ( 2 , 3 , 4 ) emit pulse pauses modulated pulses ( 12 , 13 ) with an identifier,
that the identifier ( 12 ) of a selected infrared transmitter diode ( 2 ) is different from the identifier ( 13 ) of the other infrared transmitter diodes ( 3 , 4 ),
that the cyclic activation of the photodiodes ( 16 , 17 , 18 ) is clocked by a free-running oscillator ( 168 ), and
that the evaluation unit ( 19 , 20 ) synchronizes the cyclic activation of the photodiodes ( 16 , 17 , 18 ) of the receiver ( 15 ) due to the light pulses received by the selected infrared transmitter diode ( 2 ) with the transmitter ( 1 ). 2. One-way light barrier according to claim 1, characterized in that the identifier of the selected infrared transmitter diode ( 2 ) a first number of preferably four pulse / pause sequences ( 12 ) and the identifier of the other infrared transmitter diodes ( 3 , 4 ) one including different second number of preferably two pulse / pause sequences ( 13 ). 3. one-way light barrier according to claim 1 or 2, characterized in that in the transmitter ( 1 ) a ring slide gister ( 6 ) is provided, through which a single logical "1" is pushed cyclically, only the sliding space ( 7 , 8 , 9 ) , which leads the logical "1", activates the associated infrared transmitter diode ( 2 , 3 , 4 ). 4. one-way light barrier according to one of claims 1 to 3, characterized in that the receiver ( 15 ) has two mutually independent channels, each with a ring shift register ( 26 , 27 ), through which a single logical "1" is pushed cyclically, whereby A pair of sliding places ( 28 , 32 ; 29 , 33 ; 30 , 34 ) of the two ring shift registers ( 26 , 27 ) is assigned a photodiode ( 16 , 17 , 18 ) and the photo detector activated by a sliding place ( 28-34 ) outputs a signal corresponding to the light pulses received by it to a bus ( 36 , 37 ) of the individual channels. 5. one-way light barrier according to claim 4, characterized in that for each receiving channel an independent microcontroller ( 19 , 20 ) is provided, each of which generates clock pulses for the two ring shift registers ( 26 , 27 ), with the first switching space ( 28 , 32 ) the ring shift register ( 26 , 27 ) is activated and further clock signals for advancing the ring shift register ( 26 , 27 ) are only generated when the first photodetector ( 16 ) has received the identifier ( 12 ) of the selected infrared transmitter diode ( 2 ), whereby the synchronization between transmitter and receiver is established. 6. one-way light barrier according to claims 3, 4 or 5, characterized in that the Ringschieberegi ster ( 6 ; 26 , 27 ) have at least one sliding space ( 10 ; 31 , 35 ) more than infrared transmit diodes or photodiodes are present. 7. one-way light barrier according to one of claims 3 to 6, characterized in that the Ringschieberegi ster ( 6 , 26 , 27 ) from D flip-flops ( 7; 10 ; 28-31 ; 32-35 ) are constructed, the data input each flip-flop is connected to the output of the previous flip-flop and the data input of the first flip-flop is connected to the output of the last flip-flop. 8. one-way light barrier according to one of claims 2, 3, 6 or 7, characterized in that in the transmitter ( 1 ) a switching mechanism ( 5 ) is provided, which upon activation of the selected transmission diode ( 2 ) associated sliding space ( 7 ) of the ring slide rule sters ( 6 ) generates a first number of pulses ( 12 ) and generates a second number of pulses ( 13 ) upon actuation of all further sliding places ( 3 , 4 ) of the ring shift register ( 6 ). 9. one-way light barrier according to claim 8, characterized in that the switching mechanism ( 5 ) has a free-running oscillator ( 79 ) with a downstream binary counter ( 80 ),
that selected outputs of the binary counter ( 80 ) are connected to decoders ( 81 , 82 , 83 , 84 ) whose outputs produce phase-shifted pulses (I 81 , I 82 , I 83 , I 84 ), one of these pulses (I 81 ) is only generated if the first shift location ( 7 ) of the ring shift register ( 6 ) has a logical "1",
that the pulses (I 81- I 84 ) generated by the decoders ( 81-84 ) are supplied via a common line ( 50 ) to all transmitting diodes ( 2-4 ) and
that another pulse (I 84 ) of one of the decoders ( 84 ) blocks the outputs of all sliding locations except for the first sliding location of the ring shift register ( 6 ), so that the last-mentioned pulse (I 84 ) only excites the selected first infrared transmitter diode ( 2 ) is effective. 10. one-way light barrier according to claim 9, characterized in that in the switching mechanism ( 5 ) there is a first detection circuit ( 94 ) which generates a pulse (I 94 , I 93 ) when the power supply is switched on, by means of which a logic "1" in the the first shift location ( 7 ) of the ring shift register ( 6 ) is registered. 11. One-way light barrier according to claim 10, characterized in that the pulse (I 93 ) generated when the power supply is switched on is delayed, preferably by a counter ( 90 ), to the first sliding place ( 7 ). 12. One-way light barrier according to claim 11, characterized in that the counter ( 90 ) after a predetermined number of counted clock pulses (z. B. 128 pulses) writes a logical "1" in the first sliding space ( 7 ), unless previously by the last sliding place ( 10 ) of the ring slide register ( 6 ) a logical "1" in the first sliding place ( 7 ) was registered. 13. One-way light barrier according to one of claims 1, 4 to 7, characterized in that each photodiode ( 16-18 ) of the receiver ( 15 ) via a two-channel analog switch ( 121 , 122 , 123 ) each with a sliding space ( 111-113 ; 115-117 ) with the collecting lines ( 36 , 37 ) of the two channels and that the analog switches ( 121-123 ) are each formed as separate components. 14. One-way light barrier according to claim 13, characterized in that the microprocessors ( 19 , 20 ) during a test phase (signal on line 120 ) inactivate the outputs of all sliding positions of the ring slide gister ( 26 and 27 ) for checking the analog switch ( 121 -123 ) for errors. 15. One-way light barrier according to claim 14, characterized in that each analog switch ( 121-123 ) is capacitively ( 299 ) coupled to the output of the associated photodiode ( 16-18 ), and two separate amplifiers ( 293 , 294 ) and two separate Switching transistors ( 295 , 296 ), wherein the control inputs ( 297 , 298 ) of the two transistors ( 295 , 296 ) are each connected to an output of the associated shift location of the two ring shift registers, that the outputs of the two amplifiers ( 293 , 294 ) each with one of the transistors ( 295 , 296 ) are connected and that the other connections of the switching path of the transistors ( 295 , 296 ) are each connected to one of the two bus lines ( 36 , 37 ). 16. One-way light barrier according to claim 15, characterized in that the two amplifiers ( 293 , 294 ) are supplied from one of two mutually independent voltage sources. 17. one-way light barrier according to one of claims 4 to 7 and 13 to 17, characterized in that the collecting lines ( 36 , 37 ) of each channel are each connected to two comparators ( 146 , 149 ) which are set to different threshold values, and that Outputs of the comparators ( 146 , 149 ) are fed to the respective microcontroller ( 19 , 20 ) of the respective channel, which output a "contamination signal" depending on whether both or only one of the comparators generate a signal. 18. One-way light barrier according to one of claims 4 to 7 and 13 to 17, characterized in that both microprocessors ( 19 , 20 ) before outputting a signal signaling a free protective field (line 158 , 158 ') mutually via control signals (lines 162 , 165 ) Assure whether the other microcontroller has also reached the same evaluation result when evaluating the received light pulses. 19. One-way light barrier according to one of claims 4 to 7 and 13 to 18, characterized in that the light pulses on one of the busbars ( 36 , 37 ) optionally via a comparator ( 146 , 149 ), a non-retriggerable monostable flip-flop ( 147 , 150 ) are supplied so that the output signals of the monostable flip-flop ( 147 , 150 ) are fed to the counter input of a fast-working binary counter ( 148 , 151 ) and that the binary outputs of the counter ( 148 , 151 ) with inputs of the microcontroller ( 19 , 20 ) are connected, the Mikrocon troller ( 19 , 20 ) working slower than the counter ( 148 , 151 ). 20. One-way light barrier according to one of claims 4 to 7 and 13 to 19, characterized in that the microcontroller ( 19 , 20 ) of both channels with perfect operation and undisturbed protective field, a dynamic output signal (line 158 , 158 ') with a predetermined clock frequency to one Output common fail-safe comparator ( 23 ), which compares whether both microprocessors generate the dynamic output signal at the same time. 21. One-way light barrier according to claim 20, characterized in that the comparator ( 23 ) is designed in relay contact technology. 22. One-way light barrier according to claim 21, characterized in that each channel is assigned a relay ( 187 , 188 ), each having a normally closed contact ( 189 , 190 ) and a normally open contact ( 191 , 192 ), the normally closed contacts of the two relays ( 187 , 188 ) are each arranged in an evaluation circuit for the dynamic output signal of the other channel, while the working contacts of the relays are each arranged in an evaluation circuit for the dynamic output signal of the own channel. 23. One-way light barrier according to claim 21 or 22, characterized in that the dynamic output signals of both channels (lines 158 , 158 ') are each fed to a transformer converter ( 185 , 186 ), that the transformer converter ( 185 , 186 ) the assigned Relay ( 187 , 188 ) excite, each transformer converter ( 185 , 186 ) can only respond due to the relay contacts ( 189-192 ) if the other transformer converter has not yet responded, so that both transformer converters only simultaneously can address. 24. One-way light barrier according to one of claims 21 to 23, characterized in that both relays ( 187 , 188 ) have additional contacts ( 193-196 ) as switching elements of the one-way light barrier and that all contacts of the two relays are each positively driven. 25. One-way light barrier according to one of claims 4 to 7 and 13 to 24, characterized in that the microcontrollers ( 19 , 20 ) of each channel first perform a self-test after switching on the power supply, reset both ring shift registers ( 26 , 27 ), then the first Activate the receive diode and query whether the identifier of the first beam has been received, then only activate the next receiver diode after receipt of the identifier of the first beam and query the received identifier; if the light is received, activate the next receive diode and query its light reception Until all the receiving diodes have reported correct light reception, whereupon a switching command "protective field free" is generated and the cycle is repeated with activation of the first receiving diode and that if the light reception is incorrect, one of the receiving diodes generates a switching command "protective field not free". 26. One-way light barrier according to one of claims 21 to 25, characterized in that contacts ( 365 , 366 ) additional external, controlled by the light barrier relay ( 367 , 368 ) are looped into the monitoring circuit of the two channels. 27. One-way light barrier according to one of claims 1 to 26, characterized in that a restart lock ( 351 , 333 , 354 ) is provided which prevents an automatic restart of the downstream machine after an interruption of the protective field or after an error-caused switching off of the light barrier . 28. One-way light barrier according to one of claims 22, 23 or 24, characterized in that one connection of each of the two relays ( 187 , 188 ) is connected to a pole of the energy supply via a common controllable switch ( 320 ). 29. One-way light barrier according to claim 28, characterized in that the switch ( 320 ) in dependence on set or not set Schaltbrük ken ( 362 , 363 ) or the switching position of a mode selector switch ( 370 , 371 ) and in dependence on signals of a clock control ( 218 ) is closed or open. 30. through-beam sensor according to claim 29, characterized in that the mode selector switch ( 370 , 371 ) is a multi-pole, positively driven switch with interrupting, non-overlapping Schaltkon clocks.