DE3927343A1 - PROGRAMMABLE FUZZYLOGIKSCHALTUNG - Google Patents

Abstract

A fuzzy logic circuit for operating a fuzzy logic with "fuzziness" taken into account has an operation section memory unit 13 in which the result of operation to be outputted in response to an input is stored in an address specified by the input, the result of operation being rewritable, whereby the change in the contents of a fuzzy logic operation to be performed can be handled merely by rewriting the contents of the operation section memory unit. <IMAGE>

Description

Background of the Invention

The invention relates to an operating circuit for fuzzy logic.

Fuzzy logic is a logic with which so-called "fuzziness" is edited, which is based on the conception of the fuzzy sets L. A. Zadeh based in 1965.

Human characteristics and behavior are generally only definable with a certain blur (fuzzy). Therefore a machine with fuzzy characteristics similar to humans ("Fuzziness") not complete with conventional control technology operate such a characteristic ("fuzziness") does not do it justice.

However, if there is a way, this characteristic To express (fuzziness) logically or quantitatively through the fuzzy logic, can be expressed through experience or observational values  Characteristics or behavior of people through automatic facilities are taken into account. Comprehensive Research has been carried out on this.

First of all, the difference between a conventional amount (sharply defined amount (crisp set), see FIG. 4) and the fuzzy amount will be described with reference to FIGS . 4 and 5.

Fig. 4 shows an example of the characteristic function of the conventional, crisp set.

In the case of this set (crisp set) is a boundary line or a Threshold is provided and it is determined whether given data are greater or less than the threshold to determine whether the data belongs to a certain amount. So the case with the given data in the threshold value, not taken into account will. The characteristic function can only Accept values "1" (belonging) or "0" (not belonging).

Fig. 4 shows the characteristic function for data or elements "height". People taller than 170 cm belong to the group "taller people". The function value "1" means that the data information belongs to the set "larger persons"; the function value "0" means that the data information does not belong to the set "larger persons".

The characteristic function of the fuzzy set is called "membership or membership function.  

Fig. 5 shows an example of a membership function of the fuzzy set.

In the membership function, the function value doesn't just take the values "1" and "0", but also intermediate values, for Example 0.8. The function value "1" means that the data information 100% belongs to the crowd; the function value "0.8" means that the data information is 80% to the amount and 20% not is part of it. The function value "0" means that the 0% data information belongs to the set (completely not belongs to it).

As in FIG. 4, the element in FIG. 5 is "body size". In this membership function, the function value 0.2 is intended for a height of 165 cm; a person who is 165 cm tall is 20% of the "taller" crowd.

On the other hand, a function value of "0.8" is for one person provided that is 170 cm tall. That means that the person 170 cm tall, 80% of the crowd "taller people" belongs.

Research in the field of fuzzy logic can mostly be found on Use software systems with digital computers. However, it is necessary an exclusive hardware system for fuzzy logic operations use to speed up complex systems to edit.

The hardware system can consist of digital or analog circuits  be constructed. In view of the current ones The hardware system is preferably a digital computer with digital circuits realized.

If a fuzzy logic operation using a digital circuit is carried out, several function values between the Function values "1" and "0" provided; the membership function is approximated by using a step-shaped curve (according to the discrete values of the membership function) and a digital operation is performed for each of the function values or Level performed. In practice, the processing is done with value-added data instead of binary data. Through the The approximation accuracy increases the number of function values and also the accuracy of the fuzzy logic operation elevated.

Figure 6 shows an example where the membership function of the fuzzy set is approximated by a plurality of levels. In the case shown in Fig. 6, the number of levels is eight (0 to 7). In Fig. 6, reference numeral a denotes the membership function, b the step-shaped approximation curve and E 0 to E 10 the values of the elements.

The membership function is approximated by curve b . For example, if the element is "E 7", the associated level is "6" (the corresponding functional value of the membership function is 6/7).

An operation is performed by an exclusive digital circuit. Therefore, a digital circuit is provided which outputs a level "5" when an element value E 6 is input. In a corresponding manner, a digital circuit is provided which outputs a level "4" when an element value E 5 is input.

By integrating the above operations, the approximation the membership function with the digital circuits carried out.

Reference documents for the above fuzzy set and the Membership roles include the Japanese Patent application (OPI) 95 673/1987 ("OPI" means unchecked published application) and the publication of M. Togai and H. Watanabe "A VLSI IMPLEMENTATION OF FUZZY INFERENCE ENGINE: TOWARD AN EXPERT ON A CHIP ", PROC. Of the 2nd Conf. On Art. Int. Appli., Pp. 192-197, Miami Beach, 1985.

The above fuzzy logic operation, in which the membership function through a variety of levels or levels is approximated and being a digital circuit exclusively Difficulties used for each operation are as follows or disadvantages on:

A first difficulty is that with an increase the number of levels or levels the accuracy of the approximation is increased, but the increase in the number of fuzzy logic operations to a corresponding increase in the number which performs exclusive arithmetic circuits.  

A second difficulty is that in hardware design of the exclusive arithmetic circuits the contents of the Operations can no longer be changed.

The first difficulty will now be described in detail.

FIGS. 7 (a) to 7 (d) are tables for the cases in which two levels are provided for input and 16 operators (or surgical techniques) with 2 inputs and 1 output are present.

Fig. 7 (a) shows an arithmetic circuit arrangement, wherein reference numeral 70 denotes a first input signal line, 71 a second input signal line, 72 the arithmetic circuit and 73 the output signal line. Two levels, ie "0" and "1", are provided for one input.

An oblique line above the input signal line 70 and a reference symbol "1" mean that a 1-bit signal is supplied via the signal line. This applies to the other signal lines in FIG. 7 and to the signal lines in the other figures.

Fig. 7 (d) shows the combination of the inputs and outputs of the arithmetic circuit. The number of combinations of first and second inputs is 4 because each input can have two levels (0 and 1). For the 4 combinations, 16 output combinations Nos. 1 to 16 are provided as shown in Fig. 7 (d).

Fig. 7 (b) and 7 (c) the relationship between input and output values show in the output combinations no. 6 and no. 12,.

For example, Fig. 7 (b) shows the following relationship: When the first input value on the first input signal line 70 is "0" and the second input value on the second input signal line 71 is "1", the output signal line 73 outputs the output value "1".

That is, the arithmetic circuit for performing the Operation No. 6 is designed in such a way that it works as before described works.

As can be seen from the above, there are two input levels 16 operators with two inputs and one output intended. To perform any surgery are essential 16 exclusive logic circuits required.

Generally speaking, with n input levels, n ^{n ²} operators with 2 inputs and one output are provided. For example, if n = 3, there are 19,683 operators with two inputs and one output. So 19 683 operators are to be provided. For a fuzzy logic operation in which the number of levels is very large (infinite), an extremely large number of exclusive logic circuits is required.

The second difficulty will now be described in detail. It have been doing extensive research on fuzzy logic and there is a high probability that a significant number of useful fuzzy logic operations is developed and applied. This creates a demand  for fuzzy logic circuits that are so flexible that the content of the operation changed quickly and easily can be. However, the demand for the above not satisfy the exclusive arithmetic circuits described, which, if they are made of hardware, the content of the operations cannot change.

Summary of the invention

The invention has for its object the above Difficulties associated with conventional Eliminate fuzzy logic operations.

These and other objects of the invention are accomplished by a programmable fuzzy logic circuit that according to the invention consists of the following components: an operation section storage unit (operation section memory unit), in which the operation result, which is output depending on an input value, under an address that is saved by the input value is specified, the operation result being overwritable is.

Thus, with the fuzzy logic circuit according to the invention Contents of a fuzzy logic operation can be changed without an exclusive arithmetic circuit must also be provided.

In the operation section storage unit, the operation result, that results in response to an input value, stored under the address specified by the input becomes. Therefore, the operation result of the fuzzy logic operation  by simply reading the data information stored under the address be preserved.

The result of the operation can be overwritten. The overwriting allows another fuzzy logic operation to be performed. According to the invention, a programmable fuzzy logic circuit created in which the surgical result is successive is overwritten according to the program.

The characteristic, the principle and the applications of the invention are derived from the following detailed description and the Claims in connection with the drawings clearly, wherein Identical components denoted by identical reference symbols will.

Brief description of the drawings

It shows

Figure 1 is a block diagram of the basic arrangement of an essential part of the programmable fuzzy logic circuit according to the invention.

Fig. 2 is a block diagram showing the arrangement of an embodiment of the programmable fuzzy logic circuit according to the invention;

. Fig. 3 (a) and 3 (b) the functions of the output bits of A 6 and A 7 of a counter shown in Figure 2;

FIG. 4 shows an embodiment of a characteristic function of a conventional clear-cut amount (crisp set);

FIG. 5 shows an embodiment of a membership function of a fuzzy set;

Fig. 6 shows an embodiment of an approximation of the fuzzy set by applying a plurality of stages or levels (level);

Fig. 7 (a) to 7 (d) show a circuit or tables for the case where an input having two levels is applied and 16 operators with 2 inputs and 1 output are present;

Fig. 8 is an input / output table for an operator with 2 inputs and 1 output for the case of 8 input levels;

Fig. 9 is a block diagram of a conventional fuzzy interference system;

FIG. 10 is a block diagram of a fuzzy interference system to which the technical concept of the invention is applied;

Fig. 11 is a block diagram with reference to which the principle is to design a fuzzy interference system programmable explained.

Detailed description of the invention

Preferred embodiments of the invention are based on the Described drawings.

Fig. 1 shows a block diagram of the basic arrangement of an essential part of the programmable fuzzy logic circuit according to the invention.

In Fig. 1, reference numeral 10 denotes a programming address signal line, 11 an input signal line, 12 an input selection circuit, 13 a memory section for an operation section, 14 and 15 two-way buffers, 16 a programming data signal line and 17 an output signal line.

The reference symbol "m" , which is arranged along the signal lines in the figure, means that the signal lines m -bit are formed in parallel. The value m depends on the maximum value N (7 in FIG. 6) of the levels which share the membership function, that is to say that m is selected such that N = 2 ^m − 1.

The input selection circuit 12 selects one of the input signals that are supplied via the programming address signal line 10 and the input signal line 11 and sends this signal to the memory unit 13 . The input selection circuit 12 comprises, for example, a multiplexer.

The operation section memory unit 13 is designed such that an operation output signal is output in accordance with a so-called look-up table system. An m- bit signal is supplied to the storage unit 13 and is used as data information for specifying an address in the storage unit 13 . The operation result to be output in response to the input signal is previously written into the address. Therefore, when the address is specified by the input signal, the operation result is read from the address to output the target operation output signal.

The operation result is written into the memory unit 13 as follows:

In this case, the input selection circuit 12 selects the input signal that was supplied via the programming address signal line 10 and supplies it to the memory unit 13 . The input signal thus supplied specifies an address in the storage unit 13 . The data information (or the operation result) to be written in the address thus specified is supplied via the programming data signal line 16 . Therefore, in this operation, the two-way buffer 14 is controlled so that the data is transferred to the storage unit 13 . Thus, the data information supplied via the programming data signal line 16 is stored at the address specified by the signal supplied via the programming address signal line 10 .

The operation controlled in this way in connection with the storage unit 13 is carried out as follows:

In this operation, the input selection circuit 12 selects the input signal that is supplied via the input signal line 11 . The branch path buffer 14 is deactivated while the two-way buffer 15 is controlled so that the signal is transferred from the memory unit 13 to the output signal line 17 .

The input signal supplied through the input signal line 11 is used as an address signal specifying an address in the storage unit 13 . As a result, the data information (or the operation result) that has been stored at the address thus specified is supplied to the output signal line 17 through the two-way buffer 15 . In this way, the operation result is created (read out).

The logic circuit shown in Fig. 1 is a 1-input / 1-output circuit. However, it can be expanded to a 2-input / 1-output circuit by adding another input signal line similar to the input signal line 11 and by using a 2 m- bit parallel programming address signal line instead of the programming address signal line 10 .

In Fig. 1, the two-way buffers 14 and 15 and the input selection circuit 12 can be eliminated.

Fig. 2 shows an embodiment of a programmable fuzzy logic circuit according to the invention. In FIG. 2, the circuit elements that were previously described with reference to FIG. 1 are denoted by the same reference numerals or terms. In FIG. 2, reference numeral 18 designates a counter, 19 a storage unit which supplies operation results (logic operation result supplying memory unit; hereinafter referred to as "a second storage unit 19 " as far as applicable) and 20 the essential circuit part which corresponds to that in FIG. 1 corresponds to the circuit part shown.

Is at the position shown in Fig. 2 circuit arrangement of a 6-bit parallel signal for specifying the address in the operation section storage unit 13 is used (hereinafter referred to as "a first storage unit 13" hereinafter as applicable). The number of specifiable addresses is 2⁶ = 64.

A 2-input system is used. The input line 11 consists of a first input line 11-1 and a second input line 11-2 . The two input values specify an address in the first memory unit 13 and therefore each input signal line supplies a 3-bit parallel signal.

The second storage unit 19 supplies a large number of data quantities, including operation results, which are to be written into the first storage unit 13 . When there is a requirement to change the contents of the fuzzy logic operation, the second storage unit 19 supplies the first storage unit 13 with one of the plurality of data sets including the operation result corresponding to the respective operation.

The counter 18 generates an address signal in order to write the operation result into the first storage unit 13 . The address signal thus generated is supplied to the first storage unit 13 through the input selection circuit 12 to specify an address at which the data information is to be written, and is supplied to the second storage unit 19 to communicate the address at which the data information to be written is stored .

An address with 6 bits can be specified in the first memory unit 13 ; while the counter outputs an 8-bit signal (A 7- A 0), which is two bits more.

The two higher value bits, i.e. the output signal from the two additional bits (A 7, A 6) (or a control signal) is fed to the second storage unit 19 only in order to divide the operation results into groups or sets, as shown in FIG. 3.

Fig. 3 (a) and 3 (b) are diagrams describing the functions of the counter output bits A 6 and A 7. Figure 3 (a) shows that there are four combinations (a, b, c and d) of the two higher bits.

64 addresses can be specified with the least significant bits, which means that an address signal exists on the 6 remaining bits (A 5 to A 0). Therefore, the control signal consisting of the two higher-value bits divides the address area into four areas a, b, c and d , each having 64 addresses, as shown in Fig. 3 (b).

The second storage unit 19 thus selects the contents in the area a, b, c and d , so that the contents selected in this way are written into the first storage unit. The contents of the operation can thus be changed according to the program.

The second memory unit 19 has outputs D 0 to D 2; the corresponding output signals are 3-bit parallel.

The number of input levels is 2³ = 8, because the first and second input signal lines 11-1 and 11-2 are 3-bit parallel. This corresponds to the case shown in FIG. 6, in which the membership function of the fuzzy set 8 has levels 0 to 7.

On the other hand, the output of the first memory unit 13 is designed to be 3-bit parallel, so that 8 output values 0 to 7 are provided. In such a case, the ratio of inputs and outputs of the fuzzy logic circuit is configured, for example, as follows:

Fig. 8 shows an embodiment of a 2-input / 1-output-operator table, said input level 8 are provided.

In FIG. 8, each output value of the first memory unit 13 is provided at the intersection of the level of the first input value and the level of the second input value. For example, if the level of the first input and the second input is "4" and "6", respectively, the output value is "4". The input / output board concerns the logic circuit, which is also referred to as the "minimum circuit", which outputs the smaller of the two input values and is only one of an extraordinarily large number of (n ^{n ²} , with n = 8) input and output boards which is to be considered as described above.

The operation section storage unit 13 and the logic operation result supply storage unit 19 may be RAM memories (random access memories), EPROM memories (erasable by ultraviolet rays / programmable read-only memories), E²PROM memories (electrically erasable / programmable read-only memories) or flip-flops. If necessary, ROM memory (read-only memory) can also be used. Alternatively, the unit 19 can be eliminated, the programming instead being carried out directly by a digital computer.

In the embodiment described above, the logic circuit is performing fuzzy logic operations from stores and the result of the operation is based on a table search system formed with the consequence that the logic operation by its nature can be changed freely, that is, the logic operation is programmable.

The membership function is saved in the memory. On the other hand, the essential part is in a fuzzy interference system a membership functional section and a fuzzy logic section. Therefore, the essential part of the system in its Entirely made up of memories. It means that both the membership function section and the fuzzy logic operation section can be trained programmably.

Fig. 9 shows an embodiment of a conventional fuzzy interference system. In Fig. 9, reference numerals 81 to 84 denote input signal lines, 85 to 88 membership function memory units, 89 to 90 fuzzy logic circuits, 91 and 92 counters, 93 and 94 membership function memories, 95 and 96 fuzzy logic circuits, and 97 and 98 output signal lines.

The fuzzy interference system has 4 input signal lines 81 to 84 and two output signal lines 97 and 98 . A fuzzy production rule is thus carried out in the system with four inputs and two outputs.

The fuzzy logic circuits 89, 90, 95 and 96 consist of exclusive logic circuits.

The fuzzy interference system constructed in this way works in in the following way:

A signal corresponding to the element in FIG. 6 is supplied via the input signal line 81 to the membership function storage unit 85 , in which a predetermined membership function is stored. The storage unit 85 supplies an output signal corresponding to the input signal. The remaining membership function storage units 86 to 88 operate in the same manner as the membership function unit 85 .

Fuzzy logic circuits 89 and 90 are configured to perform predetermined fuzzy AND (AND) operations. Each of the fuzzy logic circuits 89 and 90 receives four input values from the membership function storage units 85 to 88 and outputs an output value.

The fuzzy interference system includes a so-called "condition section" (or earlier condition section) and a so-called "result section" (or later condition section). The condition section extends from the input signal lines 81 to 84 to the fuzzy logic circuits 89 and 90 , while the result section comprises the remaining components.

The output signals of the condition section are fed to the fuzzy logic circuits 95 and 96 in the result section where predetermined fuzzy AND operations are performed. The output signals of the membership function storage units 93 and 94 are also supplied to the fuzzy logic circuits 95 and 96, respectively.

The output signals of the counters 91 and 92 are supplied to the membership function storage units 93 and 94, respectively. In particular, each counter generates signals corresponding to the elements of the membership function stored in the respective membership function storage unit in increasing order (or decreasing order) of the elements. Depending on the signals generated in this way, the corresponding membership function values are output successively.

In the fuzzy logic circuits 95 and 96 , the output signals of the condition section and the membership function values which are successively output from the membership function storage units 93 and 94 are subjected to a fuzzy AND operation. The output signals of the fuzzy logic circuits 95 and 96 are fed to their output signal lines 97 and 98, respectively.

An embodiment of a fuzzy interference system to which the technical concept of the invention is applied is shown in FIG. 10, wherein those circuit elements which have already been described with reference to FIG. 9 are designated by the same reference symbols. In Fig. 10, reference numerals 89-1, 90-1, 95-1 and 96-1 denote operation section storage units ; B denotes a condition section and C the fuzzy interference system.

As is 9 and 10, is clear from a comparison of FIGS., The fuzzy interference system according to the invention from the conventional fuzzy interference system differs in that the fuzzy logic circuits 89, 90, 95 and 96 through the operation section memory units 89-1, 90-1, 95- 1 and 96-1 are replaced.

The method of making each fuzzy logic circuit programmable by replacing it with an operation section storage unit has already been described. In this application, the circuit elements that form the fuzzy interference system are divided into a few groups, and the groups are designed programmably according to the method described with reference to FIGS . 1 and 2.

For example, the condition section B , which is framed by a dashed line (in FIG. 10), or the fuzzy interference system C , which is framed by the dot-dash line, can be designed to be programmable. Of course it is possible to design only the result section (the part remaining in the fuzzy interference system C in addition to the condition section B ).

When fuzzy interference is used in practice, several units of ten fuzzy interference systems C are generally connected in parallel. These fuzzy interference systems C connected in this way can be designed as a whole to be programmable.

Fig. 11 shows the basic principle to design a fuzzy interference system programmable. In Fig. 11, reference numeral 100 denotes a programming address signal line, 101 and 102 input signal lines, 103 an input selection circuit, 104 a memory section, 105 and 106 two-way buffers, 107 a programming data signal line and 108 an output signal line. Fig. 11 corresponds to the arrangement 1 of FIG..

When condition section B is made programmable, storage section 104 includes membership function storage units 85 through 88 and operation section storage units 89-1 and 90-1 . When the fuzzy interference system as a whole is made programmable, membership function storage units 93 and 94 and operation section storage units 95-1 and 96-1 are additionally included.

By presetting these circuit elements, the input selection circuit 103 selects the programming address signal line 100 . The signal output from the programming address signal line 100 must specify the address in the membership function storage unit 85, 86, 87 or 88 or in the operation section storage units 89-1 or 90-1 .

The data information supplied from the programming data signal line 107 through the two-way buffer 105 is stored at the address thus specified by the signal output from the programming address signal line 100 . The programming data signal line 107 is used to supply data signals to the membership function storage unit 85 etc. or the operation section storage unit 89-1 etc.

When performing a fuzzy logic operation, the input selection circuit 103 selects the input signal lines 101 and 102 . In the case shown in Fig. 11, two inputs are provided; however, it is emphasized that the number of inputs is not limited to only 2. With the input signal as the address, the output signal of the membership function storage unit is output. Similarly, the operation result corresponding to the table search system is read out in the operation section storage unit with the input signal as the address.

The output signals thus obtained are fed through the two-way buffer 106 to the output signal line 108 .

As can be seen from the above description, the Invention has the following effects and advantages:

• 1. In order to approximate a fuzzy logic operation with a digital circuit with sufficient accuracy, several levels are used; however, according to the invention, in one embodiment, the number of operation section units can be 1.
  As described in connection with conventional systems, the accuracy of the approximation can be improved by increasing the number of stages or levels; however, it turns out that the number of types of fuzzy logic operations is increased in that and in accordance with the increase in the number of exclusive arithmetic circuits.
  On the other hand, according to the invention, the contents of a fuzzy logic operation to be carried out can be changed simply by rewriting the contents of the data in the operation section storage unit.
• 2. Problems of fuzzy logic have been researched intensively, and it is very likely that now fuzzy logic operations be applied that have not been used previously. Such fuzzy logic operations can easily be performed by the contents of the operation section storage unit be overwritten.
• 3. The essential parts of the fuzzy interference system can are formed from memory and programmable according to the invention be designed.

The invention has been achieved on the basis of a preferred embodiment described. However, those skilled in the art will recognize that numerous Changes and modifications can be made without that abandon inventive principle by the following Claims under protection including changes and Modifications should be made.

Claims (5)

1. Programmable fuzzy logic circuit, characterized in that it has an operation section storage means in which an operation result to be output in response to an input signal is stored at an address which has been specified by this input signal and that the operation result can be overwritten. 2. Programmable fuzzy logic circuit according to claim 1, characterized characterized as further operating result delivery means which, in connection with the overwriting of the Operation result selectively a data set from a Variety of data sets including surgery results feeds the operation section storage means. 3. Programmable fuzzy logic circuit according to claim 2, characterized characterized in that the operation result supply means is an operation result supply storage unit which Variety of data sets including surgery results stores a large amount of data in response  selects a control signal and selects it Outputs operation results according to a specified address. 4. Programmable fuzzy logic circuit according to claim 3, characterized characterized in that it further comprises a signal generating means, which is an address signal for specifying an address in the operation section storage means and an address in the operation result feed storage unit as well as that Control signal generated that the operation result supply storage unit is fed. 5. Programmable fuzzy circuit according to claim 4, characterized characterized in that the signal generating means by a Counter is formed.