DE3907843A1 - HARDWARE-ESTABLISHED, CONTROLLED EXPERT SYSTEM - Google Patents

Abstract

A hardware-implemented rule-based expert system 11 (REX) includes a working memory 12 in which, at the beginning of an inferencing operation, is stored known information or facts pertaining to the application domain; and a memory 13 for storing a rule set 15 comprised of a series of instructions, each defining a condition or an action. Means is provided for loading from the rule memory into working memory successive instructions of the rule set, and a logic means 12 is provided for successively executing the instructions in working memory with reference to the stored facts to thereby deduce new facts. As new facts are deduced, they are stored in working memory and may be used during the execution of subsequent instructions of the rule set to derive additional facts. Upon the completion of the inferencing operation, the facts stored in working memory are transferred, 14, to an output device. <IMAGE>

Description

The invention relates to an executed in hardware, rule based expert system and in particular relates to a in Hardware executed or hard-wired, rule-based Expert system, the high-speed conclusions in An applications with artificial intelligence.

Expert systems are a specific type of computer program containing artificial intelligence (AI) technology to address problems whose solution is usually require human experts or specialists. In one rule - based expert system will be knowledgeable in a very specific application in the form of a series of rules or regulations, d. H. so-called "production In the operation of a typical expert system provides the user with a conventional Be user interface the expert system with certain known Information about a particular problem, and the Ex pertensystem utilizes the production rules with regard to of this known information to deduce facts and to solve problems that affect the scope. For more background information, which expert systems Reference is made to the following articles: Robert H. Michaelsen, et al., Stn. 308-312; Beverly A. Thompson, et al., "Inside an Expert System," Byte Magazine, April 1985 Stn. 315-330; Michael F. Deering, "Architectures for AI", Byte Magazine, April 1985, Stn. 193-206.

Successful expert systems are for a number of times been developed, for example for Performing medical diagnoses, identifying organic compounds for selecting oil wells  Muds, etc. In addition, a number are range-independent pending expert skeletons developed in software form to form a rule-based expert system for specific applications. meh Other commercially available expert system tools or instructions ments described in the above-mentioned articles. Usually these expert systems and tools or Instruments designed in the form of software programs that go through a general purpose computer or microcomputer. with The software program will have a dialogue session between the user and the expert system brought about, the Expert system asks the user questions and his property knowledge used to solve the problems and the Be give users advice.

There is a great interest in the use of Expert systems to other practical applications to expand, and in particular to develop expert systems, wel can be used in real-time applications. Such Systems would be used, for example, as control systems for ver various applications, such as manufacturing or manufacturing Procedures, process control, steering or guidance systems, robots control, etc. be useful. A limitation in the Ent Development of complicated real-time systems with artificial ones Intelligence, however, represents the computing speed. Um artificial intelligence technology is effective in practice Therefore, the computational power and gene must be used speed are increased.

Considerable efforts have already been made to speed up the processing of artificial Improve intelligence by using the software tools or Agents used in the processing of artificial intelligence used, such as the artificial ones Languages, improve and streamline. He is too been known that performance improvements by custom Hardware can be achieved, especially for  a processing of artificial intelligence designed wor that is. As in the above mentioned article of Deering has suggested a solution Hardware architecture refinements in the Processor command set affected so that the processor can work faster. Special attention is also the Development of parallel processing architectures ge which would allow it, the artificial ones Perform intelligence calculations in parallel. In which he The article mentioned is also designed to be customized VLSI hardware could be used to specific purpose Operations, such as fitting and retrieving, parallel Prozes sor communication and signal symbol processing accelerate.

According to the invention, therefore, the speed and Efficiency of rule-based expert systems thereby ver that conclusions are made Device is provided which is executed in hardware is. In particular, the invention is a Anwendungsspezi create fish integrated circuit, which is specially there is designed for, high-speed conclusions for a perform rule-based expert system. That in Hard ware executed d. H. Hardwired, rule-based Ex pertensystem is described below with the acronym REX (Rule supported expert) and has a working memory in which at the beginning of a conclusion known information or known facts which the scope are stored. to In addition, the system has a rule memory for storage a rule list for the respective field of application. The rule header has a series of instructions or be missing, each one condition or condition or define an action or an operating measure. Further A facility is provided to remove from the rule storage successive instructions or loading into the main memory lack of the control intent to load; beyond that  a logic means is provided to execute the instructions in the Memory regarding the stored facts in the Run memory one after another to create new ones Deduce facts. If during the inference operation new facts are deduced, they are working in the stored and can while running after following instructions from the rule pool are used, to derive additional facts. After completion of the Fol The operation will be stored in the memory transferred facts to an output device.

Each of the rules of the rule set contains an operator a condition / action flag and a pair of operands. The lo The device has a command decoder to handle the Check condition / action flag of each command to determine whether the command is a condition or condition an action or operating measure is. If the command is a condition, the operands are corresponding to the logical operation specified by the operator has been compared to obtain a logical result (eg right or wrong). If the statement is a Action or action, this action, wel has been specified by the operator to whom Operands performed.

The memory and the logical device can be in be provided an integrated circuit. The rule Memory can either be external in the integrated scarf provided and with the main memory via a be connected to the corresponding external memory bus, or The rule memory may be present on the integrated circuit be seen, with corresponding data bus connections with consist of the working memory. Since the application rule rat is stored in a memory, the REX-Fol Regardless of area and can be in a be sweet number of different use cases in simple Be used by another application  rule reserve is housed in the rule memory. The Structure of Rule Memory and the Data Structure of the On application rulesets are designed to work the efficiency and thus the performance of the inference pro to increase their zeal.

To the versatility and the wide scope of the Invention will be described in detail be wrote how the REX inference device as a co-pro computer in conjunction with an existing computer or Microcomputer can be used to provide an expert system create what conclusions with speeds through can lead, which are considerably larger than those which with conventional in-software implications could be carried out. The REX conclusion However, the device can also be used in many other applications cases are used, such as in a selb constantly operating system, if it corresponds with one the internal control system, a user interface and Input / output facilities is provided.

The REX reasoning device can also be a real-time Perform knowledge processing based on the current VLSI Technology based. The speed with which one Problem is solved, instead of floating-point Operatio per second (FLOPS) by logical inference per Second (LIPS). One logical conclusion per Second corresponds to approximately 100 to 1000 floating-point Opera per second in a conventional computer.

The invention will be described below with reference to preferred management forms with reference to the attached drawing explained in detail. It shows

Fig. 1 is a perspective view showing how the REX inference device according to the invention can be used as a co-processor in a conventional personal computer;

Fig. 2 is a more detailed illustration of a co-processor circuit board used in the REX inference device;

Figure 3 is a schematic block diagram of the data flow for the REX device.

4 is a block diagram of the rule-based structure for the REX device.

FIGS. 5a and 5b are diagrams in which the data structure of the instructions is shown that are stored in a gelspeicher Re;

Fig. 6 is a diagram of the operation code format used in the REX chip;

Fig. 7 is an overall block diagram of the main functional components of the REX chip;

FIG. 8 is a diagram of data bus bit allocation for input / output read / write operations; FIG.

Fig. 9 is a flowchart of the inference flow of chips and REX

Fig. 10 to 12 are timing diagrams for the REX-chip showing the timing of the read, the write-mode and of the external memory.

In Fig. 1, an expert system according to the invention is provided, which is adapted to operate with a microcomputer 10 , such as an IBM AT personal computer, which is a rule-based Ex pertensystem (REX) co-processor Circuit card 11 is added. The REX circuit board 11 is composed of a REX chip 12 , an external rule memory 13 and an input / output interface 14 . The REX circuit card is shown in Fig. 2 in detail. An application rule stock for a very specific application, wel cher in Fig. 2 is denoted by 15 is stored in the external rule memory 13 . Consequently, the REX chip 12 is domain independent and can be used in a variety of different applications.

Referring now to Figure 2, each component of the REX co-processor circuit card 11 will be explained in detail:

Input / output interface:
The I / O interface 14 is responsible for the communication between the personal computer 10 and the REX co-processor circuit board 11 . External data is transferred from the personal computer 10 to the REX circuit card 11 via the input / output interface 14 . In the illustrated preferred embodiment, a DMA channel provides data transfer between the REX circuit board 11 and the personal computer 10 . A software program pass through the personal computer is used to provide an easy-to-understand user interface.
REX chip:
The REX chip 12 is a hardware inference device and represents the heart of the REX co-processor circuit card 11. Two major components of the REX chip are memory and control logic. Before the inference process is started, the work memory with external data is initialized by the I / O interface. External data concerning facts known about the scope are stored at very specific memory locations. During the inference process, the memory is temporary storage for intermediate data. When the sequencing process is completed, the memory contains the results of the inference process, which are then transferred to the personal computer via the I / O interface.
Rule memory:
A well-informed engineer extracts a set of production rules, referred to as application rule stock 15 , from the scope, and this rule set is stored in the rule storage 13 . During the inference process, the REX chip 12 refers to the rule memory 13 for control information. The structure of the rule memory is known to adapt to the REX chip requirements and to reduce storage space. The data structure of the application rule set stored in the rule store is appropriately set to greatly increase the efficiency and performance of the inference process. Further details about the structure of the rule storage and the stored rule stock are still given after standing.

The rule memory may be ROM, RAM, EPROM, or other equivalent memory. When a RAM memory is used as a rule memory, an initialization program is used to initially apply the rule set 15 in the external memory 13 .

Although the particular embodiment shown here shows how the REX chip 12 can be used as a co-processor for a personal computer, those skilled in the art will recognize that the hardware-executed, ie, hard-wired, rule-based expert system according to the invention (REX) many other special applications can be used. For example, it can be used as a stand-alone system. In such a case, a control system is provided to handle a user interface and an input / output interface, and additional input / output devices, such as a keypad, a graphic display, etc., are provided to provide a user interface Communication between the REX circuit board and the user is possible.

There are several types of inference methods which can be used to solve a problem in a rule solved expert system to solve. Some of the important fol evaluation procedures are linked forward (forward chaining) backward chaining (backwar chaining) or assign a Combination of these links. The individual dar Asked and described inference used the forward link inference method with product tion rules.

The rules of the rule-based system are by product tion rules. The production rule consists of an if-part and a then-part. The if part is one List from one or more conditions or precursors (Antecedents). The then part is a list of actions or conclusions. Consequently, a production rule are represented as follows:

If condition 1, condition 2, : condition n Then action 1, action 2, : action n

If the conditions (condition    1, condition    2,. , , condition    n) is satisfied by the facts of a given problem, it can be said that the rule is triggered. The expert system can then perform the given actions. Once the actions are done, it says that the rules are enabled. These special actions can change other conditions, which in turn can activate other rules. The constant activation of rules lasts until the problems are solved or no other rules can be met. This method of rule activation is passed through the rules in the forward direction, which is why this is also referred to as forward linkage. A forward link is also referred to as a deduction system of driven facts, as the facts guide the flow or flow of the rules to be acted upon.

The triggering of the rules does not mean that the rules are active Fourth, because of the conditions of some other rules at the same time it can be enough and everything can be triggered. If this happens, then a conflict decision must be made strategy to decide which Re gel is actually activated. A conflict decision Strategy is a process to rule out the most advantageous select if more than one rule is sufficient. Examples for conflict-resolution strategies are the following:

• 1. The rule that contains the most common data becomes selected. This strategy will be data novelty order records.
• 2. The rule, which is the most complicated of the most difficult Requirements is selected. This is also called Context limitation strategy called.
• 3. The rule that is listed first in the list will be chosen. This is called a rule arrangement.

Example 1 Example of a forward chaining

This example is a general representation of the work example of the rule-based expert system. For this dar Position is added to the Animal Identification Rule Pool in the Angang A reference. This rule store tries to Identify animal by its physical charak teristic characteristics are given. The following characteristic features should have been observed:

the animal has hair;
the animal eats meat;
the animal has a yellow-brown color;
the animal has black stripes.

The perceptions are translated into the following facts:

Covering = hair;
Food = meat;
Color = yellow-brown;
Stripes = black.

If these facts are given then rule 1 will be triggered. The rule then deduces:

Class = mammal.

Now the system takes this as a new fact that the animal is a mammal. Consequently, Rule 2 bis Rule 4 will not be triggered. The requirement of Re gel 5 is valid; consequently, the system deduces that Animal is a carnivore.

Carnivore = yes.

So far the system has deduced two new facts which can be used. The first three requirements of Rule 9 is correct, but the last condition applies Not; therefore, the rule is not enough. Rule 10 becomes triggered and can be activated. The system deduced hence that the animal is a tiger.

Animal = Tiger.

The reasoning process does not stop here, as it is still There are more rules. In this case, however, none of the rest will suffice. The system then identifies that Animal as a tiger.

The example shows the inference method in which of the actual facts or observations up to one  Conclusion or result is worked forward.

Architecture of the REX reasoning device

The main components of the REX reasoning device are shown in detail in FIG . The REX chip itself has three main functional components, namely the main memory 16 , an arithmetic logic unit (ALU) 17 and a control logic 18th In the illustrated embodiment, the read-only memory 13 is a separate memory device which is connected to the random access memory 16 through a data bus 21 . However, of course, the data store could, if necessary, be integrated in the REX chip itself. The input / output interface 14 is communi katively connected to the main memory by a designated in its entirety Ge with 22 system interface bus. The control logic 18 is shown schematically in FIG . In general, the task of the control logic 18 is to control the operations of the other elements, such as the arithmetic logic unit (ALU) 17 and the random access memory 16 .

Data flow in the REX reasoning device

The data flow for the REX device is best understood with reference to FIG. 3 and described below. The numbers surrounded by circles in FIG. 3 correspond to the following numbered headings:

1. Input data

The user enters the facts into the system via a user interface program in the personal computer 10 . The user presents the facts in a predefined syntax. For example, using the actual data of example 1 and the rule stock in Appendix A, the user would enter the following:

Covering = hair
Color = yellow-brown
, , ,
, , , etc.

The user interface program sets each actual Observation into values around, which by a few binary numbers are shown. The first part of the pair is an address and the second part of the pair is a value.

In the example above, then:

(Address $ 32) coverage = (value # 10) hair;
(Address $ 58) Color = (value # 55) tan;
, , ,
, , , etc.

where "$" and "#" indicate that the number in question is a Address or value. In the case reproduced above Cover is stored at the address 32. (Nothing else Word is filed at address 32.) Consequently, each one is Word assigned to a unique address number. The value Hair is stored in address 32. These numbers will be used in step 2.

2. Saving facts to memory

In step 2, the factors are ge in the memory ge stores.

3. Store the rules in the main memory

An external memory is used to create rules that are too fit the scope of application. Every rule will as shown:

IF Condition 1 and Condition 2 and , , , THEN Action 1 Action 2 , , ,

A condition element is:

(Class = mammal)

Accordingly, an action item is:
(Type: hoof-shaped)

Every element, be it a condition or an action Part of the rule is internally as an instruction in the shown below format:

Each statement has a predetermined length, for example wise 32 bits. The operand 1 represents an address of the Ar depending on the value of the Dir / Unm field, the operand 2 is an address or a Value in the memory. The Dir / Unm. Field determines whether the addressing mode of operand 2 DIRECT or immediate bar is. The Act./Beding field determines whether the item is refers to the condition or action part of a rule. The operator field determines the type of operator, which in the condition part of the rule is used. Examples of Operators are: equal (=), greater than (<), less as (<) etc.

4-5 inference cycle

The following steps are taken during the inference cycle carried out.

4.1 Retrieve External Memory Element

A rule is retrieved from the rules store 13 and the condition / act field of the rule's first command is checked to see if it is a condition or an action. If the command is a conditional element then the procedure described in section 4.1.1 is applied. If it is an action then the procedure described in section 4.1.2 is used.

4.1.1. Adjust rule condition item to memory sen

The address in operand 1 becomes the arithmetic logic on (ALU) is loaded (step 4). Next is the dir / Unm. Field checked to see if the operand 2 is Direct or Immediately. If he is immediate then he will Value of operand 2 inserted directly in the ALU unit give; otherwise the contents of the operand 2 are indicated showed address entered in ALU unit. The entries in The ALU unit is controlled by the ALU unit using the Operator (operator field) compared to determine if the Condition is right or wrong. If the condition is rich tiger, the next command of the rule is checked, by repeating the sequence of steps described in section 4.1 is reproduced. If the condition element is wrong, then this rule is eliminated, and the next rule is tested by following the steps of section 4.1 is repeated.

4.1.2 Action part

The Dir / Unm. Flag of the action item is checked first. If it is direct then the value which is at the Memory location for operand 2 is stored, to the memory memory represented by operand 1 Address copied. If the Dir / Unm flag is Immediate, then operand 2 is presented to the one indicated by operand 1 set memory address copied. After the execution The action specified by the command becomes the Next action command usually read, and the The procedure described in section 4.1.2 is repeated. If the action command is the last command of the rule, then the next rule is tested by following the step sequence in Section 4.1 is repeated.

6. Facts in data

After all the data has been processed, the control is transmitted to the I / O interface 14 . The numerical representation of the facts is translated into a form which is readily understood by the user.

7. Data Output

The input / output interface will then deliver the data to the personal computer 10 .

example 2 Example of a REX data flow

This example illustrates how the REX chip solves the problem described in Example 1 above. The numbered headings again correspond to the circle surrounded numbers in Figure 3. For the complete animal identification rule stock, reference is again made to Appendix A.

1. Enter external data

The data or the observation made is or is the following:

The animal has hair;
the animal eats meat;
the animal has a yellow-brown color;
the animal has black stripes.

The above data is input to the I / O interface are entered and translated into facts. The data will be then in the following:

(Address $ 32) coverage = (value # 10) hair;
(Address $ 21) Food = (Value # 3) Meat;
(Address $ 58) Color = (value '55) tan;
(Address $ 35) stripe = (value # 8) black.

2. Save facts to memory

The address represents the location in the memory. For example, at the address 32, the value of 10 ge stores.  

3. Load command

A command is loaded from the rules memory. The first Instruction of rule 1 is a condition and has the form:

(Address $ 32) Covering the same (value # 10) hair.

4. Operands loading a) Condition

The value of the address location 32 is in the ALU unit loaded as 10 in this case. The comparison operation the ALU unit is then;

(Value # 10) hair equal (value # 10) hair.

This result is correct.

If the command is:

(Address $ 32) Covering Equal (Value # 11) Springs;

the output value of the ALU unit is wrong. The control returns to step 3.

b) Action

If the command is an action, then:

(Address $ 77) Class MOV (value #) Mammal

The ALU unit receives the value 20 and will receive it at the Store memory location 77.

5. Save facts to memory

The value 20 is deduced from the rule and it will be foal to save him at the address 77. The Control then returns to step 3.

6. Facts in data

In this example, the value at the ($ 88 address) Transfer class to I / O interface. by virtue of of these facts is the value at the address location 88 (value # 100) Tiger.

7. Data output

The value 100 is translated into Tiger by the interface.  

Rule-based structure

The application rule list 15, which is stored in the working memory 16 , is divided into two parts, namely structure and rules. A set of conditions in each rule is grouped together with adjacent addresses. A set of actions in each rule is also grouped together with adjacent addresses. These groups can then be stored in the rule part of the working memory in the following way.

Rule # 1 Address xxx 1 condition 1 1 Address xxx 2 condition 1 2 , @ , @ Address xxxm condition 1 m Address yyy 1 action 1 1 Address yyy 2 action 1 2 , @ , @ Rule # 2 @ Address zzz 1 condition 2 1 , @ ,

Because conditions and actions follow one another at different times Memory addresses can be saved, the representation of rules using the starting address of each rule struk be tured. Consequently, the production rule can be canceled be expressed as:

if xxx 1 then yyy 1 if zzz 1 then , , ,

This format shows that if a group of conditions is correct at a certain point, then the group of actions at the address specified in the THEN part  is performed. If now the first rule is missing, the jumps Control mechanism to the starting address of the next rule. There is no need for the end indicators for every rule; therefore, REX does not waste time searching for End indicators.

A rule-based structure of REX is shown in Fig. 4 Darge. In this version, an external memory in the form of a 64K × 32 ROM is used to store the application rule stock 15 . To maximize the utilization of the limited memory, structure and rules are stored at the ends of the rule memory 13 . In the case of structure, it is started and increased from the address OOOOH. With rules, the address FFFFH is started and then reduced.

The detailed structure of the rule memory is shown in Figs. 5a and b. In structure, the address index is stored which indicates the start address of each rule in RULES. The size of the rule memory is 64K, so only 16-bit lower half words are used.

Each condition or action is represented as a 32-bit word instruction executed by REX. The condition is basically a logical comparison of two given operands. The actions are organized in a similar way. The operators of the actions are basically logical operators and an assignment operator. There are two operands for each operation, namely an operand 1 and an operand 2. The operand 2 can have two forms, namely direct or immediate. As shown in Fig. 4, the direct operand is a pointer to an address in the memory represented by the symbol "$", and the immediate operand is an integer represented by "#".

Command set for REX reasoning device

As shown in Fig. 5 (b), the instructions of REX are always 32 bits long. The operation code (6 bits), operand 1 (13 bits) and operand 2 (13 bits) are composed in a 32-bit instruction. Each rule in a given application rule set has condition and action parts. Therefore, REX has two types of instruction sets:

• - Condition commands:
  This type of command is used to check if the condition is true or false. This allows the users to specify different logical rela tions between two operands, such as "equal", "greater than", and so on. This instruction result of a conditional instruction can only be true or false, which will then affect the next execution order.
• - Action commands:
  This command type is only executed if all the conditions of the current rule are correct. The result of the execution of the action is always stored in the first operand.

The commands and the corresponding opcodes are in Table 1 summarized.

Table 1

REX opcodes

The format of the operand code is shown in FIG . MSB (the most significant bit), ie F1, of the operand code is used to specify the type of instruction. If F1 is 0, then it is a conditional command; otherwise it is an action command.

A conditional instruction always has two operands, while a Action command depending on the operation requirement can only ever have one or two operands.

REX admits two types of addressing modes, one immediate and direct addressing. The first operand used in mer direct addressing mode. The second operand can be immediate data value or direct-addressed data be worth. The addressing mode is determined by checking the two most significant bits (MSB), d. H. F2, the operation code checked. If F2 is 0, the second operand is an immediate one stable data value. Otherwise, the second operand is a direct addressed data value.

Functional description of the REX chip

Referring to Fig. 7, a detailed block diagram of the REX chip 12 is shown . To avoid repetition, ele ments, which have been previously described in connection with an early ren drawing, provided with the same reference characters.

In the following Table 2, the name, the input / output type, and the function of each input or output value shown in Fig. 7 are listed.

Table 2

Pin or pin description of REX

The identification of each register and its respective Function are the following:

• - WM (Memory):
  The random access memory 16 is used to store the intermediate data during the inference process. Before REX starts the reasoning process, the memory is loaded with facts entered by the user. The amount of memory limits the amount of user input in REX at a particular time. In the illustrated embodiment, the working memory is a 4K × 8 random RAM.
• - WMC (Memory Counter) registers:
  WMC is a 13-bit increment counter that can be loaded in parallel. During the input / output mode, WMC is used as a memory address counter for data transfer. When the data transfer is in progress, WMC is automatically incremented. The contents of WMC can then be set by the central unit (CPU) before the data transfer starts.
• - C1 register:
  C1 is a 16-bit increment counter that can be loaded in parallel. During the inference process, C1 points to one of the rule addresses in the structure part of the rule memory 13 . C1 is incremented by 1 before going to the next rule before REX. For a JMP (Spring command, C1 is loaded with a new value instead of being incremented by one.
• C2 register:
  C2 is a 16-bit decrement counter that can be loaded in parallel. C2 points to the rule part of the rule memory. If no false condition occurs in a rule, C2 is decremented by one before REX transitions to the next condition or action. If an incorrect condition of a rule is detected, C2 is loaded with the start address of the next rule instead of being decremented by one.
• - OP registry:
  An OP register contains three parts: the operation code, operand OP1 and operand OP2, which contain a REX instruction. The operation code is a 6-bit register which stores the operator of a command. Both operand groups OP1 and OP2 are 13-bit data registers which store the address of operand 1 or operand 2 in the main memory.
• - OP'-register:
  The OP 'register is a prefetch register that is used to store the prefetch instruction for the OP register. REX now wants to execute the prefetch command, except when a JMP (Spring) command or condition occurs.
• - SI (Start / Idle) control flag:
  SI is used to identify a REX operation state, namely, a conclusion mode or an input / output mode. SI is set by the central processing unit (CPU) after the system sends all the facts to the main memory. SI has the value one during the inference mode. SI is reset by REX each time the inference process stops; then REX switches to input / output mode.
• - IE (Interrupt Enable) control flag:
  IE is set by the central processing unit (CPU) at the same time as the SI flag. REX guarantees the interrupt release before REX goes into the inference mode. IO is used together with the IRQ flag to generate an interrupt signal. The IE flag is reset by the central processing unit (CPU) at the end of the interrupt service program.
• IRQ (Interrupt ReQuest) (Interrupt Request) State Flag:
  When the inference process stops, IRQ is set by REX to indicate that REX is requesting an interrupt at the central processing unit (CPU). IRQ becomes and is linked by IE flags to generate an interrupt signal INT after the interruption is asserted.

When REX operates in the input / output mode, the central one can (CPU) read or write REX registers. The Signals and affected registers are listed in Table 3 lists.

Table 3

Definition of register codes

Operation Modes

REX has two modes of operation, namely the input / output mode and the inference mode. A control flag SI is considered a Fashion flag used. REX switches to the other mode, though the SI flag is changed.

Before REX goes into inference mode, REX has disabled all user Input files from the processing system (host) in the To load RAM from REX. REX is powered by the on / off Output mode switched to inference mode, if the SI- Flag is set by the processing system. After the Conclusion process is finished, the results of the Memory transferred to the processing system.  

During the I / O operation, the processing system may read or write special registers when the REX chip is selected. The control of the read / write operations and the selection of registers are controlled by means of a group of control lines, which are listed in Table 3. During reading and writing of WMC and C / S registers, only a few bits of the system data bus are used. This is shown in FIG. 8.

Once the memory is loaded with user input data, REX starts the inference process from the first rule in the external memory. The inference flow of REX is shown in FIG . There are three different machine cycles for REX in the inference mode.

• T1 cycle:
  T1 is a rule polling cycle. The T1 cycle is executed only at the very beginning of the inference process or when a JMP (Spring) command occurs. In the T1 cycle, the start address of a rule is fetched in the external memory in the C1 register. C1 is a rule counter directed to the start address of a current inference rule.
• T2 cycle:
  T2 is a command fetch cycle. The T2 cycle retrieves the first condition command of each rule in REX registers. The T2 cycle is performed when one of the conditions of a rule is false and execution starts from the first instruction of the next rule to off. C2 may be considered as a command counter directed to a condition command or to an action command which is currently performed in an arithmetic logic unit (ALU).
• T3 cycle:
  The T3 cycle is an instruction execution cycle.

There are several cases of the T3 cycle:

Condition Command / Immediate Data
Condition Command / Direct Addressing
Action command / Immediate data
Action command / direct addressing
JMP (jump)
STOP (rule end)

The instruction prefetch cycle overlaps with T3 cycle. If a JMP (jump) command occurs, the execution sequence goes on the T1 cycle. If the result of a Conditionbe is wrong, the execution sequence goes to the T2-Zy klus. If no JMP (jump) command and no wrong Kondi REX uses the prefetch data, and then on to go the T3 cycle.

REX goes through the same process over and over again until the Fol All rules in the external memory are done are. If the inference process is stopped, it will SI flag reset to "0". Then REX shuts off the Inference mode in the input / output mode.

time charts

The timing diagrams for REX in the input / output read mode, the input / output write mode and the external rule memory are shown in Figs. 10 to 12. The AC characteristics of REX in input / output mode are listed in Table 4.

Table 4

AC Specification

technical terms Heats The if part of a production rule. scope of application The area where the area to which the expert system relates. Application usually stock A set of rules extracted by a well-trained engineer that relates to a specific field of application. ASIC An application specific integrated circuit is custom integrated circuit for a very specific application episode The then part is a production rule. CPU Central unit: An operating unit that processes commands and data. Coprocessor A dedicated processor that works with a host to increase the performance of the entire system. control logic A custom circuit that controls all operations necessary for the REX chip. DMA Direct Memory Access: A commonly used communication method between a host computer and peripheral devices. DMA creates the most effective way to transfer a block of data. External data A block of binary data is stored in a host memory. External storage A memory which stores an application rule supply. fact A truth known from actual experiences and observations. A group of facts is collected in combat conjectures. conclusion Interpret a rule of an application rule set or phrase. Reasoner A problem-solving control mechanism for an expert system. I / O Interface A type of driving device, which is responsible for the communication between the host computer system and the peripheral devices of the computer. Well-informed engineer A person who extracts the knowledge and facts of a particular application and translates them into an application rule set. PC Personal computer PC / DOS The disk driven system of a personal computer managing the read / write operations of a disk drive unit. production rule A rule specified in an if-then format. R.A.M. Random Memory: An electronic memory stores binary information that is read or written by access. ROME Read Only Memory: An electronic memory that stores the binary information. A ROM has only one read access; there is no possibility to write in it. Rule-based structure An organization that stores the production rules in an efficient way to save space and processing time. random access memory A RAM which is stored in the REX chip to store the start, intermediate and end data of an inference process. User Interface A software program responsible for communication between the end users and the host computer system.

Appendix A Example of a rule set or supply for animal identification Rule 1 IF (Coverage = hair) THEN (Class = mammal) Rule 2 @ IF (Product = milk) THEN (Class = mammal) Rule 3 @ IF (Coverage = feathers) THEN (Class = bird) Rule 4 @ IF (Movement = flying) and (product = eggs) THEN (Class = bird) Rule 5 @ IF (Food = meat) THEN (Carnivore = yes). Rule 6 @ IF (Teeth = pointed) and (limb = clown) and (eyes = forward) THEN (Carnivore = Yes) Rule 7 @ IF (Class = mammal) and (limbs = hooves) THEN (Type = ungulate) Rule 8 @ IF (Class = mammal) and (food = recultivated feed) THEN (Type = ungulate) and (toe = even-toed). Rule 9 @ IF (Class = mammal) and (type = carnivore) and (color = yellow-brown) and (spots = dark) THEN (Animal = cheetah). Rule 10 @ IF (Class = mammal) and (type = carnivore) and (color = yellow-brown) and (strip = black) THEN (Animal = tiger) Rule 11 @ IF (Type = hoofed animal) and (neck = long) and (limbs = long) and (points = dark) THEN (Animal = giraffe) Rule 12 @ IF (Type = ungulate) and (stripes = black) THEN (Animal = zebra). Rule 13 @ IF (Class = bird) and (movement << fly) and (neck = long) and (limbs = long) and (color = black-and-white) THEN (Animal = ostrich). Rule 14 @ IF (Class = bird) and (movement << fly) and (float = yes) and (color = black-and-white) THEN (Animal = penguin) Rule 15 @ IF (Class = bird) and (movement = flies well) THEN (Animal = albatross).

Claims (32)

1. A hardware-based, rule-based expert system that can perform high-speed conclusions in artificial intelligence applications based on an application rule set characterized by

• a) a working memory;
• b) input means for receiving external data concerning the application area and for storing the external data in the working memory as facts;
• c) a rule memory;
• d) means for storing in the rule store a rule set for the scope containing a series of commands and instructions each defining a condition or action;
• e) means for sequentially loading the rule store instruction from the rule store into the work memory, and
• f) a logic means for successively executing the instructions in the working memory with respect to the stored facts in the working memory to thereby deduce new facts.

2. expert system according to claim 1, characterized records that the logic device means to save the deduced new data in the working  memory and additionally has an output device, to the deduced new facts, which in the work memory are stored, to an output device to transfer. 3. expert system according to claim 2, characterized indicates that the output device has an input Output interface and has an interface bus, the communicatively the input-output interface with the Ar memory connects. 4. expert system according to claim 1, characterized marked indicates that the main memory is a semiconductor Random memory has, and that the rule memory a having separate semiconductor random memory, and that a Data bus and an address bus are provided by wel the memory and rule memory to carry out a data transfer are interconnected. 5. A hardware-based, rule-based expert system for making high-speed inference in artificial intelligence applications based on a rule set for an application area, characterized by

• a) a working memory;
• b) an input-output interface for communicatively connecting the working memory to an external system, the input-output device having means operable to initialize the inference operation to receive values in the working memory and to store which are known facts pertaining to the field of application;
• c) a rule memory;
• d) means for storing in the rule memory a set of rules for the scope of application containing a series of commands each defining a condition or an action;
• e) means operable during said inference operation for sequentially fetching from said rule memory commands of said rule set and storing them in said working memory;
• f) a logical device operable during the follow-up operation to successively receive the corresponding instructions stored in the work memory and to execute the instructions on the stored facts in the work memory to thereby deduce new facts wherein the logic means also includes means for storing deduced new facts in the working memory for use during execution of the subsequent instructions, and
• g) wherein the input-output device comprises a device which is operable at the conclusion of the reasoning operation to transmit the ge stored in the memory ge facts to an output device.

6. expert system according to claim 5, characterized records that the device to successively Be to retrieve the rule queue, a rule memory Counter having an address register to the Address of the current command in the rule memory to spei and having means to address the address gister with the address of the next command every time to bring up to date when a command from the Rule memory is retrieved. 7. expert system according to claim 5, characterized records that each command of the rule supply a Operator, a condition / action flag, and a pair of operands and that the logical device has a command Decoder to test the condition / action flag to firm determine whether the command is a condition or an action, a device that is operable when the command is a Condition is to set the operands according to the logical To compare operation specified by the operator speci  is fied to produce a logical result, and having means operable when the Command is an action to perform an action, wel have been specified by the operator to the operand is. 8. expert system according to claim 7, characterized gekenn indicates that the logical device is an On which is operable if the logical result the comparison is correct to retrieve the next one To cause an order to follow the same rule. 9. expert system according to claim 8, characterized indicates that the logical device is an On which is operable if the logical Result of the comparison is wrong to retrieve the first command of the next rule. 10. expert system according to claim 7, characterized draws that each command also a direct / immediate bar flag to the addressing mode of one of the operans to specify the. 11. An expert system implemented in hardware to perform high-speed conclusions in artificial intelligence applications based on a rule set for a particular application, characterized by an integrated circuit providing:

• a) a working memory;
• b) a system interface bus to communicatively connect the main memory to an external system to receive values representing known facts pertaining to the application area and to store them in the working memory;
• c) a rule storage bus for communicating with an external rule store in which a rule set or set is stored for the scope containing a series of commands each defining a condition or action;
• d) a rule memory counter with an address register to store the address of the current instruction in the external memory;
• e) means for retrieving the current instruction from the rule storage via the rule storage bus, and
• f) a logical means for receiving the current command and executing the command on the stored data in the main memory to thereby deduce new facts.

12. expert system according to claim 11, characterized records that the logical device is also a Device for storing deduced, new facts in the Has memory. 13. Hardware-based, rule-based expert system characterized by

• a) a working memory;
• b) means for receiving external data representing known facts and for storing values representing the facts at predetermined memory addresses of the working memory;
• c) a memory for storing a rule set;
• d) a rule set having a series of rules stored in the memory, each rule of the rule set including a series of instructions stored at successive memory addresses of the memory;
• e) at least one of the instructions of each rule, which represent a condition or condition which is satisfied by the facts of a given problem, and which include one
  • (i) an operation code specifying a logical operation to be performed;
  • (ii) a first operand specifying a first value to be compared by the logical operation, and
  • (iii) a second operand which sets the address in the working memory containing a second value to be compared by the logical operation.

14. Expert system according to claim 13, characterized in that

• f) at least one of the commands of each rule represents an action to be performed when all the conditions or conditions to be performed are satisfied and which has
  • (i) an operation code which specifies the action to be performed;
  • (ii) a first operand specifying a value for a fact, and
  • (iii) a second operand which specifies an address in the random access memory to which the value defined in the first operand is to be stored.

15. An application rule set for a hardware-executed, rule-based expert system having a memory with a memory address, characterized in that the rule set comprises
a series of rules stored in the memory;
each rule of the rule set containing a series of instructions stored at successive memory addresses of the memory;
at least one of the commands of each rule representing a condition or condition to be satisfied by the facts of a given problem and at least one of the commands of each rule representing an action to be performed when the condition is satisfied. 16. Rule set according to claim 15, characterized marked draws that the instructions in length are all the same Have number of bits.   17. Rule set according to claim 15, characterized marked records that certain bits of each instruction one Operands and other bits of the instruction, an operation code establish. 18. Rule set according to claim 15, characterized marked records that at least one bit of the instruction is on Flag indicating whether the command is a condition or an action is. 19. Rule set according to claim 16, characterized marked records that the instructions are 32 bits long and bits which define an operation code, bits which one specify first operands, bits defining a second operand specify at least one bit, which sets a flag indicating whether the command is a condition or an action is. 20. Rule set according to claim 16, characterized marked records that the instructions each at least one bit containing the addressing mode of one of the operands shows. 21. Rule set according to claim 15, characterized marked draws that the rules of the ruleset as a Series of commands at successive addresses ge stores are started, starting at one end of the memory , and have a rule index which abuts on the following memory addresses is stored, where the opposite end of the memory is started, where the rule index is a series of memory addresses which indicates the initial memory address of each rule of the Set ruleset. 22. An application rule set for a hardware-executed, rule-based expert system having a memory with a number of memory addresses, characterized in that the rule set comprises
a series of rules, each in turn containing a series of instructions which are a predetermined number of bits long and stored at successive memory addresses of the memory;
certain commands of each rule representing a condition or condition satisfied by the facts of a given problem;
yet other instructions of each rule representing an action to perform when this rule is activated and a rule index also stored in the memory and holding a series of memory addresses in the memory corresponding to the starting memory address of each rule of the rule set , 23. Rule set according to claim 22, characterized marked records that the rules of the ruleset are on consecutive memory addresses are stored, wherein is started at one end of the memory, and that the Re gelindex stored at successive memory addresses chert is, being at the opposite end of the Spei chers is started. 24. Rule set according to claim 22, characterized marked records that each of the ruleset's commands an operator, a condition / action flag and a pair Has operands. 25. An application rule set for a hardware-executed, rule-based expert system having a memory with a number of memory addresses, characterized in that it comprises the rule set
a set of rules, each consisting of a series of instructions which are a predetermined number of bits long, the instructions of each rule being stored at successive memory addresses of the memory and the rules of the rule set to be stored beginning at one end of the memory;
wherein the instructions bits defining an operation code, bits specifying a first operand, bits specifying a second operand, at least one bit specifying a flag indicating whether the instruction is a condition or an action, and have at least one bit indicating the addressing mode of one of the operands, and a rule index also stored in the memory and having a series of memory addresses in the memory corresponding to the initial memory address of each rule of the rule set, the rule index in memory addresses beginning at the other end of the memory from which the ruleset begins. 26. A method for a hardware-based, rule-based expert system for performing high-speed sequences in artificial intelligence applications based on a rule set for a particular application, characterized in that

• (a) storing in known memory known facts pertaining to the scope;
• (b) a policy set is stored in a rule store for the scope of application which has a number of items each defining a condition or an action;
• (c) loading a rule set instruction from the rule memory into the memory and;
• (d) executing the instruction in the working memory with respect to the stored data in the working memory.

27. The method according to claim 26, characterized gekenn characterized in that steps (c) and (d) are for one another the following commands of the ruleset are repeated to deduce a new fact and that the deduced new one Fact is stored in the memory.   28. The method according to claim 27, characterized records that the step is a rule set in the To store rules memory, saving the commands of the Ruleset at consecutive memory addresses of the Rule memory and that a memory address Register with the address of the next command every time is updated when a command is issued the rule memory is loaded. 29. The method according to claim 26, characterized gekenn records that saving a rule set in a rule memory storing instructions which an operator, a condition / action flag and a pair Operands contained, at successive Speicheradres sen of the rule memory, and that performing of the command, checking the condition / action flag closes to determine if the command is a condition or an action is. 30. The method according to claim 29, characterized gekenn records that the step being performed if the instruction is a condition that corresponds to operands to compare the logical operation, which by the Operator is specified, thereby providing a logical result did produce. 31. The method according to claim 29, characterized marked records that the step being performed if the command is an action that performs action, which is specified by the operator to the operand. 32. A method for a hardware-based, rule-based expert system for making high-speed in artificial intelligence applications based on a rule set for a particular application, characterized in that:

• (a) a set of characteristics is defined which correspond to the scope;
• (b) allocating each characteristic of the set to specify memory addresses in a random access memory;
• (c) from the set for a particular problem to be solved by the expert system, selecting those characteristics having values that are known;
• (d) storing the values for the known characteristics in the random access memory at corresponding memory addresses associated with these characteristics;
• (e) a policy set is stored in a rule store, the rule set containing a set of commands;
• (F) are loaded from the rule memory in the working memory on successive commands of the rule set, and the instructions are executed with respect to the stored characteristics in the working memory, thereby to deduce a value for an unknown characteristic and
• (g) storing the deduced value in memory at the corresponding memory address for that characteristic.