DE3885834D1 - Lötstelle und Verfahren zu ihrer Bewerkstelligung. - Google Patents

Lötstelle und Verfahren zu ihrer Bewerkstelligung.

Info

Publication number
DE3885834D1
DE3885834D1 DE88115732T DE3885834T DE3885834D1 DE 3885834 D1 DE3885834 D1 DE 3885834D1 DE 88115732 T DE88115732 T DE 88115732T DE 3885834 T DE3885834 T DE 3885834T DE 3885834 D1 DE3885834 D1 DE 3885834D1
Authority
DE
Germany
Prior art keywords
accomplishing
soldering point
soldering
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88115732T
Other languages
English (en)
Other versions
DE3885834T2 (de
Inventor
Koji C O Patent Divis Yamakawa
Nobuo C O Patent Divisio Iwase
Michihiko C O Patent Div Inaba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62239817A external-priority patent/JP2633580B2/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3885834D1 publication Critical patent/DE3885834D1/de
Publication of DE3885834T2 publication Critical patent/DE3885834T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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DE88115732T 1987-09-24 1988-09-23 Lötstelle und Verfahren zu ihrer Bewerkstelligung. Expired - Fee Related DE3885834T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62239817A JP2633580B2 (ja) 1987-09-24 1987-09-24 バンプ、バンプの形成方法および半導体素子
JP6138688 1988-03-15

Publications (2)

Publication Number Publication Date
DE3885834D1 true DE3885834D1 (de) 1994-01-05
DE3885834T2 DE3885834T2 (de) 1994-04-28

Family

ID=26402429

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88115732T Expired - Fee Related DE3885834T2 (de) 1987-09-24 1988-09-23 Lötstelle und Verfahren zu ihrer Bewerkstelligung.

Country Status (4)

Country Link
US (1) US4970571A (de)
EP (1) EP0308971B1 (de)
KR (1) KR910006949B1 (de)
DE (1) DE3885834T2 (de)

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EP0308971A2 (de) 1989-03-29
EP0308971A3 (en) 1990-10-10
EP0308971B1 (de) 1993-11-24
KR890005857A (ko) 1989-05-17
KR910006949B1 (ko) 1991-09-14
US4970571A (en) 1990-11-13
DE3885834T2 (de) 1994-04-28

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