DE3885268D1 - Verdrahtungsleiter für Halbleiteranordnung. - Google Patents

Verdrahtungsleiter für Halbleiteranordnung.

Info

Publication number
DE3885268D1
DE3885268D1 DE88121320T DE3885268T DE3885268D1 DE 3885268 D1 DE3885268 D1 DE 3885268D1 DE 88121320 T DE88121320 T DE 88121320T DE 3885268 T DE3885268 T DE 3885268T DE 3885268 D1 DE3885268 D1 DE 3885268D1
Authority
DE
Germany
Prior art keywords
semiconductor device
wiring conductor
conductor
wiring
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88121320T
Other languages
English (en)
Other versions
DE3885268T2 (de
Inventor
Marvin Lumbard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of DE3885268D1 publication Critical patent/DE3885268D1/de
Publication of DE3885268T2 publication Critical patent/DE3885268T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
DE88121320T 1987-12-28 1988-12-20 Verdrahtungsleiter für Halbleiteranordnung. Expired - Fee Related DE3885268T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/138,887 US4859632A (en) 1987-12-28 1987-12-28 Method for manufacturing the same

Publications (2)

Publication Number Publication Date
DE3885268D1 true DE3885268D1 (de) 1993-12-02
DE3885268T2 DE3885268T2 (de) 1994-04-21

Family

ID=22484103

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88121320T Expired - Fee Related DE3885268T2 (de) 1987-12-28 1988-12-20 Verdrahtungsleiter für Halbleiteranordnung.

Country Status (4)

Country Link
US (1) US4859632A (de)
EP (1) EP0331814B1 (de)
JP (1) JP2696772B2 (de)
DE (1) DE3885268T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5234866A (en) * 1985-03-25 1993-08-10 Hitachi, Ltd. Semiconductor device and process for producing the same, and lead frame used in said process
US5026667A (en) * 1987-12-29 1991-06-25 Analog Devices, Incorporated Producing integrated circuit chips with reduced stress effects
US5038453A (en) * 1988-07-22 1991-08-13 Rohm Co., Ltd. Method of manufacturing semiconductor devices, and leadframe and differential overlapping apparatus therefor
US5184207A (en) * 1988-12-07 1993-02-02 Tribotech Semiconductor die packages having lead support frame
US5038468A (en) * 1990-04-19 1991-08-13 Illinois Tool Works Inc. Method of insert molding with web placed in the mold
JPH0419114A (ja) * 1990-05-15 1992-01-23 Mitsubishi Electric Corp インサート電極モールド体の製造方法
US5167556A (en) * 1990-07-03 1992-12-01 Siemens Aktiengesellschaft Method for manufacturing a light emitting diode display means
KR950003337B1 (ko) * 1990-08-23 1995-04-10 미쓰비시덴키 가부시키가이샤 내연기관용 점화장치의 제조방법
US5270262A (en) * 1991-02-28 1993-12-14 National Semiconductor Corporation O-ring package
US5185653A (en) * 1990-11-08 1993-02-09 National Semiconductor Corporation O-ring package
US5098863A (en) * 1990-11-29 1992-03-24 Intel Corporation Method of stabilizing lead dimensions on high pin count surface mount I.C. packages
US5132773A (en) * 1991-02-06 1992-07-21 Olin Corporation Carrier ring having first and second ring means with bonded surfaces
US5213748A (en) * 1991-06-27 1993-05-25 At&T Bell Laboratories Method of molding a thermoplastic ring onto a leadframe
JP2923096B2 (ja) * 1991-09-10 1999-07-26 株式会社日立製作所 テープキャリアパッケージおよび高周波加熱はんだ接合装置
US5146662A (en) * 1991-12-30 1992-09-15 Fierkens Richard H J Lead frame cutting apparatus for various sized integrated circuit packages and method therefor
US5609652A (en) * 1994-04-13 1997-03-11 Koito Manufacturing Co., Ltd. Method of manufacturing a synthetic resin part integrally formed with metal members
FR2736740A1 (fr) * 1995-07-11 1997-01-17 Trt Telecom Radio Electr Procede de production et d'assemblage de carte a circuit integre et carte ainsi obtenue
US5640746A (en) * 1995-08-15 1997-06-24 Motorola, Inc. Method of hermetically encapsulating a crystal oscillator using a thermoplastic shell
US5890644A (en) * 1996-01-26 1999-04-06 Micron Technology, Inc. Apparatus and method of clamping semiconductor devices using sliding finger supports
US5673845A (en) 1996-06-17 1997-10-07 Micron Technology, Inc. Lead penetrating clamping system
US6003369A (en) * 1997-05-19 1999-12-21 Continental Teves, Inc. Method for manufacturing encapsulated semiconductor devices
US6986197B2 (en) * 2001-12-06 2006-01-17 Asm Technology Singapore Pte Ltd. Method of manufacturing an IC package
KR20030085868A (ko) * 2002-05-02 2003-11-07 삼성전기주식회사 부품 다층 실장 소자의 제조방법 및 이에 의해 제조된 소자
US7279785B2 (en) * 2005-02-14 2007-10-09 Stats Chippac Ltd. Stacked die package system

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3444440A (en) * 1964-11-27 1969-05-13 Motorola Inc Multiple lead semiconductor device with plastic encapsulation supporting such leads and associated elements
US3385426A (en) * 1966-03-18 1968-05-28 Sprague Electric Co Lead protecting structure
US3689991A (en) * 1968-03-01 1972-09-12 Gen Electric A method of manufacturing a semiconductor device utilizing a flexible carrier
US3864820A (en) * 1971-01-04 1975-02-11 Gte Sylvania Inc Fabrication Packages Suitable for Integrated Circuits
US3611061A (en) * 1971-07-07 1971-10-05 Motorola Inc Multiple lead integrated circuit device and frame member for the fabrication thereof
US3838984A (en) * 1973-04-16 1974-10-01 Sperry Rand Corp Flexible carrier and interconnect for uncased ic chips
JPS5339866A (en) * 1976-09-24 1978-04-12 Fujitsu Ltd Packaging method of semiconductor device
US4132856A (en) * 1977-11-28 1979-01-02 Burroughs Corporation Process of forming a plastic encapsulated molded film carrier CML package and the package formed thereby
US4282544A (en) * 1977-12-12 1981-08-04 Motorola Inc. Encapsulated hybrid circuit assembly
JPS5521128A (en) * 1978-08-02 1980-02-15 Hitachi Ltd Lead frame used for semiconductor device and its assembling
JPS5588350A (en) * 1978-12-27 1980-07-04 Hitachi Ltd Manufacture of semiconductor device
US4214364A (en) * 1979-05-21 1980-07-29 Northern Telecom Limited Hermetic and non-hermetic packaging of devices
US4305204A (en) * 1980-01-16 1981-12-15 Litronix, Inc. Method for making display device
US4413404A (en) * 1980-04-14 1983-11-08 National Semiconductor Corporation Process for manufacturing a tear strip planarization ring for gang bonded semiconductor device interconnect tape
US4477827A (en) * 1981-02-02 1984-10-16 Northern Telecom Limited Lead frame for leaded semiconductor chip carriers
US4380042A (en) * 1981-02-23 1983-04-12 Angelucci Sr Thomas L Printed circuit lead carrier tape
US4466183A (en) * 1982-05-03 1984-08-21 National Semiconductor Corporation Integrated circuit packaging process
US4480150A (en) * 1982-07-12 1984-10-30 Motorola Inc. Lead frame and method
JPS60165748A (ja) * 1984-02-08 1985-08-28 Toshiba Corp リ−ドフレ−ム
US4701781A (en) * 1984-07-05 1987-10-20 National Semiconductor Corporation Pre-testable semiconductor die package
JPS61212031A (ja) * 1985-03-15 1986-09-20 Matsushita Electric Ind Co Ltd デイスプレイパネルの実装体
JPS61296749A (ja) * 1985-06-25 1986-12-27 Toray Silicone Co Ltd 半導体装置用リードフレームの製造方法
EP0213014B1 (de) * 1985-07-23 1990-09-19 Fairchild Semiconductor Corporation Verpackungsanordnung für Halbleiterchip und Verfahren zum Erleichtern deren Prüfung und Montage auf ein Substrat
GB2178895B (en) * 1985-08-06 1988-11-23 Gen Electric Co Plc Improved preparation of fragile devices
US4689875A (en) * 1986-02-13 1987-09-01 Vtc Incorporated Integrated circuit packaging process

Also Published As

Publication number Publication date
EP0331814A3 (en) 1989-10-04
US4859632A (en) 1989-08-22
JPH023262A (ja) 1990-01-08
EP0331814A2 (de) 1989-09-13
DE3885268T2 (de) 1994-04-21
JP2696772B2 (ja) 1998-01-14
EP0331814B1 (de) 1993-10-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee