DE3885160D1 - Verfahren zur Bearbeitung der kanten Halbleiterplättchen sowie dazugehörige Apparatur. - Google Patents

Verfahren zur Bearbeitung der kanten Halbleiterplättchen sowie dazugehörige Apparatur.

Info

Publication number
DE3885160D1
DE3885160D1 DE88201242T DE3885160T DE3885160D1 DE 3885160 D1 DE3885160 D1 DE 3885160D1 DE 88201242 T DE88201242 T DE 88201242T DE 3885160 T DE3885160 T DE 3885160T DE 3885160 D1 DE3885160 D1 DE 3885160D1
Authority
DE
Germany
Prior art keywords
processing
semiconductor wafers
associated equipment
edge semiconductor
edge
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88201242T
Other languages
English (en)
Other versions
DE3885160T2 (de
Inventor
Giorgio Beretta
Antonino Inserra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of DE3885160D1 publication Critical patent/DE3885160D1/de
Application granted granted Critical
Publication of DE3885160T2 publication Critical patent/DE3885160T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67028—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like
    • H01L21/6704—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing
    • H01L21/67057—Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing with the semiconductor substrates being dipped in baths or vessels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
DE88201242T 1987-06-29 1988-06-20 Verfahren zur Bearbeitung der kanten Halbleiterplättchen sowie dazugehörige Apparatur. Expired - Fee Related DE3885160T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8706615A IT1229640B (it) 1987-06-29 1987-06-29 Processo di conformazione del bordo di fette di materiale semiconduttore e relativa apparecchiatura

Publications (2)

Publication Number Publication Date
DE3885160D1 true DE3885160D1 (de) 1993-12-02
DE3885160T2 DE3885160T2 (de) 1994-04-07

Family

ID=11121454

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88201242T Expired - Fee Related DE3885160T2 (de) 1987-06-29 1988-06-20 Verfahren zur Bearbeitung der kanten Halbleiterplättchen sowie dazugehörige Apparatur.

Country Status (5)

Country Link
US (1) US4897369A (de)
EP (1) EP0297648B1 (de)
JP (1) JPH01220832A (de)
DE (1) DE3885160T2 (de)
IT (1) IT1229640B (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2645478B2 (ja) * 1988-10-07 1997-08-25 富士通株式会社 半導体装置の製造方法
US5128281A (en) * 1991-06-05 1992-07-07 Texas Instruments Incorporated Method for polishing semiconductor wafer edges
JPH0715897B2 (ja) * 1991-11-20 1995-02-22 株式会社エンヤシステム ウエ−ハ端面エッチング方法及び装置
JP2628424B2 (ja) * 1992-01-24 1997-07-09 信越半導体株式会社 ウエーハ面取部の研磨方法及び装置
US5424224A (en) * 1993-01-19 1995-06-13 Texas Instruments Incorporated Method of surface protection of a semiconductor wafer during polishing
US5595522A (en) * 1994-01-04 1997-01-21 Texas Instruments Incorporated Semiconductor wafer edge polishing system and method
DE69428986D1 (de) * 1994-07-29 2001-12-13 St Microelectronics Srl Verfahren zur Behandlung von Halbleiterscheiben mit Flüssigkeiten
US6523553B1 (en) * 1999-03-30 2003-02-25 Applied Materials, Inc. Wafer edge cleaning method and apparatus
US6465353B1 (en) * 2000-09-29 2002-10-15 International Rectifier Corporation Process of thinning and blunting semiconductor wafer edge and resulting wafer
US20050211379A1 (en) * 2004-03-29 2005-09-29 Hung-Wen Su Apparatus and method for removing metal from wafer edge
US20050252547A1 (en) * 2004-05-11 2005-11-17 Applied Materials, Inc. Methods and apparatus for liquid chemical delivery
JP4993721B2 (ja) * 2007-07-02 2012-08-08 シャープ株式会社 薄板処理方法および薄板処理装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3951728A (en) * 1974-07-30 1976-04-20 Hitachi, Ltd. Method of treating semiconductor wafers
JPS5433676A (en) * 1977-08-22 1979-03-12 Hitachi Ltd Wafer processing unit
JPS55143037A (en) * 1979-04-25 1980-11-08 Hitachi Ltd Treating method of semiconductor complex
JPS5928036Y2 (ja) * 1980-07-15 1984-08-14 信越化学工業株式会社 化学エツチング処理装置
JPS5958827A (ja) * 1982-09-28 1984-04-04 Toshiba Corp 半導体ウエ−ハ、半導体ウエ−ハの製造方法及び半導体ウエ−ハの製造装置
JPS5994425A (ja) * 1982-11-19 1984-05-31 Nec Kyushu Ltd 半導体製造装置
JPS59117123A (ja) * 1982-12-23 1984-07-06 Toshiba Corp レジスト除去装置
JPS6072234A (ja) * 1983-09-28 1985-04-24 Mitsubishi Electric Corp 半導体ウエハ−の水洗装置
JPS61230332A (ja) * 1985-04-04 1986-10-14 Mitsubishi Electric Corp ウエハ等薄板体の搬送装置
JPS6296400A (ja) * 1985-10-23 1987-05-02 Mitsubishi Metal Corp ウエハの製造方法

Also Published As

Publication number Publication date
IT1229640B (it) 1991-09-04
EP0297648A3 (en) 1990-05-30
IT8706615A0 (it) 1987-06-29
EP0297648B1 (de) 1993-10-27
US4897369A (en) 1990-01-30
JPH01220832A (ja) 1989-09-04
DE3885160T2 (de) 1994-04-07
EP0297648A2 (de) 1989-01-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee