DE3880478D1 - Geschichtetes netz. - Google Patents

Geschichtetes netz.

Info

Publication number
DE3880478D1
DE3880478D1 DE8989900410T DE3880478T DE3880478D1 DE 3880478 D1 DE3880478 D1 DE 3880478D1 DE 8989900410 T DE8989900410 T DE 8989900410T DE 3880478 T DE3880478 T DE 3880478T DE 3880478 D1 DE3880478 D1 DE 3880478D1
Authority
DE
Germany
Prior art keywords
layered net
layered
net
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8989900410T
Other languages
English (en)
Other versions
DE3880478T2 (de
Inventor
Ralph Larson
Bruce Bennett
Allen Murphy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Publication of DE3880478D1 publication Critical patent/DE3880478D1/de
Application granted granted Critical
Publication of DE3880478T2 publication Critical patent/DE3880478T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/64—Distributing or queueing
    • H04Q3/68—Grouping or interlacing selector groups or stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1507—Distribute and route fabrics, e.g. sorting-routing or Batcher-Banyan
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/20—Support for services
    • H04L49/205—Quality of Service based
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/25—Routing or path finding in a switch fabric
    • H04L49/253—Routing or path finding in a switch fabric using establishment or release of connections between ports
    • H04L49/254—Centralised controller, i.e. arbitration or scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/40—Constructional details, e.g. power supply, mechanical construction or backplane
DE8989900410T 1987-10-14 1988-10-14 Geschichtetes netz. Expired - Fee Related DE3880478T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/108,514 US4833468A (en) 1987-10-14 1987-10-14 Layered network
PCT/US1988/003608 WO1989003566A2 (en) 1987-10-14 1988-10-14 Layered network

Publications (2)

Publication Number Publication Date
DE3880478D1 true DE3880478D1 (de) 1993-05-27
DE3880478T2 DE3880478T2 (de) 1993-08-05

Family

ID=22322642

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8989900410T Expired - Fee Related DE3880478T2 (de) 1987-10-14 1988-10-14 Geschichtetes netz.

Country Status (5)

Country Link
US (1) US4833468A (de)
EP (1) EP0334954B1 (de)
JP (1) JPH02501183A (de)
DE (1) DE3880478T2 (de)
WO (1) WO1989003566A2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5088032A (en) * 1988-01-29 1992-02-11 Cisco Systems, Inc. Method and apparatus for routing communications among computer networks
US5163149A (en) * 1988-11-02 1992-11-10 International Business Machines Corporation Combining switch for reducing accesses to memory and for synchronizing parallel processes
US5258752A (en) * 1988-11-25 1993-11-02 Sumitomo Electric Industries, Ltd. Broad band digital exchange
US5123011A (en) * 1989-09-27 1992-06-16 General Electric Company Modular multistage switch for a parallel computing system
WO1991014326A2 (en) * 1990-03-05 1991-09-19 Massachusetts Institute Of Technology Switching networks with expansive and/or dispersive logical clusters for message routing
US5216420A (en) * 1990-07-12 1993-06-01 Munter Ernst A Matrix sorting network for sorting N inputs onto N outputs
US5144293A (en) * 1990-12-18 1992-09-01 International Business Machines Corporation Serial link communication system with cascaded switches
US5321813A (en) 1991-05-01 1994-06-14 Teradata Corporation Reconfigurable, fault tolerant, multistage interconnect network and protocol
US5307413A (en) * 1991-07-19 1994-04-26 Process Software Corporation Method and apparatus for adding data compression and other services in a computer network
CA2113647A1 (en) * 1991-08-05 1993-02-18 Aloke Guha Crossbar with return net for scalable self-routing non-blocking message switching and routing system
US5701120A (en) * 1992-12-13 1997-12-23 Siemens Business Communication Systems, Inc. Partitioned point-to-point communications networks
JP3094849B2 (ja) * 1995-06-21 2000-10-03 株式会社日立製作所 並列計算機およびその多段結合網
KR100278016B1 (ko) * 1995-12-26 2001-01-15 윤종용 비동기 전송모드 교환시스템의 스위칭 장치 및 방법
US5867649A (en) * 1996-01-23 1999-02-02 Multitude Corporation Dance/multitude concurrent computation
US5787082A (en) * 1996-05-13 1998-07-28 Lockheed Martin Corporation Identification of new and stale packets in switching networks used with scalable coherent interfaces
US5787081A (en) * 1996-05-13 1998-07-28 Lockheed Martin Corporation Allocation of node transmissions in switching networks used with scalable coherent interfaces
US5826028A (en) * 1996-05-13 1998-10-20 Lockheed Martin Corporation Initialization of switching networks for use with a scalable coherent interface
US5790524A (en) * 1996-05-13 1998-08-04 Lockheed Martin Corporation Detection of lost packets in switching networks used with scalable coherent interfaces
FI103312B (fi) * 1996-11-06 1999-05-31 Nokia Telecommunications Oy Kytkentämatriisi
US6018523A (en) * 1997-10-22 2000-01-25 Lucent Technologies, Inc. Switching networks having improved layouts
US6301247B1 (en) * 1998-04-06 2001-10-09 Lockheed Martin Corporation Pad and cable geometries for spring clip mounting and electrically connecting flat flexible multiconductor printed circuit cables to switching chips on spaced-parallel planar modules
US6215786B1 (en) 1998-04-06 2001-04-10 Lockheed Martin Corporation Implementation of multi-stage switching networks
US6529983B1 (en) 1999-11-03 2003-03-04 Cisco Technology, Inc. Group and virtual locking mechanism for inter processor synchronization
US6519697B1 (en) 1999-11-15 2003-02-11 Ncr Corporation Method and apparatus for coordinating the configuration of massively parallel systems
US6745240B1 (en) 1999-11-15 2004-06-01 Ncr Corporation Method and apparatus for configuring massively parallel systems
US6412002B1 (en) 1999-11-15 2002-06-25 Ncr Corporation Method and apparatus for selecting nodes in configuring massively parallel systems
US6418526B1 (en) 1999-11-15 2002-07-09 Ncr Corporation Method and apparatus for synchronizing nodes in massively parallel systems
US6892237B1 (en) 2000-03-28 2005-05-10 Cisco Technology, Inc. Method and apparatus for high-speed parsing of network messages
US6505269B1 (en) 2000-05-16 2003-01-07 Cisco Technology, Inc. Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
US6836815B1 (en) * 2001-07-11 2004-12-28 Pasternak Solutions Llc Layered crossbar for interconnection of multiple processors and shared memories
US7177301B2 (en) * 2001-12-27 2007-02-13 Intel Corporation Signal permuting
US7523218B1 (en) 2002-04-30 2009-04-21 University Of Florida Research Foundation, Inc. O(log n) dynamic router tables for prefixes and ranges
US7474657B2 (en) * 2002-04-30 2009-01-06 University Of Florida Research Foundation, Inc. Partitioning methods for dynamic router tables
US20040018237A1 (en) * 2002-05-31 2004-01-29 Perricone Nicholas V. Topical drug delivery using phosphatidylcholine
WO2004006061A2 (en) * 2002-07-03 2004-01-15 University Of Florida Dynamic ip router tables using highest-priority matching
US7444318B2 (en) * 2002-07-03 2008-10-28 University Of Florida Research Foundation, Inc. Prefix partitioning methods for dynamic router tables
US7801156B2 (en) * 2007-04-13 2010-09-21 Alcatel-Lucent Usa Inc. Undirected cross connects based on wavelength-selective switches
US8065433B2 (en) 2009-01-09 2011-11-22 Microsoft Corporation Hybrid butterfly cube architecture for modular data centers
GB2474446A (en) * 2009-10-13 2011-04-20 Advanced Risc Mach Ltd Barrier requests to maintain transaction order in an interconnect with multiple paths

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE381548B (sv) * 1974-12-20 1975-12-08 Ellemtel Utvecklings Ab Anordning for omstyrning av veljarnet
JPS51110642A (de) * 1975-03-25 1976-09-30 Kyonobu Kinoshita
US4004103A (en) * 1975-10-15 1977-01-18 Bell Telephone Laboratories, Incorporated Path-finding scheme for a multistage switching network
JPS58147573A (ja) * 1982-02-27 1983-09-02 Toagosei Chem Ind Co Ltd 塩酸製造法
GB2130049B (en) * 1982-10-21 1986-01-29 Plessey Co Plc Method of growth of a digital switchblock
US4566007A (en) * 1983-05-16 1986-01-21 At&T Bell Laboratories Rearrangeable multiconnection switching networks
US4654842A (en) * 1984-08-02 1987-03-31 Coraluppi Giorgio L Rearrangeable full availability multistage switching network with redundant conductors
US4656622A (en) * 1984-09-26 1987-04-07 American Telephone And Telegraph Company Multiple paths in a self-routing packet and circuit switching network
JPS61214694A (ja) * 1985-03-18 1986-09-24 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション データ伝送のスイッチング装置
US4752777A (en) * 1985-03-18 1988-06-21 International Business Machines Corporation Delta network of a cross-point switch

Also Published As

Publication number Publication date
US4833468A (en) 1989-05-23
WO1989003566A2 (en) 1989-04-20
JPH02501183A (ja) 1990-04-19
EP0334954A1 (de) 1989-10-04
WO1989003566A3 (en) 1989-06-01
EP0334954B1 (de) 1993-04-21
DE3880478T2 (de) 1993-08-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee