DE3850901D1 - Datenverarbeitungsanordnung mit Mitteln zur angrenzenden Adressierung eines Speichers. - Google Patents

Datenverarbeitungsanordnung mit Mitteln zur angrenzenden Adressierung eines Speichers.

Info

Publication number
DE3850901D1
DE3850901D1 DE3850901T DE3850901T DE3850901D1 DE 3850901 D1 DE3850901 D1 DE 3850901D1 DE 3850901 T DE3850901 T DE 3850901T DE 3850901 T DE3850901 T DE 3850901T DE 3850901 D1 DE3850901 D1 DE 3850901D1
Authority
DE
Germany
Prior art keywords
memory
data processing
processing arrangement
adjacent addressing
addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3850901T
Other languages
English (en)
Other versions
DE3850901T2 (de
Inventor
Dag Reidar Blokkum
Charles Ray Johns
Lee Jack Morozink
David Lawrence Peterson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3850901D1 publication Critical patent/DE3850901D1/de
Application granted granted Critical
Publication of DE3850901T2 publication Critical patent/DE3850901T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
DE3850901T 1987-04-01 1988-03-29 Datenverarbeitungsanordnung mit Mitteln zur angrenzenden Adressierung eines Speichers. Expired - Fee Related DE3850901T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/034,236 US4908789A (en) 1987-04-01 1987-04-01 Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range

Publications (2)

Publication Number Publication Date
DE3850901D1 true DE3850901D1 (de) 1994-09-08
DE3850901T2 DE3850901T2 (de) 1995-03-09

Family

ID=21875137

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3850901T Expired - Fee Related DE3850901T2 (de) 1987-04-01 1988-03-29 Datenverarbeitungsanordnung mit Mitteln zur angrenzenden Adressierung eines Speichers.

Country Status (5)

Country Link
US (1) US4908789A (de)
EP (1) EP0285986B1 (de)
JP (1) JPH065513B2 (de)
BR (1) BR8801568A (de)
DE (1) DE3850901T2 (de)

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US5241642A (en) * 1989-09-28 1993-08-31 Pixel Semiconductor, Inc. Image memory controller for controlling multiple memories and method of operation
US5483646A (en) * 1989-09-29 1996-01-09 Kabushiki Kaisha Toshiba Memory access control method and system for realizing the same
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US6240496B1 (en) * 1989-11-24 2001-05-29 Hyundai Electronics America Architecture and configuring method for a computer expansion board
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JP3110035B2 (ja) * 1990-06-07 2000-11-20 株式会社東芝 携帯可能電子装置
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US5269010A (en) * 1990-08-31 1993-12-07 Advanced Micro Devices, Inc. Memory control for use in a memory system incorporating a plurality of memory banks
US5241665A (en) * 1990-08-31 1993-08-31 Advanced Micro Devices, Inc. Memory bank comparator system
EP0500915B1 (de) * 1990-09-17 2000-02-02 Samsung Semiconductor, Inc. Verfahren zum Konfigurieren eines Speichersystems
US5530934A (en) * 1991-02-02 1996-06-25 Vlsi Technology, Inc. Dynamic memory address line decoding
US5448710A (en) * 1991-02-26 1995-09-05 Hewlett-Packard Company Dynamically configurable interface cards with variable memory size
US5551012A (en) * 1991-04-22 1996-08-27 Acer Incorporated Single socket upgradeable computer motherboard with automatic detection and socket reconfiguration for inserted CPU chip
US5761479A (en) * 1991-04-22 1998-06-02 Acer Incorporated Upgradeable/downgradeable central processing unit chip computer systems
EP0510241A3 (en) * 1991-04-22 1993-01-13 Acer Incorporated Upgradeable/downgradeable computer
US5428758A (en) * 1991-05-10 1995-06-27 Unisys Corporation Method and system for remapping memory from one physical configuration to another physical configuration
EP0525308A1 (de) * 1991-07-31 1993-02-03 International Business Machines Corporation Speicherabbildung für einen Prozessor-Cache-Speicher
JPH0546447A (ja) * 1991-08-08 1993-02-26 Hitachi Ltd 空き領域検索方法
EP0529142A1 (de) * 1991-08-30 1993-03-03 Acer Incorporated Ausbaubare und abbaubare Rechner
US5586303A (en) * 1992-02-12 1996-12-17 Integrated Device Technology, Inc. Structure and method for providing a cache memory of selectable sizes
TW390446U (en) * 1992-10-01 2000-05-11 Hudson Soft Co Ltd Information processing system
CA2116985C (en) * 1993-03-11 1999-09-21 Cynthia J. Burns Memory system
US5603055A (en) * 1994-01-27 1997-02-11 Vlsi Technology, Inc. Single shared ROM for storing keyboard microcontroller code portion and CPU code portion and disabling access to a portion while accessing to the other
US5721860A (en) * 1994-05-24 1998-02-24 Intel Corporation Memory controller for independently supporting synchronous and asynchronous DRAM memories
US6360285B1 (en) 1994-06-30 2002-03-19 Compaq Computer Corporation Apparatus for determining memory bank availability in a computer system
US5530836A (en) * 1994-08-12 1996-06-25 International Business Machines Corporation Method and apparatus for multiple memory bank selection
US5809224A (en) * 1995-10-13 1998-09-15 Compaq Computer Corporation On-line disk array reconfiguration
US5809555A (en) * 1995-12-15 1998-09-15 Compaq Computer Corporation Method of determining sizes of 1:1 and 2:1 memory interleaving in a computer system, configuring to the maximum size, and informing the user if memory is incorrectly installed
US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US6567904B1 (en) 1995-12-29 2003-05-20 Intel Corporation Method and apparatus for automatically detecting whether a memory unit location is unpopulated or populated with synchronous or asynchronous memory devices
DE59610672D1 (de) * 1995-12-29 2003-09-25 Siemens Ag Verfahren und Anordnung zum Konvertieren von Speicheradressen in Speicheransteuersignale
US6334175B1 (en) * 1998-07-22 2001-12-25 Ati Technologies, Inc. Switchable memory system and memory allocation method
US6567950B1 (en) 1999-04-30 2003-05-20 International Business Machines Corporation Dynamically replacing a failed chip
JP3498021B2 (ja) 1999-10-07 2004-02-16 エヌイーシーコンピュータテクノ株式会社 メモリ制御方式
US7065531B2 (en) * 2002-03-12 2006-06-20 Hewlett-Packard Development Company, L.P. Combining computer programs
US6981122B2 (en) * 2002-09-26 2005-12-27 Analog Devices, Inc. Method and system for providing a contiguous memory address space
DE602004005806T2 (de) * 2003-12-12 2008-01-10 Stmicroelectronics S.A. Serieller Speicher mit Mitteln zur Integration eines erweiterten Speicherfeldes
US7366819B2 (en) 2004-02-11 2008-04-29 Infineon Technologies Ag Fast unaligned cache access system and method
US7296134B2 (en) * 2004-02-11 2007-11-13 Infineon Technologies Ag Fast unaligned memory access system and method
EP2701077A1 (de) * 2012-08-24 2014-02-26 Software AG Verfahren und System zum Speichern von tabellenförmigen Daten auf speicherwirksame Weise
KR102369402B1 (ko) * 2017-09-20 2022-03-02 삼성전자주식회사 스토리지 장치, 이의 동작 방법 및 스토리지 장치를 포함하는 스토리지 시스템
CN110298824A (zh) * 2019-06-17 2019-10-01 浙江省农业科学院 基于彩色图像和卷积神经网络技术的鱿鱼自动分类方法

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US3813652A (en) * 1973-01-15 1974-05-28 Honeywell Inf Systems Memory address transformation system
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US4234934A (en) * 1978-11-30 1980-11-18 Sperry Rand Corporation Apparatus for scaling memory addresses
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CA1102007A (en) * 1979-05-15 1981-05-26 Prem L. Sood Duplicated memory system having status indication
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JPS60157646A (ja) * 1984-01-27 1985-08-17 Mitsubishi Electric Corp メモリバンク切換装置

Also Published As

Publication number Publication date
JPH065513B2 (ja) 1994-01-19
EP0285986B1 (de) 1994-08-03
EP0285986A3 (en) 1990-09-26
EP0285986A2 (de) 1988-10-12
BR8801568A (pt) 1988-11-08
JPS63250752A (ja) 1988-10-18
US4908789A (en) 1990-03-13
DE3850901T2 (de) 1995-03-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee