DE3780743T2 - Verfahren zum erzeugen von kontaktloechern durch siliziumnitrid und polyimid. - Google Patents

Verfahren zum erzeugen von kontaktloechern durch siliziumnitrid und polyimid.

Info

Publication number
DE3780743T2
DE3780743T2 DE8787113825T DE3780743T DE3780743T2 DE 3780743 T2 DE3780743 T2 DE 3780743T2 DE 8787113825 T DE8787113825 T DE 8787113825T DE 3780743 T DE3780743 T DE 3780743T DE 3780743 T2 DE3780743 T2 DE 3780743T2
Authority
DE
Germany
Prior art keywords
polyimide
silicon nitride
contact holes
producing contact
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787113825T
Other languages
English (en)
Other versions
DE3780743D1 (de
Inventor
Madan Mohan Nanda
Steven Louis Peterman
David Stanasolovich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3780743D1 publication Critical patent/DE3780743D1/de
Publication of DE3780743T2 publication Critical patent/DE3780743T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
DE8787113825T 1986-10-09 1987-09-22 Verfahren zum erzeugen von kontaktloechern durch siliziumnitrid und polyimid. Expired - Fee Related DE3780743T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US91735086A 1986-10-09 1986-10-09

Publications (2)

Publication Number Publication Date
DE3780743D1 DE3780743D1 (de) 1992-09-03
DE3780743T2 true DE3780743T2 (de) 1993-03-11

Family

ID=25438667

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787113825T Expired - Fee Related DE3780743T2 (de) 1986-10-09 1987-09-22 Verfahren zum erzeugen von kontaktloechern durch siliziumnitrid und polyimid.

Country Status (4)

Country Link
US (1) US4978419A (de)
EP (1) EP0263348B1 (de)
JP (1) JPS63104425A (de)
DE (1) DE3780743T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0410420A (ja) * 1990-04-26 1992-01-14 Sanyo Electric Co Ltd 半導体集積回路の製造方法
FR2671909B1 (fr) * 1991-01-17 1999-01-22 Alcatel Nv Procede de lithogravure sur saillie notamment sur substrat semiconducteur.
US5245213A (en) * 1991-10-10 1993-09-14 Sgs-Thomson Microelectronics, Inc. Planarized semiconductor product
KR940008323B1 (ko) * 1991-10-16 1994-09-12 삼성전자 주식회사 반도체장치의 층간접속방법
US5266530A (en) * 1991-11-08 1993-11-30 Bell Communications Research, Inc. Self-aligned gated electron field emitter
JPH05234965A (ja) * 1992-02-21 1993-09-10 Sony Corp コンタクトホールの形成方法
US5543335A (en) * 1993-05-05 1996-08-06 Ixys Corporation Advanced power device process for low drop
GB2279804A (en) * 1993-07-02 1995-01-11 Plessey Semiconductors Ltd Insulating layers for multilayer wiring
US5747375A (en) * 1993-07-22 1998-05-05 Sanyo Electric Co., Ltd. Method of manufacturing a semiconductor integrated circuit device
GB9414362D0 (en) * 1994-07-15 1994-09-07 Plessey Semiconductors Ltd Trimmable capacitor
KR0179838B1 (ko) * 1995-09-02 1999-04-15 문정환 반도체 소자의 절연막 구조 및 절연막 평탄화 방법
JPH09306901A (ja) * 1996-05-17 1997-11-28 Nec Corp 半導体装置の製造方法
KR100226749B1 (ko) * 1997-04-24 1999-10-15 구본준 반도체 소자의 제조 방법
US5976987A (en) * 1997-10-03 1999-11-02 Vlsi Technology, Inc. In-situ corner rounding during oxide etch for improved plug fill
US6557253B1 (en) 1998-02-09 2003-05-06 Tessera, Inc. Method of making components with releasable leads
US6965165B2 (en) * 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
JP3387478B2 (ja) * 1999-06-30 2003-03-17 セイコーエプソン株式会社 半導体装置およびその製造方法
JP3847068B2 (ja) * 2000-09-11 2006-11-15 アルプス電気株式会社 薄膜磁気ヘッド及びその製造方法
EP1393131A4 (de) * 2001-05-11 2006-08-09 Shipley Co Llc Dickfilm-fotoresists und verfahren zu ihrer verwendung
US6645848B2 (en) 2001-06-01 2003-11-11 Emcore Corporation Method of improving the fabrication of etched semiconductor devices
US7547635B2 (en) * 2002-06-14 2009-06-16 Lam Research Corporation Process for etching dielectric films with improved resist and/or etch profile characteristics
US20040171260A1 (en) * 2002-06-14 2004-09-02 Lam Research Corporation Line edge roughness control
DE10241990B4 (de) * 2002-09-11 2006-11-09 Infineon Technologies Ag Verfahren zur Strukturierung von Schichten auf Halbleiterbauelementen
JP2008300557A (ja) * 2007-05-30 2008-12-11 Mitsubishi Electric Corp 半導体装置
US8039356B2 (en) * 2010-01-20 2011-10-18 International Business Machines Corporation Through silicon via lithographic alignment and registration

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4367119A (en) * 1980-08-18 1983-01-04 International Business Machines Corporation Planar multi-level metal process with built-in etch stop
DE3175488D1 (en) * 1981-02-07 1986-11-20 Ibm Deutschland Process for the formation and the filling of holes in a layer applied to a substrate
US4423547A (en) * 1981-06-01 1984-01-03 International Business Machines Corporation Method for forming dense multilevel interconnection metallurgy for semiconductor devices
JPS58140139A (ja) * 1982-02-16 1983-08-19 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US4447290A (en) * 1982-06-10 1984-05-08 Intel Corporation CMOS Process with unique plasma etching step
JPS59149025A (ja) * 1983-02-16 1984-08-25 Hitachi Ltd 半導体装置の製造法
US4497684A (en) * 1983-02-22 1985-02-05 Amdahl Corporation Lift-off process for depositing metal on a substrate
JPS59214240A (ja) * 1983-05-09 1984-12-04 Fujitsu Ltd 半導体装置の製造方法
JPS601846A (ja) * 1983-06-18 1985-01-08 Toshiba Corp 多層配線構造の半導体装置とその製造方法
US4430153A (en) * 1983-06-30 1984-02-07 International Business Machines Corporation Method of forming an RIE etch barrier by in situ conversion of a silicon containing alkyl polyamide/polyimide
US4495220A (en) * 1983-10-07 1985-01-22 Trw Inc. Polyimide inter-metal dielectric process
US4487652A (en) * 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US4519872A (en) * 1984-06-11 1985-05-28 International Business Machines Corporation Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes
US4523976A (en) * 1984-07-02 1985-06-18 Motorola, Inc. Method for forming semiconductor devices
JPS6237945A (ja) * 1985-08-13 1987-02-18 Toshiba Corp 半導体装置の製造方法
US4758306A (en) * 1987-08-17 1988-07-19 International Business Machines Corporation Stud formation method optimizing insulator gap-fill and metal hole-fill

Also Published As

Publication number Publication date
EP0263348A2 (de) 1988-04-13
EP0263348A3 (en) 1988-10-05
JPS63104425A (ja) 1988-05-09
US4978419A (en) 1990-12-18
DE3780743D1 (de) 1992-09-03
EP0263348B1 (de) 1992-07-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee