DE3774808D1 - Halbleiteranordnung mit einer eine verbesserte wasserbestaendigkeit aufweisenden siliziumoxynitridschicht. - Google Patents
Halbleiteranordnung mit einer eine verbesserte wasserbestaendigkeit aufweisenden siliziumoxynitridschicht.Info
- Publication number
- DE3774808D1 DE3774808D1 DE8787113101T DE3774808T DE3774808D1 DE 3774808 D1 DE3774808 D1 DE 3774808D1 DE 8787113101 T DE8787113101 T DE 8787113101T DE 3774808 T DE3774808 T DE 3774808T DE 3774808 D1 DE3774808 D1 DE 3774808D1
- Authority
- DE
- Germany
- Prior art keywords
- water resistance
- silicon oxynitride
- oxynitride layer
- improved water
- semiconductor arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21235886 | 1986-09-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3774808D1 true DE3774808D1 (de) | 1992-01-09 |
Family
ID=16621222
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8787113101T Expired - Fee Related DE3774808D1 (de) | 1986-09-08 | 1987-09-08 | Halbleiteranordnung mit einer eine verbesserte wasserbestaendigkeit aufweisenden siliziumoxynitridschicht. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4907064A (de) |
EP (1) | EP0259826B1 (de) |
JP (1) | JPS63184340A (de) |
KR (1) | KR910001779B1 (de) |
DE (1) | DE3774808D1 (de) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4717631A (en) * | 1986-01-16 | 1988-01-05 | Rca Corporation | Silicon oxynitride passivated semiconductor body and method of making same |
US5528058A (en) * | 1986-03-21 | 1996-06-18 | Advanced Power Technology, Inc. | IGBT device with platinum lifetime control and reduced gaw |
US5164339A (en) * | 1988-09-30 | 1992-11-17 | Siemens-Bendix Automotive Electronics L.P. | Fabrication of oxynitride frontside microstructures |
US5107323A (en) * | 1988-12-22 | 1992-04-21 | At&T Bell Laboratories | Protective layer for high voltage devices |
US5614756A (en) * | 1990-04-12 | 1997-03-25 | Actel Corporation | Metal-to-metal antifuse with conductive |
US5646439A (en) * | 1992-05-13 | 1997-07-08 | Matsushita Electric Industrial Co., Ltd. | Electronic chip component with passivation film and organic protective film |
US5365104A (en) * | 1993-03-25 | 1994-11-15 | Paradigm Technology, Inc. | Oxynitride fuse protective/passivation film for integrated circuit having resistors |
US5397720A (en) * | 1994-01-07 | 1995-03-14 | The Regents Of The University Of Texas System | Method of making MOS transistor having improved oxynitride dielectric |
US5478765A (en) * | 1994-05-04 | 1995-12-26 | Regents Of The University Of Texas System | Method of making an ultra thin dielectric for electronic devices |
US5789764A (en) * | 1995-04-14 | 1998-08-04 | Actel Corporation | Antifuse with improved antifuse material |
CA2213034C (en) * | 1996-09-02 | 2002-12-17 | Murata Manufacturing Co., Ltd. | A semiconductor device with a passivation film |
US5939763A (en) * | 1996-09-05 | 1999-08-17 | Advanced Micro Devices, Inc. | Ultrathin oxynitride structure and process for VLSI applications |
JPH10256539A (ja) * | 1997-03-10 | 1998-09-25 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5969382A (en) | 1997-11-03 | 1999-10-19 | Delco Electronics Corporation | EPROM in high density CMOS having added substrate diffusion |
US5972804A (en) * | 1997-08-05 | 1999-10-26 | Motorola, Inc. | Process for forming a semiconductor device |
US6235650B1 (en) * | 1997-12-29 | 2001-05-22 | Vanguard International Semiconductor Corporation | Method for improved semiconductor device reliability |
US5872063A (en) * | 1998-01-12 | 1999-02-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Self-aligned contact structures using high selectivity etching |
US7804115B2 (en) * | 1998-02-25 | 2010-09-28 | Micron Technology, Inc. | Semiconductor constructions having antireflective portions |
US6274292B1 (en) * | 1998-02-25 | 2001-08-14 | Micron Technology, Inc. | Semiconductor processing methods |
US6281100B1 (en) * | 1998-09-03 | 2001-08-28 | Micron Technology, Inc. | Semiconductor processing methods |
US6174743B1 (en) * | 1998-12-08 | 2001-01-16 | Advanced Micro Devices, Inc. | Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
US6221794B1 (en) * | 1998-12-08 | 2001-04-24 | Advanced Micro Devices, Inc. | Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines |
KR100300628B1 (ko) * | 1999-02-08 | 2001-09-26 | 윤종용 | 실리콘 옥시나이트라이드 보호층을 갖는 반도체 장치 및 그 제조 방법 |
US6174820B1 (en) | 1999-02-16 | 2001-01-16 | Sandia Corporation | Use of silicon oxynitride as a sacrificial material for microelectromechanical devices |
JP2000243831A (ja) * | 1999-02-18 | 2000-09-08 | Sony Corp | 半導体装置とその製造方法 |
US7067414B1 (en) * | 1999-09-01 | 2006-06-27 | Micron Technology, Inc. | Low k interlevel dielectric layer fabrication methods |
US6440860B1 (en) * | 2000-01-18 | 2002-08-27 | Micron Technology, Inc. | Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride |
US6670695B1 (en) * | 2000-02-29 | 2003-12-30 | United Microelectronics Corp. | Method of manufacturing anti-reflection layer |
US6562689B1 (en) * | 2000-04-14 | 2003-05-13 | Micron Technology, Inc. | Non-ion-implanted resistive silicon oxynitride films as resistors |
US6566186B1 (en) * | 2000-05-17 | 2003-05-20 | Lsi Logic Corporation | Capacitor with stoichiometrically adjusted dielectric and method of fabricating same |
US6548892B1 (en) * | 2000-08-31 | 2003-04-15 | Agere Systems Inc. | Low k dielectric insulator and method of forming semiconductor circuit structures |
JP2002100469A (ja) * | 2000-09-25 | 2002-04-05 | Pioneer Electronic Corp | 有機エレクトロルミネッセンス表示パネル |
US6509282B1 (en) * | 2001-11-26 | 2003-01-21 | Advanced Micro Devices, Inc. | Silicon-starved PECVD method for metal gate electrode dielectric spacer |
CN1577796A (zh) * | 2003-07-10 | 2005-02-09 | 精工爱普生株式会社 | 电子器件的制造方法和半导体器件的制造方法 |
JP5201831B2 (ja) * | 2006-12-25 | 2013-06-05 | ルネサスエレクトロニクス株式会社 | 膜の評価方法 |
DE202007001431U1 (de) * | 2007-01-31 | 2007-05-16 | Infineon Technologies Austria Ag | Halbleiteranordnung und Leistungshalbleiterbauelement |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1211354A (en) * | 1966-12-01 | 1970-11-04 | Gen Electric | Improvements relating to passivated semiconductor devices |
US3629088A (en) * | 1968-07-11 | 1971-12-21 | Sperry Rand Corp | Sputtering method for deposition of silicon oxynitride |
US4091406A (en) * | 1976-11-01 | 1978-05-23 | Rca Corporation | Combination glass/low temperature deposited Siw Nx Hy O.sub.z |
US4097889A (en) * | 1976-11-01 | 1978-06-27 | Rca Corporation | Combination glass/low temperature deposited Siw Nx Hy O.sub.z |
DE2967704D1 (de) * | 1978-06-14 | 1991-06-13 | Fujitsu Ltd | Verfahren zur herstellung einer halbleiteranordnung mit einer isolierschicht. |
JPS5642377A (en) * | 1979-09-14 | 1981-04-20 | Fujitsu Ltd | Ultraviolet ray erasable type rewritable read-only memory |
JPS58206129A (ja) * | 1982-05-27 | 1983-12-01 | Seiko Epson Corp | 半導体装置 |
JPS6195534A (ja) * | 1984-10-17 | 1986-05-14 | Hitachi Ltd | 半導体記憶装置 |
JPS62172733A (ja) * | 1986-01-16 | 1987-07-29 | ア−ルシ−エ− コ−ポレ−ション | 半導体基体 |
-
1987
- 1987-09-04 JP JP62222411A patent/JPS63184340A/ja active Pending
- 1987-09-08 EP EP87113101A patent/EP0259826B1/de not_active Expired - Lifetime
- 1987-09-08 DE DE8787113101T patent/DE3774808D1/de not_active Expired - Fee Related
- 1987-09-08 KR KR8709909A patent/KR910001779B1/ko not_active IP Right Cessation
- 1987-09-08 US US07/093,657 patent/US4907064A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0259826A1 (de) | 1988-03-16 |
US4907064A (en) | 1990-03-06 |
KR910001779B1 (ko) | 1991-03-23 |
KR880004558A (ko) | 1988-06-04 |
EP0259826B1 (de) | 1991-11-27 |
JPS63184340A (ja) | 1988-07-29 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8339 | Ceased/non-payment of the annual fee |