DE3773563D1 - Dynamisch rekonfigurierbare feldlogik. - Google Patents

Dynamisch rekonfigurierbare feldlogik.

Info

Publication number
DE3773563D1
DE3773563D1 DE8787305676T DE3773563T DE3773563D1 DE 3773563 D1 DE3773563 D1 DE 3773563D1 DE 8787305676 T DE8787305676 T DE 8787305676T DE 3773563 T DE3773563 T DE 3773563T DE 3773563 D1 DE3773563 D1 DE 3773563D1
Authority
DE
Germany
Prior art keywords
dynamically reconfigurable
field logic
reconfigurable field
logic
dynamically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787305676T
Other languages
English (en)
Inventor
Mathew W Henry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
Original Assignee
Honeywell Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Application granted granted Critical
Publication of DE3773563D1 publication Critical patent/DE3773563D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17752—Structural details of configuration resources for hot reconfiguration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
DE8787305676T 1986-07-18 1987-06-25 Dynamisch rekonfigurierbare feldlogik. Expired - Fee Related DE3773563D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/886,700 US4791603A (en) 1986-07-18 1986-07-18 Dynamically reconfigurable array logic

Publications (1)

Publication Number Publication Date
DE3773563D1 true DE3773563D1 (de) 1991-11-14

Family

ID=25389563

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787305676T Expired - Fee Related DE3773563D1 (de) 1986-07-18 1987-06-25 Dynamisch rekonfigurierbare feldlogik.

Country Status (4)

Country Link
US (1) US4791603A (de)
EP (1) EP0253530B1 (de)
JP (1) JPS6331220A (de)
DE (1) DE3773563D1 (de)

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US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
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Also Published As

Publication number Publication date
US4791603A (en) 1988-12-13
EP0253530A2 (de) 1988-01-20
EP0253530B1 (de) 1991-10-09
EP0253530A3 (en) 1989-03-08
JPS6331220A (ja) 1988-02-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee