DE3681112D1 - Plasmaaetzverfahren zur herstellung von metall-halbleiter-kontakte des ohmischen typs. - Google Patents

Plasmaaetzverfahren zur herstellung von metall-halbleiter-kontakte des ohmischen typs.

Info

Publication number
DE3681112D1
DE3681112D1 DE8686830254T DE3681112T DE3681112D1 DE 3681112 D1 DE3681112 D1 DE 3681112D1 DE 8686830254 T DE8686830254 T DE 8686830254T DE 3681112 T DE3681112 T DE 3681112T DE 3681112 D1 DE3681112 D1 DE 3681112D1
Authority
DE
Germany
Prior art keywords
plasma etching
etching method
producing metal
metal semiconductor
semiconductor contacts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686830254T
Other languages
English (en)
Inventor
Fabio Gualandris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE3681112D1 publication Critical patent/DE3681112D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
DE8686830254T 1985-10-14 1986-09-15 Plasmaaetzverfahren zur herstellung von metall-halbleiter-kontakte des ohmischen typs. Expired - Fee Related DE3681112D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT22468/85A IT1200785B (it) 1985-10-14 1985-10-14 Migliorato procedimento di attaco in plasma (rie) per realizzare contatti metallo-semiconduttore di tipo ohmico

Publications (1)

Publication Number Publication Date
DE3681112D1 true DE3681112D1 (de) 1991-10-02

Family

ID=11196692

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686830254T Expired - Fee Related DE3681112D1 (de) 1985-10-14 1986-09-15 Plasmaaetzverfahren zur herstellung von metall-halbleiter-kontakte des ohmischen typs.

Country Status (5)

Country Link
US (1) US4806199A (de)
EP (1) EP0219465B1 (de)
JP (1) JPH0821575B2 (de)
DE (1) DE3681112D1 (de)
IT (1) IT1200785B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1201840B (it) * 1986-08-28 1989-02-02 Sgs Microelettronica Spa Procedimento per realizzare contatti ohmici metallo-semiconduttore
JPH0770523B2 (ja) * 1987-05-19 1995-07-31 日本電気株式会社 半導体装置の製造方法
KR910008983B1 (ko) * 1988-12-20 1991-10-26 현대전자산업 주식회사 비등방성 식각을 이용한 잔유물 제거방법
US5034091A (en) * 1990-04-27 1991-07-23 Hughes Aircraft Company Method of forming an electrical via structure
JP3185150B2 (ja) * 1991-03-15 2001-07-09 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
US5312717A (en) * 1992-09-24 1994-05-17 International Business Machines Corporation Residue free vertical pattern transfer with top surface imaging resists
DE4339465C2 (de) * 1993-11-19 1997-05-28 Gold Star Electronics Verfahren zur Behandlung der Oberfläche eines einer Trockenätzung ausgesetzten Siliciumsubstrats
US5750441A (en) * 1996-05-20 1998-05-12 Micron Technology, Inc. Mask having a tapered profile used during the formation of a semiconductor device
US5893757A (en) * 1997-01-13 1999-04-13 Applied Komatsu Technology, Inc. Tapered profile etching method
US6117791A (en) 1998-06-22 2000-09-12 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US7173339B1 (en) 1998-06-22 2007-02-06 Micron Technology, Inc. Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure
US6875371B1 (en) 1998-06-22 2005-04-05 Micron Technology, Inc. Etchant with selectivity for doped silicon dioxide over undoped silicon dioxide and silicon nitride, processes which employ the etchant, and structures formed thereby
US6281142B1 (en) * 1999-06-04 2001-08-28 Micron Technology, Inc. Dielectric cure for reducing oxygen vacancies
JP4896367B2 (ja) * 2003-10-23 2012-03-14 パナソニック株式会社 電子部品の処理方法及び装置
WO2013092759A2 (en) * 2011-12-21 2013-06-27 Solvay Sa Method for etching of sio2 layers on thin wafers
CN103779271B (zh) * 2012-10-26 2017-04-05 中微半导体设备(上海)有限公司 一种倒锥形轮廓刻蚀方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4268374A (en) * 1979-08-09 1981-05-19 Bell Telephone Laboratories, Incorporated High capacity sputter-etching apparatus
EP0040081B1 (de) * 1980-05-12 1984-09-12 Fujitsu Limited Verfahren und Vorrichtung zum Plasma-Ätzen
JPS56158873A (en) * 1980-05-14 1981-12-07 Hitachi Ltd Dry etching method
DE3103177A1 (de) * 1981-01-30 1982-08-26 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von polysiliziumstrukturen bis in den 1 (my)m-bereich auf integrierte halbleiterschaltungen enthaltenden substraten durch plasmaaetzen
US4599243A (en) * 1982-12-23 1986-07-08 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks
US4534826A (en) * 1983-12-29 1985-08-13 Ibm Corporation Trench etch process for dielectric isolation
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4528066A (en) * 1984-07-06 1985-07-09 Ibm Corporation Selective anisotropic reactive ion etching process for polysilicide composite structures
US4582581A (en) * 1985-05-09 1986-04-15 Allied Corporation Boron trifluoride system for plasma etching of silicon dioxide
US4631248A (en) * 1985-06-21 1986-12-23 Lsi Logic Corporation Method for forming an electrical contact in an integrated circuit
US4687543A (en) * 1986-02-21 1987-08-18 Tegal Corporation Selective plasma etching during formation of integrated circuitry

Also Published As

Publication number Publication date
EP0219465A3 (en) 1988-03-30
EP0219465B1 (de) 1991-08-28
IT1200785B (it) 1989-01-27
IT8522468A0 (it) 1985-10-14
EP0219465A2 (de) 1987-04-22
JPS6289333A (ja) 1987-04-23
JPH0821575B2 (ja) 1996-03-04
US4806199A (en) 1989-02-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee