DE3671574D1 - Doppelschicht-photowiderstandstechnik fuer kontrollierte seitenwandkontur mittels plasmaaetzverfahren. - Google Patents
Doppelschicht-photowiderstandstechnik fuer kontrollierte seitenwandkontur mittels plasmaaetzverfahren.Info
- Publication number
- DE3671574D1 DE3671574D1 DE8686902253T DE3671574T DE3671574D1 DE 3671574 D1 DE3671574 D1 DE 3671574D1 DE 8686902253 T DE8686902253 T DE 8686902253T DE 3671574 T DE3671574 T DE 3671574T DE 3671574 D1 DE3671574 D1 DE 3671574D1
- Authority
- DE
- Germany
- Prior art keywords
- double
- side wall
- photo resistance
- plasma method
- controlled side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/728,012 US4645562A (en) | 1985-04-29 | 1985-04-29 | Double layer photoresist technique for side-wall profile control in plasma etching processes |
PCT/US1986/000649 WO1986006547A1 (en) | 1985-04-29 | 1986-03-31 | Double layer photoresist technique for side-wall profile control in plasma etching processes |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3671574D1 true DE3671574D1 (de) | 1990-06-28 |
Family
ID=24925070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686902253T Expired - Fee Related DE3671574D1 (de) | 1985-04-29 | 1986-03-31 | Doppelschicht-photowiderstandstechnik fuer kontrollierte seitenwandkontur mittels plasmaaetzverfahren. |
Country Status (7)
Country | Link |
---|---|
US (1) | US4645562A (de) |
EP (1) | EP0221093B1 (de) |
JP (1) | JPS63500411A (de) |
KR (1) | KR900002688B1 (de) |
DE (1) | DE3671574D1 (de) |
HK (1) | HK81190A (de) |
WO (1) | WO1986006547A1 (de) |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6218028A (ja) * | 1985-07-16 | 1987-01-27 | Toshiba Corp | デイスカム装置 |
US6087267A (en) * | 1986-03-04 | 2000-07-11 | Motorola, Inc. | Process for forming an integrated circuit |
JPS6318697A (ja) * | 1986-07-11 | 1988-01-26 | 日本電気株式会社 | 多層配線基板 |
JPS63258021A (ja) * | 1987-04-16 | 1988-10-25 | Toshiba Corp | 接続孔の形成方法 |
US5486449A (en) * | 1989-02-07 | 1996-01-23 | Rohm Co., Ltd. | Photomask, photoresist and photolithography for a monolithic IC |
US5034091A (en) * | 1990-04-27 | 1991-07-23 | Hughes Aircraft Company | Method of forming an electrical via structure |
DE4115414C2 (de) * | 1991-05-10 | 1995-07-06 | Meinhard Prof Dr Knoll | Verfahren zur Herstellung von miniaturisierten Chemo- und Biosensorelementen mit ionenselektiver Membran sowie von Trägern für diese Elemente |
JP3360461B2 (ja) * | 1995-01-31 | 2002-12-24 | ソニー株式会社 | メタル成膜工程の前処理方法 |
KR0172237B1 (ko) * | 1995-06-26 | 1999-03-30 | 김주용 | 반도체 소자의 미세패턴 형성방법 |
US5728627A (en) * | 1996-11-14 | 1998-03-17 | Samsung Electronics Co., Ltd. | Methods of forming planarized conductive interconnects for integrated circuits |
US5976987A (en) * | 1997-10-03 | 1999-11-02 | Vlsi Technology, Inc. | In-situ corner rounding during oxide etch for improved plug fill |
US6218310B1 (en) * | 1998-05-12 | 2001-04-17 | Advanced Micro Devices, Inc. | RTA methods for treating a deep-UV resist mask prior to gate formation etch to improve gate profile |
US6664194B1 (en) * | 1999-03-18 | 2003-12-16 | Taiwan Semiconductor Manufacturing Company | Photoexposure method for facilitating photoresist stripping |
US6320269B1 (en) * | 1999-05-03 | 2001-11-20 | Taiwan Semiconductor Manufacturing Company | Method for preparing a semiconductor wafer to receive a protective tape |
KR100356987B1 (ko) * | 2000-01-22 | 2002-10-18 | 엘지.필립스 엘시디 주식회사 | 열경화성 수지 제거용 조성물 |
US7078348B1 (en) * | 2001-06-27 | 2006-07-18 | Advanced Micro Devices, Inc. | Dual layer patterning scheme to make dual damascene |
US7384727B2 (en) * | 2003-06-26 | 2008-06-10 | Micron Technology, Inc. | Semiconductor processing patterning methods |
US6969677B2 (en) | 2003-10-20 | 2005-11-29 | Micron Technology, Inc. | Methods of forming conductive metal silicides by reaction of metal with silicon |
US7026243B2 (en) | 2003-10-20 | 2006-04-11 | Micron Technology, Inc. | Methods of forming conductive material silicides by reaction of metal with silicon |
US7361605B2 (en) * | 2004-01-20 | 2008-04-22 | Mattson Technology, Inc. | System and method for removal of photoresist and residues following contact etch with a stop layer present |
US7153769B2 (en) | 2004-04-08 | 2006-12-26 | Micron Technology, Inc. | Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon |
US7229745B2 (en) * | 2004-06-14 | 2007-06-12 | Bae Systems Information And Electronic Systems Integration Inc. | Lithographic semiconductor manufacturing using a multi-layered process |
US7241705B2 (en) * | 2004-09-01 | 2007-07-10 | Micron Technology, Inc. | Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects |
KR100640525B1 (ko) * | 2004-12-29 | 2006-10-31 | 동부일렉트로닉스 주식회사 | 반도체 소자의 금속 라인 형성 방법 |
KR100710187B1 (ko) * | 2005-11-24 | 2007-04-20 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조 방법 |
US20080160749A1 (en) * | 2006-12-27 | 2008-07-03 | Texas Instruments Incorporated | Semiconductor device and method of forming thereof |
US20090008430A1 (en) * | 2007-07-06 | 2009-01-08 | Lucent Technologies Inc. | Solder-bonding process |
CN101785088B (zh) * | 2007-08-08 | 2013-06-05 | 株式会社爱发科 | 等离子处理方法和等离子处理装置 |
US7755123B2 (en) * | 2007-08-24 | 2010-07-13 | Aptina Imaging Corporation | Apparatus, system, and method providing backside illuminated imaging device |
US20090072269A1 (en) * | 2007-09-17 | 2009-03-19 | Chang Soo Suh | Gallium nitride diodes and integrated components |
US7915643B2 (en) | 2007-09-17 | 2011-03-29 | Transphorm Inc. | Enhancement mode gallium nitride power devices |
US8519438B2 (en) | 2008-04-23 | 2013-08-27 | Transphorm Inc. | Enhancement mode III-N HEMTs |
US8289065B2 (en) | 2008-09-23 | 2012-10-16 | Transphorm Inc. | Inductive load power switching circuits |
US7898004B2 (en) | 2008-12-10 | 2011-03-01 | Transphorm Inc. | Semiconductor heterostructure diodes |
US8742459B2 (en) | 2009-05-14 | 2014-06-03 | Transphorm Inc. | High voltage III-nitride semiconductor devices |
US8390000B2 (en) | 2009-08-28 | 2013-03-05 | Transphorm Inc. | Semiconductor devices with field plates |
US8389977B2 (en) | 2009-12-10 | 2013-03-05 | Transphorm Inc. | Reverse side engineered III-nitride devices |
US8742460B2 (en) | 2010-12-15 | 2014-06-03 | Transphorm Inc. | Transistors with isolation regions |
US8643062B2 (en) | 2011-02-02 | 2014-02-04 | Transphorm Inc. | III-N device structures and methods |
US8716141B2 (en) | 2011-03-04 | 2014-05-06 | Transphorm Inc. | Electrode configurations for semiconductor devices |
US8772842B2 (en) | 2011-03-04 | 2014-07-08 | Transphorm, Inc. | Semiconductor diodes with low reverse bias currents |
US8901604B2 (en) | 2011-09-06 | 2014-12-02 | Transphorm Inc. | Semiconductor devices with guard rings |
US9257547B2 (en) | 2011-09-13 | 2016-02-09 | Transphorm Inc. | III-N device structures having a non-insulating substrate |
US8598937B2 (en) | 2011-10-07 | 2013-12-03 | Transphorm Inc. | High power semiconductor electronic components with increased reliability |
US9165766B2 (en) | 2012-02-03 | 2015-10-20 | Transphorm Inc. | Buffer layer structures suited for III-nitride devices with foreign substrates |
US9257279B2 (en) * | 2012-03-29 | 2016-02-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mask treatment for double patterning design |
WO2013155108A1 (en) | 2012-04-09 | 2013-10-17 | Transphorm Inc. | N-polar iii-nitride transistors |
US9184275B2 (en) | 2012-06-27 | 2015-11-10 | Transphorm Inc. | Semiconductor devices with integrated hole collectors |
CN103066095B (zh) * | 2013-01-14 | 2016-01-20 | 武汉新芯集成电路制造有限公司 | 一种影像传感器及其制造方法 |
WO2014127150A1 (en) | 2013-02-15 | 2014-08-21 | Transphorm Inc. | Electrodes for semiconductor devices and methods of forming the same |
US9087718B2 (en) | 2013-03-13 | 2015-07-21 | Transphorm Inc. | Enhancement-mode III-nitride devices |
US9245992B2 (en) | 2013-03-15 | 2016-01-26 | Transphorm Inc. | Carbon doping semiconductor devices |
WO2015009514A1 (en) | 2013-07-19 | 2015-01-22 | Transphorm Inc. | Iii-nitride transistor including a p-type depleting layer |
US9318593B2 (en) | 2014-07-21 | 2016-04-19 | Transphorm Inc. | Forming enhancement mode III-nitride devices |
US9536966B2 (en) | 2014-12-16 | 2017-01-03 | Transphorm Inc. | Gate structures for III-N devices |
US9536967B2 (en) | 2014-12-16 | 2017-01-03 | Transphorm Inc. | Recessed ohmic contacts in a III-N device |
US11322599B2 (en) | 2016-01-15 | 2022-05-03 | Transphorm Technology, Inc. | Enhancement mode III-nitride devices having an Al1-xSixO gate insulator |
US10224401B2 (en) | 2016-05-31 | 2019-03-05 | Transphorm Inc. | III-nitride devices including a graded depleting layer |
US11764062B2 (en) * | 2017-11-13 | 2023-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
US10157773B1 (en) * | 2017-11-28 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure having layer with re-entrant profile and method of forming the same |
US10927450B2 (en) * | 2018-12-19 | 2021-02-23 | Applied Materials, Inc. | Methods and apparatus for patterning substrates using asymmetric physical vapor deposition |
US11856877B2 (en) | 2019-12-23 | 2023-12-26 | The University Of Canterbury | Electrical contacts for nanoparticle networks |
CN113766412B (zh) * | 2021-11-05 | 2022-02-15 | 绍兴中芯集成电路制造股份有限公司 | 具有弧形底角的凹槽的制备方法、mems麦克风的制备方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS547871A (en) * | 1977-06-21 | 1979-01-20 | Toshiba Corp | Pattern forming method |
JPS5569264A (en) * | 1978-11-15 | 1980-05-24 | Toshiba Corp | Etching method |
JPS56114319A (en) * | 1980-02-14 | 1981-09-08 | Fujitsu Ltd | Method for forming contact hole |
JPS56130925A (en) * | 1980-03-17 | 1981-10-14 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
JPS5783034A (en) * | 1980-11-12 | 1982-05-24 | Toshiba Corp | Method for taper etching |
DE3215411A1 (de) * | 1982-04-24 | 1983-10-27 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verfahren zum herstellen von oeffnungen mit hilfe einer maske in einer auf einer unterlage befindlichen schicht |
US4461672A (en) * | 1982-11-18 | 1984-07-24 | Texas Instruments, Inc. | Process for etching tapered vias in silicon dioxide |
JPS59152628A (ja) * | 1983-02-21 | 1984-08-31 | Toshiba Corp | 半導体装置の製造方法 |
US4484978A (en) * | 1983-09-23 | 1984-11-27 | Fairchild Camera & Instrument Corp. | Etching method |
US4523976A (en) * | 1984-07-02 | 1985-06-18 | Motorola, Inc. | Method for forming semiconductor devices |
-
1985
- 1985-04-29 US US06/728,012 patent/US4645562A/en not_active Expired - Lifetime
-
1986
- 1986-03-31 JP JP61501985A patent/JPS63500411A/ja active Pending
- 1986-03-31 EP EP86902253A patent/EP0221093B1/de not_active Expired - Lifetime
- 1986-03-31 DE DE8686902253T patent/DE3671574D1/de not_active Expired - Fee Related
- 1986-03-31 KR KR1019860700936A patent/KR900002688B1/ko not_active IP Right Cessation
- 1986-03-31 WO PCT/US1986/000649 patent/WO1986006547A1/en active IP Right Grant
-
1990
- 1990-10-11 HK HK811/90A patent/HK81190A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
EP0221093A1 (de) | 1987-05-13 |
HK81190A (en) | 1990-10-19 |
US4645562A (en) | 1987-02-24 |
JPS63500411A (ja) | 1988-02-12 |
KR900002688B1 (ko) | 1990-04-23 |
WO1986006547A1 (en) | 1986-11-06 |
KR880700455A (ko) | 1988-03-15 |
EP0221093B1 (de) | 1990-05-23 |
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