DE3585496D1 - Verfahren zur adressierungsfehlererkennung in einem katalogisierten speicher und katalogisierter speicher unter verwendung eines solchen verfahrens. - Google Patents

Verfahren zur adressierungsfehlererkennung in einem katalogisierten speicher und katalogisierter speicher unter verwendung eines solchen verfahrens.

Info

Publication number
DE3585496D1
DE3585496D1 DE8585113093T DE3585496T DE3585496D1 DE 3585496 D1 DE3585496 D1 DE 3585496D1 DE 8585113093 T DE8585113093 T DE 8585113093T DE 3585496 T DE3585496 T DE 3585496T DE 3585496 D1 DE3585496 D1 DE 3585496D1
Authority
DE
Germany
Prior art keywords
storage
cache
catalogized
cataloged
addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585113093T
Other languages
English (en)
Inventor
Jerry Duane Dixon
Robert Henri Farrell
Gerald A Marazas
Mcneill, Jr
Gerald Ulrich Merckel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3585496D1 publication Critical patent/DE3585496D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
DE8585113093T 1984-11-02 1985-10-15 Verfahren zur adressierungsfehlererkennung in einem katalogisierten speicher und katalogisierter speicher unter verwendung eines solchen verfahrens. Expired - Fee Related DE3585496D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/667,520 US4637024A (en) 1984-11-02 1984-11-02 Redundant page identification for a catalogued memory

Publications (1)

Publication Number Publication Date
DE3585496D1 true DE3585496D1 (de) 1992-04-09

Family

ID=24678548

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585113093T Expired - Fee Related DE3585496D1 (de) 1984-11-02 1985-10-15 Verfahren zur adressierungsfehlererkennung in einem katalogisierten speicher und katalogisierter speicher unter verwendung eines solchen verfahrens.

Country Status (5)

Country Link
US (1) US4637024A (de)
EP (1) EP0180821B1 (de)
JP (1) JPS61114356A (de)
CA (1) CA1228674A (de)
DE (1) DE3585496D1 (de)

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CA1241768A (en) * 1984-06-22 1988-09-06 Miyuki Ishida Tag control circuit for buffer storage
US4972316A (en) * 1987-03-30 1990-11-20 International Business Machines Corporation Method of handling disk sector errors in DASD cache
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
US6092153A (en) * 1988-11-14 2000-07-18 Lass; Stanley Edwin Subsettable top level cache
US5329629A (en) * 1989-07-03 1994-07-12 Tandem Computers Incorporated Apparatus and method for reading, writing, and refreshing memory with direct virtual or physical access
US5195100A (en) * 1990-03-02 1993-03-16 Micro Technology, Inc. Non-volatile memory storage of write operation identifier in data sotrage device
US5233618A (en) * 1990-03-02 1993-08-03 Micro Technology, Inc. Data correcting applicable to redundant arrays of independent disks
US5138710A (en) * 1990-04-25 1992-08-11 Unisys Corporation Apparatus and method for providing recoverability in mass storage data base systems without audit trail mechanisms
US5317713A (en) * 1991-09-19 1994-05-31 Quantum Corporation Micro-winchester disk drive having on-board segmented cache memory
US5361345A (en) * 1991-09-19 1994-11-01 Hewlett-Packard Company Critical line first paging system
JP3181001B2 (ja) * 1993-06-01 2001-07-03 インターナショナル・ビジネス・マシーンズ・コーポレ−ション キャッシュ・メモリ・システム並びにキャッシュ・メモリ・アクセス方法及びシステム
JP3264465B2 (ja) * 1993-06-30 2002-03-11 株式会社日立製作所 記憶システム
US5586253A (en) * 1994-12-15 1996-12-17 Stratus Computer Method and apparatus for validating I/O addresses in a fault-tolerant computer system
US5649155A (en) * 1995-03-31 1997-07-15 International Business Machines Corporation Cache memory accessed by continuation requests
JP2928165B2 (ja) * 1996-08-16 1999-08-03 日本電気マイコンテクノロジー株式会社 Ａｔｍスイッチ
US5883904A (en) * 1997-04-14 1999-03-16 International Business Machines Corporation Method for recoverability via redundant cache arrays
US6098190A (en) * 1998-08-04 2000-08-01 Hewlett-Packard Co. Method and apparatus for use of a host address to validate accessed data
US6370614B1 (en) 1999-01-26 2002-04-09 Motive Power, Inc. I/O cache with user configurable preload
US6463509B1 (en) * 1999-01-26 2002-10-08 Motive Power, Inc. Preloading data in a cache memory according to user-specified preload criteria
US6862689B2 (en) 2001-04-12 2005-03-01 Stratus Technologies Bermuda Ltd. Method and apparatus for managing session information
US6802022B1 (en) 2000-04-14 2004-10-05 Stratus Technologies Bermuda Ltd. Maintenance of consistent, redundant mass storage images
US6928521B1 (en) 2000-08-01 2005-08-09 International Business Machines Corporation Method, system, and data structures for using metadata in updating data in a storage device
US6948010B2 (en) * 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US6766413B2 (en) 2001-03-01 2004-07-20 Stratus Technologies Bermuda Ltd. Systems and methods for caching with file-level granularity
US6874102B2 (en) * 2001-03-05 2005-03-29 Stratus Technologies Bermuda Ltd. Coordinated recalibration of high bandwidth memories in a multiprocessor computer
JP4374834B2 (ja) * 2002-08-12 2009-12-02 セイコーエプソン株式会社 カートリッジおよび記録装置
DE10327549A1 (de) * 2003-06-18 2005-01-13 Robert Bosch Gmbh Verfahren und Vorrichtung zur Fehlererkennung für einen Cachespeicher und entsprechender Cachespeicher
US20060222126A1 (en) * 2005-03-31 2006-10-05 Stratus Technologies Bermuda Ltd. Systems and methods for maintaining synchronicity during signal transmission
US20060222125A1 (en) * 2005-03-31 2006-10-05 Edwards John W Jr Systems and methods for maintaining synchronicity during signal transmission
US7523319B2 (en) * 2005-11-16 2009-04-21 Lenovo (Singapore) Pte. Ltd. System and method for tracking changed LBAs on disk drive

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3840862A (en) * 1973-09-27 1974-10-08 Honeywell Inf Systems Status indicator apparatus for tag directory in associative stores
US3896419A (en) * 1974-01-17 1975-07-22 Honeywell Inf Systems Cache memory store in a processor of a data processing system
FR2315744A1 (fr) * 1975-06-27 1977-01-21 Telemecanique Electrique Dispositif auxiliaire d'adressage virtuel
US3976865A (en) * 1975-08-15 1976-08-24 International Business Machines Corporation Error detector for an associative directory or translator
US4084236A (en) * 1977-02-18 1978-04-11 Honeywell Information Systems Inc. Error detection and correction capability for a memory system
US4357656A (en) * 1977-12-09 1982-11-02 Digital Equipment Corporation Method and apparatus for disabling and diagnosing cache memory storage locations
US4190885A (en) * 1977-12-22 1980-02-26 Honeywell Information Systems Inc. Out of store indicator for a cache store in test mode
US4197580A (en) * 1978-06-08 1980-04-08 Bell Telephone Laboratories, Incorporated Data processing system including a cache memory
US4225922A (en) * 1978-12-11 1980-09-30 Honeywell Information Systems Inc. Command queue apparatus included within a cache unit for facilitating command sequencing
US4490782A (en) * 1981-06-05 1984-12-25 International Business Machines Corporation I/O Storage controller cache system with prefetch determined by requested record's position within data block
US4476526A (en) * 1981-11-27 1984-10-09 Storage Technology Corporation Cache buffered memory subsystem

Also Published As

Publication number Publication date
EP0180821B1 (de) 1992-03-04
EP0180821A3 (en) 1988-08-10
CA1228674A (en) 1987-10-27
US4637024A (en) 1987-01-13
JPS61114356A (ja) 1986-06-02
JPH0337218B2 (de) 1991-06-04
EP0180821A2 (de) 1986-05-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee