DE3484218D1 - Interface-schaltung und verfahren zum verbinden einer speichersteuereinrichtung mit einem synchronen oder asynchronen bussystem. - Google Patents

Interface-schaltung und verfahren zum verbinden einer speichersteuereinrichtung mit einem synchronen oder asynchronen bussystem.

Info

Publication number
DE3484218D1
DE3484218D1 DE8484110754T DE3484218T DE3484218D1 DE 3484218 D1 DE3484218 D1 DE 3484218D1 DE 8484110754 T DE8484110754 T DE 8484110754T DE 3484218 T DE3484218 T DE 3484218T DE 3484218 D1 DE3484218 D1 DE 3484218D1
Authority
DE
Germany
Prior art keywords
synchronous
control unit
interface circuit
memory control
bus system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484110754T
Other languages
English (en)
Inventor
David Ernest Finlay
Kent Steven Norgren
Frankie Sherwood Shook
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3484218D1 publication Critical patent/DE3484218D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
DE8484110754T 1983-09-19 1984-09-10 Interface-schaltung und verfahren zum verbinden einer speichersteuereinrichtung mit einem synchronen oder asynchronen bussystem. Expired - Fee Related DE3484218D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/533,397 US4615017A (en) 1983-09-19 1983-09-19 Memory controller with synchronous or asynchronous interface

Publications (1)

Publication Number Publication Date
DE3484218D1 true DE3484218D1 (de) 1991-04-11

Family

ID=24125779

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484110754T Expired - Fee Related DE3484218D1 (de) 1983-09-19 1984-09-10 Interface-schaltung und verfahren zum verbinden einer speichersteuereinrichtung mit einem synchronen oder asynchronen bussystem.

Country Status (4)

Country Link
US (1) US4615017A (de)
EP (1) EP0135879B1 (de)
JP (1) JPH0630087B2 (de)
DE (1) DE3484218D1 (de)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0658656B2 (ja) * 1984-09-17 1994-08-03 富士通株式会社 データ転送システム
NL8502642A (nl) * 1985-09-27 1986-04-01 Oce Nederland Bv Raster-beeld-processor.
JP2634583B2 (ja) * 1985-12-13 1997-07-30 株式会社日立製作所 データ転送方法
WO1988002888A1 (en) * 1986-10-17 1988-04-21 Fujitsu Limited Data transfer system having transfer discrimination circuit
US4785469A (en) * 1987-02-12 1988-11-15 Advanced Micro Devices, Inc. Processor to peripheral interface for asynchronous or synchronous applications
US5063536A (en) * 1988-03-11 1991-11-05 Washington State University Research Foundation, Inc. Microprogrammable asynchronous controllers for digital electronic systems
EP0335502A3 (de) * 1988-03-30 1991-07-03 Advanced Micro Devices, Inc. Mikrosteuereinheit und Verfahren dafür
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
GB2226666B (en) * 1988-12-30 1993-07-07 Intel Corp Request/response protocol
CA2011518C (en) * 1989-04-25 1993-04-20 Ronald N. Fortino Distributed cache dram chip and control method
US5187779A (en) * 1989-08-11 1993-02-16 Micral, Inc. Memory controller with synchronous processor bus and asynchronous i/o bus interfaces
US5218686A (en) * 1989-11-03 1993-06-08 Compaq Computer Corporation Combined synchronous and asynchronous memory controller
US5263150A (en) * 1990-04-20 1993-11-16 Chai I Fan Computer system employing asynchronous computer network through common memory
CA2044022A1 (en) * 1990-06-28 1991-12-29 Miriam A. Nihart Common agent computer management system and method
US5214774A (en) * 1990-07-30 1993-05-25 Motorola, Inc. Segmented memory transfer and message priority on synchronous/asynchronous data bus
US5128970A (en) * 1990-12-20 1992-07-07 Unisys Corporation Non-return to zero synchronizer
EP0913777B1 (de) * 1991-03-01 2005-05-11 Advanced Micro Devices, Inc. Ausgangspuffer für Mikroprozessor
US5481707A (en) * 1991-05-19 1996-01-02 Unisys Corporation Dedicated processor for task I/O and memory management
US5265216A (en) * 1991-06-28 1993-11-23 Digital Equipment Corporation High performance asynchronous bus interface
US5210856A (en) * 1991-08-07 1993-05-11 Chips And Technologies, Inc. Non-aligned DRAM state machine for page-mode DRAM control
US5576554A (en) * 1991-11-05 1996-11-19 Monolithic System Technology, Inc. Wafer-scale integrated circuit interconnect structure architecture
US5831467A (en) * 1991-11-05 1998-11-03 Monolithic System Technology, Inc. Termination circuit with power-down mode for use in circuit module architecture
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
DE69226150T2 (de) * 1991-11-05 1999-02-18 Hsu Fu Chieh Redundanzarchitektur für Schaltungsmodul
JPH05324546A (ja) * 1992-05-18 1993-12-07 Canon Inc 情報処理システム
WO1994003901A1 (en) 1992-08-10 1994-02-17 Monolithic System Technology, Inc. Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
US5388225A (en) * 1992-09-16 1995-02-07 Texas Instruments Incorporated Time-domain boundary bridge method and apparatus for asynchronous sequential machines
US5339395A (en) * 1992-09-17 1994-08-16 Delco Electronics Corporation Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode
US5414857A (en) * 1992-10-02 1995-05-09 Ast Research, Inc. Adaptive processor interface operable with different types of processors
US5592685A (en) * 1992-10-07 1997-01-07 Digital Equipment Corporation Synchronous/asynchronous partitioning of an asynchronous bus interface
CA2118662C (en) * 1993-03-22 1999-07-13 Paul A. Santeler Memory controller having all dram address and control signals provided synchronously from a single device
GB9317436D0 (en) * 1993-08-03 1993-10-06 Plessey Telecomm Telecommunications system
US5657482A (en) * 1993-08-24 1997-08-12 Micron Electronics, Inc. Automatic clock speed sensing system for determining the number of states needed for a time-dependent operation by sensing clock frequency
US5581793A (en) * 1993-08-24 1996-12-03 Micron Electronics, Inc. System for bypassing setup states in a bus operation
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5740382A (en) * 1996-03-28 1998-04-14 Motorola, Inc. Method and apparatus for accessing a chip-selectable device in a data processing system
US6047361A (en) * 1996-08-21 2000-04-04 International Business Machines Corporation Memory control device, with a common synchronous interface coupled thereto, for accessing asynchronous memory devices and different synchronous devices
US6128689A (en) * 1997-04-14 2000-10-03 Hms Fieldbus Systems Ab System for exchanging data through data memory area of common memory in synchronous and asynchronous modes
JP2002109881A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体集積回路
US6658544B2 (en) 2000-12-27 2003-12-02 Koninklijke Philips Electronics N.V. Techniques to asynchronously operate a synchronous memory
US7007186B1 (en) * 2002-02-11 2006-02-28 Adaptec Corporation Systems and methods for synchronizing a signal across multiple clock domains in an integrated circuit
US7330991B2 (en) * 2003-05-15 2008-02-12 Lsi Logic Corporation Method and/or apparatus for paging to a dynamic memory array
JP4114749B2 (ja) * 2003-11-07 2008-07-09 ローム株式会社 メモリ制御装置および電子装置
US8411695B1 (en) * 2005-05-23 2013-04-02 Juniper Networks, Inc. Multi-interface compatible bus over a common physical connection
JP4267002B2 (ja) * 2006-06-08 2009-05-27 エルピーダメモリ株式会社 コントローラ及びメモリを備えるシステム
US8266405B2 (en) 2006-12-13 2012-09-11 Cypress Semiconductor Corporation Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain
JP4367528B2 (ja) * 2007-05-25 2009-11-18 トヨタ自動車株式会社 シリアル通信装置
US9122553B2 (en) * 2007-12-01 2015-09-01 Sony Corporation Synchronous bus download of TV software update
US11132307B2 (en) 2018-05-25 2021-09-28 Rambus Inc. Low latency memory access

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3848233A (en) * 1971-11-01 1974-11-12 Bunker Ramo Method and apparatus for interfacing with a central processing unit
JPS529338B2 (de) * 1972-05-17 1977-03-15
US3999163A (en) * 1974-01-10 1976-12-21 Digital Equipment Corporation Secondary storage facility for data processing systems
US4007448A (en) * 1974-08-15 1977-02-08 Digital Equipment Corporation Drive for connection to multiple controllers in a digital data secondary storage facility
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system
US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
JPS5476034A (en) * 1977-11-30 1979-06-18 Fujitsu Ltd Bus data transfer system
US4321665A (en) * 1979-01-31 1982-03-23 Honeywell Information Systems Inc. Data processing system having centralized data alignment for I/O controllers
US4300194A (en) * 1979-01-31 1981-11-10 Honeywell Information Systems Inc. Data processing system having multiple common buses
US4319323A (en) * 1980-04-04 1982-03-09 Digital Equipment Corporation Communications device for data processing system
US4379327A (en) * 1980-07-21 1983-04-05 Motorola, Inc. Universal interface circuit for synchronous and asynchronous buses

Also Published As

Publication number Publication date
JPS6073774A (ja) 1985-04-25
US4615017A (en) 1986-09-30
EP0135879A2 (de) 1985-04-03
EP0135879B1 (de) 1991-03-06
JPH0630087B2 (ja) 1994-04-20
EP0135879A3 (en) 1988-03-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee