DE3483166D1 - Mehrstufiges steuergeraet fuer eine cachespeicherschnittstelle in einem mehrprozessorsystem. - Google Patents

Mehrstufiges steuergeraet fuer eine cachespeicherschnittstelle in einem mehrprozessorsystem.

Info

Publication number
DE3483166D1
DE3483166D1 DE8484301838T DE3483166T DE3483166D1 DE 3483166 D1 DE3483166 D1 DE 3483166D1 DE 8484301838 T DE8484301838 T DE 8484301838T DE 3483166 T DE3483166 T DE 3483166T DE 3483166 D1 DE3483166 D1 DE 3483166D1
Authority
DE
Germany
Prior art keywords
control unit
multiprocessor system
storage interface
stage control
cache storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484301838T
Other languages
English (en)
Inventor
Thomas Michael Steckler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Unisys Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisys Corp filed Critical Unisys Corp
Application granted granted Critical
Publication of DE3483166D1 publication Critical patent/DE3483166D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
DE8484301838T 1983-04-05 1984-03-19 Mehrstufiges steuergeraet fuer eine cachespeicherschnittstelle in einem mehrprozessorsystem. Expired - Fee Related DE3483166D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/482,237 US4586133A (en) 1983-04-05 1983-04-05 Multilevel controller for a cache memory interface in a multiprocessing system

Publications (1)

Publication Number Publication Date
DE3483166D1 true DE3483166D1 (de) 1990-10-18

Family

ID=23915279

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484301838T Expired - Fee Related DE3483166D1 (de) 1983-04-05 1984-03-19 Mehrstufiges steuergeraet fuer eine cachespeicherschnittstelle in einem mehrprozessorsystem.

Country Status (5)

Country Link
US (1) US4586133A (de)
EP (1) EP0121373B1 (de)
JP (1) JPH0630060B2 (de)
CA (1) CA1218162A (de)
DE (1) DE3483166D1 (de)

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BR8406089A (pt) * 1983-11-30 1985-09-24 Fujitsu Ltd Processo para controlar memoria intermediaria em aparelho de processamento de dados
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4802086A (en) * 1987-01-09 1989-01-31 Motorola, Inc. FINUFO cache replacement method and apparatus
US4851993A (en) * 1987-04-20 1989-07-25 Amdahl Corporation Cache move-in bypass
US4839793A (en) * 1987-07-01 1989-06-13 Baytec, Inc. Multiple computer interface
JPS6484361A (en) * 1987-07-30 1989-03-29 Araianto Computer Syst Corp Parallel processing computer with alterable preference of memory access
US5008816A (en) * 1987-11-06 1991-04-16 International Business Machines Corporation Data processing system with multi-access memory
US4912631A (en) * 1987-12-16 1990-03-27 Intel Corporation Burst mode cache with wrap-around fill
US5032985A (en) * 1988-07-21 1991-07-16 International Business Machines Corporation Multiprocessor system with memory fetch buffer invoked during cross-interrogation
EP0377970B1 (de) * 1989-01-13 1995-08-16 International Business Machines Corporation Ein-/Ausgabecachespeicherung
US5202973A (en) * 1990-06-29 1993-04-13 Digital Equipment Corporation Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
US5291442A (en) * 1990-10-31 1994-03-01 International Business Machines Corporation Method and apparatus for dynamic cache line sectoring in multiprocessor systems
US5813030A (en) * 1991-12-31 1998-09-22 Compaq Computer Corp. Cache memory system with simultaneous access of cache and main memories
CA2086386C (en) * 1991-12-31 1997-04-29 Daniel F. Daly Interface chip for a voice processing system
US5749090A (en) * 1994-08-22 1998-05-05 Motorola, Inc. Cache tag RAM having separate valid bit array with multiple step invalidation and method therefor
US5875462A (en) * 1995-12-28 1999-02-23 Unisys Corporation Multi-processor data processing system with multiple second level caches mapable to all of addressable memory
US5946710A (en) * 1996-11-14 1999-08-31 Unisys Corporation Selectable two-way, four-way double cache interleave scheme
US5875201A (en) * 1996-12-30 1999-02-23 Unisys Corporation Second level cache having instruction cache parity error control
US5960455A (en) * 1996-12-30 1999-09-28 Unisys Corporation Scalable cross bar type storage controller
US6122711A (en) 1997-01-07 2000-09-19 Unisys Corporation Method of and apparatus for store-in second level cache flush
US5860093A (en) * 1997-01-21 1999-01-12 Unisys Corporation Reduced instruction processor/storage controller interface
US6014709A (en) * 1997-11-05 2000-01-11 Unisys Corporation Message flow protocol for avoiding deadlocks
US6049845A (en) * 1997-11-05 2000-04-11 Unisys Corporation System and method for providing speculative arbitration for transferring data
US6092156A (en) * 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
US6052760A (en) * 1997-11-05 2000-04-18 Unisys Corporation Computer system including plural caches and utilizing access history or patterns to determine data ownership for efficient handling of software locks
US6314501B1 (en) 1998-07-23 2001-11-06 Unisys Corporation Computer system and method for operating multiple operating systems in different partitions of the computer system and for allowing the different partitions to communicate with one another through shared memory
US6665761B1 (en) 1999-07-28 2003-12-16 Unisys Corporation Method and apparatus for routing interrupts in a clustered multiprocessor system
US6687818B1 (en) 1999-07-28 2004-02-03 Unisys Corporation Method and apparatus for initiating execution of an application processor in a clustered multiprocessor system
US7512395B2 (en) * 2006-01-31 2009-03-31 International Business Machines Corporation Receiver and integrated AM-FM/IQ demodulators for gigabit-rate data detection
US8184110B2 (en) 2007-11-05 2012-05-22 Seiko Epson Corporation Method and apparatus for indirect interface with enhanced programmable direct port

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JPS50156833A (de) * 1974-06-06 1975-12-18
US4038643A (en) * 1975-11-04 1977-07-26 Burroughs Corporation Microprogramming control system
US4168523A (en) * 1975-11-07 1979-09-18 Ncr Corporation Data processor utilizing a two level microaddressing controller
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
JPS6049332B2 (ja) * 1977-01-31 1985-11-01 株式会社東芝 マイクロプログラム制御方式
US4179736A (en) * 1977-11-22 1979-12-18 Honeywell Information Systems Inc. Microprogrammed computer control unit capable of efficiently executing a large repertoire of instructions for a high performance data processing unit
US4156278A (en) * 1977-11-22 1979-05-22 Honeywell Information Systems Inc. Multiple control store microprogrammable control unit including multiple function register control field
US4354232A (en) * 1977-12-16 1982-10-12 Honeywell Information Systems Inc. Cache memory command buffer circuit
US4307445A (en) * 1978-11-17 1981-12-22 Motorola, Inc. Microprogrammed control apparatus having a two-level control store for data processor
US4217640A (en) * 1978-12-11 1980-08-12 Honeywell Information Systems Inc. Cache unit with transit block buffer apparatus
US4313158A (en) * 1978-12-11 1982-01-26 Honeywell Information Systems Inc. Cache apparatus for enabling overlap of instruction fetch operations
US4268907A (en) * 1979-01-22 1981-05-19 Honeywell Information Systems Inc. Cache unit bypass apparatus
JPS5671139A (en) * 1979-11-13 1981-06-13 Nec Corp Microprogram parallel processing computer
US4376976A (en) * 1980-07-31 1983-03-15 Sperry Corporation Overlapped macro instruction control system
JPS5748139A (en) * 1980-09-04 1982-03-19 Nec Corp Microprogram control device
US4433374A (en) * 1980-11-14 1984-02-21 Sperry Corporation Cache/disk subsystem with cache bypass
JPS5846440A (ja) * 1981-09-11 1983-03-17 Nec Corp マイクロプログラム制御方式
JPS5967319A (ja) * 1982-10-08 1984-04-17 Nippon Steel Corp 超深絞り用鋼板の製造方法

Also Published As

Publication number Publication date
JPH0630060B2 (ja) 1994-04-20
EP0121373B1 (de) 1990-09-12
EP0121373A3 (en) 1988-03-02
US4586133A (en) 1986-04-29
EP0121373A2 (de) 1984-10-10
CA1218162A (en) 1987-02-17
JPS603043A (ja) 1985-01-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee