DE3482077D1 - Verfahren zur herstellung einer halbleiteranordnung vom soi-typ. - Google Patents
Verfahren zur herstellung einer halbleiteranordnung vom soi-typ.Info
- Publication number
- DE3482077D1 DE3482077D1 DE8484308284T DE3482077T DE3482077D1 DE 3482077 D1 DE3482077 D1 DE 3482077D1 DE 8484308284 T DE8484308284 T DE 8484308284T DE 3482077 T DE3482077 T DE 3482077T DE 3482077 D1 DE3482077 D1 DE 3482077D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor device
- soi type
- soi
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
- H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
- Y10S117/903—Dendrite or web or cage technique
- Y10S117/904—Laser beam
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58225653A JPS60117613A (ja) | 1983-11-30 | 1983-11-30 | 半導体装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3482077D1 true DE3482077D1 (de) | 1990-05-31 |
Family
ID=16832661
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8484308284T Expired - Fee Related DE3482077D1 (de) | 1983-11-30 | 1984-11-29 | Verfahren zur herstellung einer halbleiteranordnung vom soi-typ. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4584025A (de) |
EP (1) | EP0145415B1 (de) |
JP (1) | JPS60117613A (de) |
KR (1) | KR900001266B1 (de) |
DE (1) | DE3482077D1 (de) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60150618A (ja) * | 1984-01-17 | 1985-08-08 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US4661224A (en) * | 1984-11-26 | 1987-04-28 | Ionics, Incorporated | Process and apparatus for electrically desorbing components selectively sorbed on an electrolytically conducting barrier |
JPS61166071A (ja) * | 1985-01-17 | 1986-07-26 | Toshiba Corp | 半導体装置及びその製造方法 |
US4857479A (en) * | 1985-10-08 | 1989-08-15 | Motorola | Method of making poly-sidewall contact transistors |
JPS6319810A (ja) * | 1986-07-14 | 1988-01-27 | Agency Of Ind Science & Technol | 半導体装置の製造方法 |
JP2505767B2 (ja) * | 1986-09-18 | 1996-06-12 | キヤノン株式会社 | 光電変換装置の製造方法 |
US4902642A (en) * | 1987-08-07 | 1990-02-20 | Texas Instruments, Incorporated | Epitaxial process for silicon on insulator structure |
US5849601A (en) * | 1990-12-25 | 1998-12-15 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
US7115902B1 (en) | 1990-11-20 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
KR950013784B1 (ko) * | 1990-11-20 | 1995-11-16 | 가부시키가이샤 한도오따이 에네루기 겐큐쇼 | 반도체 전계효과 트랜지스터 및 그 제조방법과 박막트랜지스터 |
US5404040A (en) * | 1990-12-21 | 1995-04-04 | Siliconix Incorporated | Structure and fabrication of power MOSFETs, including termination structures |
US5304831A (en) * | 1990-12-21 | 1994-04-19 | Siliconix Incorporated | Low on-resistance power MOS technology |
US7576360B2 (en) * | 1990-12-25 | 2009-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device which comprises thin film transistors and method for manufacturing the same |
US7098479B1 (en) | 1990-12-25 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
DE4300806C1 (de) * | 1993-01-14 | 1993-12-23 | Siemens Ag | Verfahren zur Herstellung von vertikalen MOS-Transistoren |
US5738731A (en) | 1993-11-19 | 1998-04-14 | Mega Chips Corporation | Photovoltaic device |
US7081938B1 (en) | 1993-12-03 | 2006-07-25 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
JP3326654B2 (ja) | 1994-05-02 | 2002-09-24 | ソニー株式会社 | 表示用半導体チップの製造方法 |
US5543348A (en) * | 1995-03-29 | 1996-08-06 | Kabushiki Kaisha Toshiba | Controlled recrystallization of buried strap in a semiconductor memory device |
US5905279A (en) * | 1996-04-09 | 1999-05-18 | Kabushiki Kaisha Toshiba | Low resistant trench fill for a semiconductor device |
US6406966B1 (en) * | 2000-11-07 | 2002-06-18 | National Semiconductor Corporation | Uniform emitter formation using selective laser recrystallization |
US6992365B2 (en) * | 2001-10-12 | 2006-01-31 | Ovonyx, Inc. | Reducing leakage currents in memories with phase-change material |
US20040084679A1 (en) * | 2002-10-30 | 2004-05-06 | Sharp Kabushiki Kaisha | Semiconductor devices and methods of manufacture thereof |
JP4511803B2 (ja) * | 2003-04-14 | 2010-07-28 | 株式会社半導体エネルギー研究所 | D/a変換回路及びそれを内蔵した半導体装置の製造方法 |
US9484451B2 (en) * | 2007-10-05 | 2016-11-01 | Vishay-Siliconix | MOSFET active area and edge termination area charge balance |
JP5548356B2 (ja) * | 2007-11-05 | 2014-07-16 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
WO2016028944A1 (en) | 2014-08-19 | 2016-02-25 | Vishay-Siliconix | Super-junction metal oxide semiconductor field effect transistor |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4926456A (de) * | 1972-07-11 | 1974-03-08 | ||
DE2510593C3 (de) * | 1975-03-11 | 1982-03-18 | Siemens AG, 1000 Berlin und 8000 München | Integrierte Halbleiter-Schaltungsanordnung |
JPS5539677A (en) * | 1978-09-14 | 1980-03-19 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor device and its manufacturing |
JPS5552221A (en) * | 1978-10-12 | 1980-04-16 | Toshiba Corp | Impurity dispersion method and its device |
NL7810549A (nl) * | 1978-10-23 | 1980-04-25 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleider- inrichting. |
JPS55160443A (en) * | 1979-05-22 | 1980-12-13 | Semiconductor Res Found | Manufacture of semiconductor integrated circuit device |
JPS5674921A (en) * | 1979-11-22 | 1981-06-20 | Toshiba Corp | Manufacturing method of semiconductor and apparatus thereof |
US4269631A (en) * | 1980-01-14 | 1981-05-26 | International Business Machines Corporation | Selective epitaxy method using laser annealing for making filamentary transistors |
US4323417A (en) * | 1980-05-06 | 1982-04-06 | Texas Instruments Incorporated | Method of producing monocrystal on insulator |
JPS56157038A (en) * | 1980-05-08 | 1981-12-04 | Fujitsu Ltd | Manufacture of semiconductor device |
US4385937A (en) * | 1980-05-20 | 1983-05-31 | Tokyo Shibaura Denki Kabushiki Kaisha | Regrowing selectively formed ion amorphosized regions by thermal gradient |
JPS5748246A (en) * | 1980-08-13 | 1982-03-19 | Fujitsu Ltd | Manufacture of semiconductor device |
JPS57154871A (en) * | 1981-03-19 | 1982-09-24 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS5861622A (ja) * | 1981-10-09 | 1983-04-12 | Hitachi Ltd | 単結晶薄膜の製造方法 |
JPS58116722A (ja) * | 1981-12-29 | 1983-07-12 | Fujitsu Ltd | 半導体装置の製造方法 |
US4528745A (en) * | 1982-07-13 | 1985-07-16 | Toyo Denki Seizo Kabushiki Kaisha | Method for the formation of buried gates of a semiconductor device utilizing etch and refill techniques |
US4542580A (en) * | 1983-02-14 | 1985-09-24 | Prime Computer, Inc. | Method of fabricating n-type silicon regions and associated contacts |
JPS59205712A (ja) * | 1983-04-30 | 1984-11-21 | Fujitsu Ltd | 半導体装置の製造方法 |
-
1983
- 1983-11-30 JP JP58225653A patent/JPS60117613A/ja active Pending
-
1984
- 1984-11-01 KR KR1019840006845A patent/KR900001266B1/ko not_active IP Right Cessation
- 1984-11-26 US US06/674,831 patent/US4584025A/en not_active Expired - Fee Related
- 1984-11-29 EP EP84308284A patent/EP0145415B1/de not_active Expired - Lifetime
- 1984-11-29 DE DE8484308284T patent/DE3482077D1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0145415A3 (en) | 1987-08-19 |
EP0145415A2 (de) | 1985-06-19 |
US4584025A (en) | 1986-04-22 |
KR900001266B1 (ko) | 1990-03-05 |
EP0145415B1 (de) | 1990-04-25 |
JPS60117613A (ja) | 1985-06-25 |
KR850004169A (ko) | 1985-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3482077D1 (de) | Verfahren zur herstellung einer halbleiteranordnung vom soi-typ. | |
DE3485924D1 (de) | Verfahren zur herstellung einer halbleiterlaservorrichtung. | |
DE3483444D1 (de) | Verfahren zur herstellung eines halbleiterbauelementes. | |
DE3485880D1 (de) | Verfahren zur herstellung von halbleiteranordnungen. | |
DE3867670D1 (de) | Verfahren zur herstellung einer halbleiteranordnung vom feldeffekttransistor-typ. | |
DE69015216D1 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung. | |
DE3686125T2 (de) | Verfahren zur herstellung einer integrierten schaltung. | |
DE3686315D1 (de) | Verfahren zur herstellung einer halbleiterstruktur. | |
DE68924366T2 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung. | |
DE68907507D1 (de) | Verfahren zur herstellung einer halbleitervorrichtung. | |
DE69004201T2 (de) | Verfahren zur Herstellung einer SOI-Halbleiteranordnung. | |
DE69023558T2 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung. | |
DE3485087D1 (de) | Verfahren zur herstellung gekruemmter oberflaechen. | |
DD132091A5 (de) | Verfahren zur herstellung einer halbleiteranordnung | |
DE3381126D1 (de) | Verfahren zur herstellung einer monokristallinen halbleiterschicht. | |
DE69016955T2 (de) | Verfahren zur Herstellung einer Halbleiteranordnung. | |
DE3485089D1 (de) | Verfahren zur herstellung von halbleitervorrichtungen. | |
DE3582143D1 (de) | Verfahren zur herstellung einer halbleitervorrichtung. | |
DE3483809D1 (de) | Verfahren zur herstellung einer dielektrisch isolierten integrierten schaltung. | |
DE3779802D1 (de) | Verfahren zur herstellung einer halbleiteranordnung. | |
DE3484526D1 (de) | Verfahren zur herstellung einer halbleiteranordnung. | |
DE3486144D1 (de) | Verfahren zur herstellung einer halbleiteranordnung. | |
DE3578263D1 (de) | Verfahren zur herstellung einer halbleiteranordnung. | |
DE3382001D1 (de) | Verfahren zur herstellung optisch aktiver halbester. | |
DE3783799T2 (de) | Verfahren zur herstellung einer halbleiteranordnung. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |