DE3475454D1 - Fabrication of stacked mos devices - Google Patents
Fabrication of stacked mos devicesInfo
- Publication number
- DE3475454D1 DE3475454D1 DE8484308910T DE3475454T DE3475454D1 DE 3475454 D1 DE3475454 D1 DE 3475454D1 DE 8484308910 T DE8484308910 T DE 8484308910T DE 3475454 T DE3475454 T DE 3475454T DE 3475454 D1 DE3475454 D1 DE 3475454D1
- Authority
- DE
- Germany
- Prior art keywords
- polysilicon
- substrate
- silicon
- gate
- mos devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/091—Laser beam processing of fets
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/164—Three dimensional processing
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000444777A CA1197628A (en) | 1984-01-05 | 1984-01-05 | Fabrication of stacked mos devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3475454D1 true DE3475454D1 (en) | 1989-01-05 |
Family
ID=4126883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE8484308910T Expired DE3475454D1 (en) | 1984-01-05 | 1984-12-19 | Fabrication of stacked mos devices |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4651408A (de) |
| EP (1) | EP0151350B1 (de) |
| JP (1) | JPH0656882B2 (de) |
| AT (1) | ATE39034T1 (de) |
| CA (1) | CA1197628A (de) |
| DE (1) | DE3475454D1 (de) |
Families Citing this family (46)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1213192B (it) * | 1984-07-19 | 1989-12-14 | Ates Componenti Elettron | Processo per la fabbricazione di transistori ad effetto di campo agate isolato (igfet) ad elevata velocita' di risposta in circuiti integrati ad alta densita'. |
| DE3685732T2 (de) * | 1985-12-20 | 1993-01-21 | Agency Ind Science Techn | Verfahren zur herstellung einer monokristallinen duennen schicht. |
| US4717688A (en) * | 1986-04-16 | 1988-01-05 | Siemens Aktiengesellschaft | Liquid phase epitaxy method |
| JP2516604B2 (ja) * | 1986-10-17 | 1996-07-24 | キヤノン株式会社 | 相補性ｍｏｓ集積回路装置の製造方法 |
| US5149666A (en) * | 1987-01-07 | 1992-09-22 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor memory device having a floating gate electrode composed of 2-10 silicon grains |
| US4772568A (en) * | 1987-05-29 | 1988-09-20 | General Electric Company | Method of making integrated circuit with pair of MOS field effect transistors sharing a common source/drain region |
| JPH0824144B2 (ja) * | 1987-06-10 | 1996-03-06 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US4849365A (en) * | 1988-02-16 | 1989-07-18 | Honeywell Inc. | Selective integrated circuit interconnection |
| US4927779A (en) * | 1988-08-10 | 1990-05-22 | International Business Machines Corporation | Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor |
| US4921813A (en) * | 1988-10-17 | 1990-05-01 | Motorola, Inc. | Method for making a polysilicon transistor |
| US4918510A (en) * | 1988-10-31 | 1990-04-17 | Motorola, Inc. | Compact CMOS device structure |
| US4950618A (en) * | 1989-04-14 | 1990-08-21 | Texas Instruments, Incorporated | Masking scheme for silicon dioxide mesa formation |
| US4948745A (en) * | 1989-05-22 | 1990-08-14 | Motorola, Inc. | Process for elevated source/drain field effect structure |
| US4997785A (en) * | 1989-09-05 | 1991-03-05 | Motorola, Inc. | Shared gate CMOS transistor |
| US5572054A (en) * | 1990-01-22 | 1996-11-05 | Silicon Storage Technology, Inc. | Method of operating a single transistor non-volatile electrically alterable semiconductor memory device |
| EP0459763B1 (de) * | 1990-05-29 | 1997-05-02 | Semiconductor Energy Laboratory Co., Ltd. | Dünnfilmtransistoren |
| JP2604487B2 (ja) * | 1990-06-06 | 1997-04-30 | 松下電器産業株式会社 | 半導体装置およびその製造方法 |
| JP2996694B2 (ja) * | 1990-06-13 | 2000-01-11 | 沖電気工業株式会社 | 半導体スタックトｃｍｏｓ装置の製造方法 |
| KR950013784B1 (ko) | 1990-11-20 | 1995-11-16 | 가부시키가이샤 한도오따이 에네루기 겐큐쇼 | 반도체 전계효과 트랜지스터 및 그 제조방법과 박막트랜지스터 |
| US7115902B1 (en) | 1990-11-20 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US5849601A (en) * | 1990-12-25 | 1998-12-15 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7098479B1 (en) | 1990-12-25 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7576360B2 (en) * | 1990-12-25 | 2009-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device which comprises thin film transistors and method for manufacturing the same |
| US5166091A (en) * | 1991-05-31 | 1992-11-24 | At&T Bell Laboratories | Fabrication method in vertical integration |
| JP3255942B2 (ja) * | 1991-06-19 | 2002-02-12 | 株式会社半導体エネルギー研究所 | 逆スタガ薄膜トランジスタの作製方法 |
| US5215932A (en) * | 1991-09-24 | 1993-06-01 | Micron Technology, Inc. | Self-aligned 3-dimensional PMOS devices without selective EPI |
| JP3277533B2 (ja) * | 1992-01-08 | 2002-04-22 | ソニー株式会社 | 半導体装置の製造方法 |
| US5252849A (en) * | 1992-03-02 | 1993-10-12 | Motorola, Inc. | Transistor useful for further vertical integration and method of formation |
| US5612563A (en) * | 1992-03-02 | 1997-03-18 | Motorola Inc. | Vertically stacked vertical transistors used to form vertical logic gate structures |
| US5308782A (en) * | 1992-03-02 | 1994-05-03 | Motorola | Semiconductor memory device and method of formation |
| JP3173854B2 (ja) | 1992-03-25 | 2001-06-04 | 株式会社半導体エネルギー研究所 | 薄膜状絶縁ゲイト型半導体装置の作製方法及び作成された半導体装置 |
| JP3144056B2 (ja) * | 1992-05-08 | 2001-03-07 | ヤマハ株式会社 | 薄膜トランジスタの製法 |
| US5266507A (en) * | 1992-05-18 | 1993-11-30 | Industrial Technology Research Institute | Method of fabricating an offset dual gate thin film field effect transistor |
| US5283456A (en) * | 1992-06-17 | 1994-02-01 | International Business Machines Corporation | Vertical gate transistor with low temperature epitaxial channel |
| US5324960A (en) * | 1993-01-19 | 1994-06-28 | Motorola, Inc. | Dual-transistor structure and method of formation |
| US6331717B1 (en) | 1993-08-12 | 2001-12-18 | Semiconductor Energy Laboratory Co. Ltd. | Insulated gate semiconductor device and process for fabricating the same |
| JP3173926B2 (ja) | 1993-08-12 | 2001-06-04 | 株式会社半導体エネルギー研究所 | 薄膜状絶縁ゲイト型半導体装置の作製方法及びその半導体装置 |
| US7081938B1 (en) * | 1993-12-03 | 2006-07-25 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| KR0136931B1 (ko) * | 1994-05-12 | 1998-04-24 | 문정환 | 박막 트랜지스터의 구조 및 제조방법 |
| US5500545A (en) * | 1995-02-27 | 1996-03-19 | United Microelectronics Corporation | Double switching field effect transistor and method of manufacturing it |
| US5668025A (en) * | 1995-02-28 | 1997-09-16 | Sgs-Thomson Microelectronics, Inc. | Method of making a FET with dielectrically isolated sources and drains |
| US5773328A (en) | 1995-02-28 | 1998-06-30 | Sgs-Thomson Microelectronics, Inc. | Method of making a fully-dielectric-isolated fet |
| US6420764B1 (en) * | 1995-02-28 | 2002-07-16 | Stmicroelectronics, Inc. | Field effect transitor having dielectrically isolated sources and drains and methods for making same |
| KR100209750B1 (ko) * | 1996-11-08 | 1999-07-15 | 구본준 | 씨모스 소자의 구조 및 제조방법 |
| US6198114B1 (en) | 1997-10-28 | 2001-03-06 | Stmicroelectronics, Inc. | Field effect transistor having dielectrically isolated sources and drains and method for making same |
| US7414289B2 (en) * | 2006-07-17 | 2008-08-19 | Advanced Micro Devices, Inc. | SOI Device with charging protection and methods of making same |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57192081A (en) * | 1981-05-19 | 1982-11-26 | Ibm | Field effect transistor unit |
| US4467518A (en) * | 1981-05-19 | 1984-08-28 | Ibm Corporation | Process for fabrication of stacked, complementary MOS field effect transistor circuits |
| US4500905A (en) * | 1981-09-30 | 1985-02-19 | Tokyo Shibaura Denki Kabushiki Kaisha | Stacked semiconductor device with sloping sides |
| JPS58164219A (ja) * | 1982-03-25 | 1983-09-29 | Agency Of Ind Science & Technol | 積層型半導体装置の製造方法 |
| CA1191970A (en) * | 1982-11-09 | 1985-08-13 | Abdalla A. Naem | Stacked mos transistor |
| US4476475A (en) * | 1982-11-19 | 1984-10-09 | Northern Telecom Limited | Stacked MOS transistor |
| US4488348A (en) * | 1983-06-15 | 1984-12-18 | Hewlett-Packard Company | Method for making a self-aligned vertically stacked gate MOS device |
| US4523370A (en) * | 1983-12-05 | 1985-06-18 | Ncr Corporation | Process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction |
| US4555843A (en) * | 1984-04-27 | 1985-12-03 | Texas Instruments Incorporated | Method of fabricating density intensive non-self-aligned stacked CMOS |
-
1984
- 1984-01-05 CA CA000444777A patent/CA1197628A/en not_active Expired
- 1984-05-17 US US06/611,549 patent/US4651408A/en not_active Expired - Lifetime
- 1984-12-19 AT AT84308910T patent/ATE39034T1/de not_active IP Right Cessation
- 1984-12-19 EP EP84308910A patent/EP0151350B1/de not_active Expired
- 1984-12-19 DE DE8484308910T patent/DE3475454D1/de not_active Expired
-
1985
- 1985-01-04 JP JP60000013A patent/JPH0656882B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0151350B1 (de) | 1988-11-30 |
| CA1197628A (en) | 1985-12-03 |
| ATE39034T1 (de) | 1988-12-15 |
| EP0151350A1 (de) | 1985-08-14 |
| JPH0656882B2 (ja) | 1994-07-27 |
| JPS60160159A (ja) | 1985-08-21 |
| US4651408A (en) | 1987-03-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8339 | Ceased/non-payment of the annual fee |