DE3381267D1 - Verfahren zur herstellung von vergrabenen gates fuer eine halbleiteranordnung. - Google Patents

Verfahren zur herstellung von vergrabenen gates fuer eine halbleiteranordnung.

Info

Publication number
DE3381267D1
DE3381267D1 DE8383304079T DE3381267T DE3381267D1 DE 3381267 D1 DE3381267 D1 DE 3381267D1 DE 8383304079 T DE8383304079 T DE 8383304079T DE 3381267 T DE3381267 T DE 3381267T DE 3381267 D1 DE3381267 D1 DE 3381267D1
Authority
DE
Germany
Prior art keywords
gates
semiconductor arrangement
burned
producing
producing burned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8383304079T
Other languages
English (en)
Inventor
Kimihiro Muraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Electric Manufacturing Ltd
Toyo Electric Manufacturing Co Ltd
Original Assignee
Toyo Electric Manufacturing Ltd
Toyo Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP12046182A external-priority patent/JPS5911685A/ja
Priority claimed from JP12045982A external-priority patent/JPS5911683A/ja
Priority claimed from JP12046082A external-priority patent/JPS5911684A/ja
Priority claimed from JP14695782A external-priority patent/JPS5936971A/ja
Application filed by Toyo Electric Manufacturing Ltd, Toyo Electric Manufacturing Co Ltd filed Critical Toyo Electric Manufacturing Ltd
Application granted granted Critical
Publication of DE3381267D1 publication Critical patent/DE3381267D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66416—Static induction transistors [SIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012—Base regions of thyristors
    • H01L29/102—Cathode base regions of thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/039—Displace P-N junction
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/088—J-Fet, i.e. junction field effect transistor
DE8383304079T 1982-07-13 1983-07-13 Verfahren zur herstellung von vergrabenen gates fuer eine halbleiteranordnung. Expired - Lifetime DE3381267D1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP12046182A JPS5911685A (ja) 1982-07-13 1982-07-13 半導体装置の埋込みゲ−ト形成法
JP12045982A JPS5911683A (ja) 1982-07-13 1982-07-13 半導体装置の埋込みゲ−ト形成法
JP12046082A JPS5911684A (ja) 1982-07-13 1982-07-13 半導体装置の埋込みゲ−ト形成法
JP14695782A JPS5936971A (ja) 1982-08-26 1982-08-26 半導体装置の埋込みゲ−ト形成法

Publications (1)

Publication Number Publication Date
DE3381267D1 true DE3381267D1 (de) 1990-04-05

Family

ID=27470688

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383304079T Expired - Lifetime DE3381267D1 (de) 1982-07-13 1983-07-13 Verfahren zur herstellung von vergrabenen gates fuer eine halbleiteranordnung.

Country Status (3)

Country Link
US (1) US4528745A (de)
EP (1) EP0099270B1 (de)
DE (1) DE3381267D1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4654679A (en) * 1983-10-05 1987-03-31 Toyo Denki Seizo Kabushiki Kaisha Static induction thyristor with stepped-doping gate region
JPS60117613A (ja) * 1983-11-30 1985-06-25 Fujitsu Ltd 半導体装置の製造方法
US4660278A (en) * 1985-06-26 1987-04-28 Texas Instruments Incorporated Process of making IC isolation structure
US4755859A (en) * 1985-09-30 1988-07-05 Kabushiki Kaisha Toshiba Thin film static induction transistor and method for manufacturing the same
US5342792A (en) * 1986-03-07 1994-08-30 Canon Kabushiki Kaisha Method of manufacturing semiconductor memory element
EP0259629A1 (de) * 1986-08-19 1988-03-16 Siemens Aktiengesellschaft Verfahren zum Herstellen einer definierten Dotierung in den vertikalen Seitenwänden und den Böden von in Halbleitersubstrate eingebrachten Gräben
US5889298A (en) * 1993-04-30 1999-03-30 Texas Instruments Incorporated Vertical JFET field effect transistor
US5554561A (en) * 1993-04-30 1996-09-10 Texas Instruments Incorporated Epitaxial overgrowth method
US5712189A (en) * 1993-04-30 1998-01-27 Texas Instruments Incorporated Epitaxial overgrowth method
DE69429130T2 (de) * 1993-04-30 2002-07-11 Texas Instruments Inc Verfahren zum epitaxialen Wachstum und Vorrichtungen
US5648665A (en) * 1994-04-28 1997-07-15 Ngk Insulators, Ltd. Semiconductor device having a plurality of cavity defined gating regions and a fabrication method therefor
JPH07302896A (ja) * 1994-04-28 1995-11-14 Ngk Insulators Ltd 半導体装置およびその製造方法
US5674766A (en) * 1994-12-30 1997-10-07 Siliconix Incorporated Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer
US6406982B2 (en) 2000-06-05 2002-06-18 Denso Corporation Method of improving epitaxially-filled trench by smoothing trench prior to filling
JP2004047967A (ja) * 2002-05-22 2004-02-12 Denso Corp 半導体装置及びその製造方法
JP3743395B2 (ja) * 2002-06-03 2006-02-08 株式会社デンソー 半導体装置の製造方法及び半導体装置
DE102010000860A1 (de) 2010-01-13 2011-07-14 ZF Friedrichshafen AG, 88046 Verfahren zum Betreiben eines Fahrzeugantriebsstranges mit einer Brennkraftmaschine

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753803A (en) * 1968-12-06 1973-08-21 Hitachi Ltd Method of dividing semiconductor layer into a plurality of isolated regions
US3855608A (en) * 1972-10-24 1974-12-17 Motorola Inc Vertical channel junction field-effect transistors and method of manufacture
US3969746A (en) * 1973-12-10 1976-07-13 Texas Instruments Incorporated Vertical multijunction solar cell
US4171995A (en) * 1975-10-20 1979-10-23 Semiconductor Research Foundation Epitaxial deposition process for producing an electrostatic induction type thyristor
JPS5368178A (en) * 1976-11-30 1978-06-17 Handotai Kenkyu Shinkokai Fet transistor
GB1602361A (en) * 1977-02-21 1981-11-11 Zaidan Hojin Handotai Kenkyu Semiconductor memory devices
JPS53127272A (en) * 1977-04-13 1978-11-07 Semiconductor Res Found Electrostatic induction transistor
US4375124A (en) * 1981-11-12 1983-03-01 Gte Laboratories Incorporated Power static induction transistor fabrication
US4466173A (en) * 1981-11-23 1984-08-21 General Electric Company Methods for fabricating vertical channel buried grid field controlled devices including field effect transistors and field controlled thyristors utilizing etch and refill techniques

Also Published As

Publication number Publication date
EP0099270A3 (en) 1985-11-27
US4528745A (en) 1985-07-16
EP0099270A2 (de) 1984-01-25
EP0099270B1 (de) 1990-02-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee