|
DE3271123D1
(en)
*
|
1982-06-08 |
1986-06-19 |
Ibm Deutschland |
Circuits in the control part of a microprogrammable processor for direct hardware execution of selected instructions
|
|
US4594658A
(en)
*
|
1983-04-05 |
1986-06-10 |
Burroughs Corporation |
Hierarchy of control stores for overlapped data transmission
|
|
EP0121372A3
(de)
*
|
1983-04-05 |
1988-03-02 |
Unisys Corporation |
Steuerspeicherhierarchie für überlappte Datenübertragung
|
|
US4586133A
(en)
*
|
1983-04-05 |
1986-04-29 |
Burroughs Corporation |
Multilevel controller for a cache memory interface in a multiprocessing system
|
|
US4800486A
(en)
*
|
1983-09-29 |
1989-01-24 |
Tandem Computers Incorporated |
Multiple data patch CPU architecture
|
|
USRE34052E
(en)
*
|
1984-05-31 |
1992-09-01 |
International Business Machines Corporation |
Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
|
|
US4791560A
(en)
*
|
1985-07-31 |
1988-12-13 |
Unisys Corporation |
Macro level control of an activity switch in a scientific vector processor which processor requires an external executive control program
|
|
JPH0743648B2
(ja)
*
|
1985-11-15 |
1995-05-15 |
株式会社日立製作所 |
情報処理装置
|
|
US5001624A
(en)
*
|
1987-02-13 |
1991-03-19 |
Harrell Hoffman |
Processor controlled DMA controller for transferring instruction and data from memory to coprocessor
|
|
US5005118A
(en)
*
|
1987-04-10 |
1991-04-02 |
Tandem Computers Incorporated |
Method and apparatus for modifying micro-instructions using a macro-instruction pipeline
|
|
US5185870A
(en)
*
|
1987-04-10 |
1993-02-09 |
Tandem Computers, Inc, |
System to determine if modification of first macroinstruction to execute in fewer clock cycles
|
|
DE3855524T2
(de)
*
|
1987-06-19 |
1997-02-06 |
Hitachi Ltd |
Arithmetik-Parallelverarbeitungseinheit und zugehöriger Kompilator
|
|
JP2982875B2
(ja)
*
|
1987-12-28 |
1999-11-29 |
株式会社日立製作所 |
スレーブ制御装置
|
|
JP2806524B2
(ja)
*
|
1988-03-04 |
1998-09-30 |
日本電気株式会社 |
ベクトル演算命令発行制御方法
|
|
WO1991011765A1
(en)
*
|
1990-01-29 |
1991-08-08 |
Teraplex, Inc. |
Architecture for minimal instruction set computing system
|
|
EP0477599A3
(en)
*
|
1990-09-26 |
1993-11-10 |
Siemens Ag |
Control store for a processor comprising several processing elements
|
|
EP0498067A2
(de)
*
|
1991-02-08 |
1992-08-12 |
International Business Machines Corporation |
Mikrokodeerzeugung für eine Maschine mit skalierbarem Verbundbefehlssatz
|
|
US5363495A
(en)
*
|
1991-08-26 |
1994-11-08 |
International Business Machines Corporation |
Data processing system with multiple execution units capable of executing instructions out of sequence
|
|
US5426783A
(en)
*
|
1992-11-02 |
1995-06-20 |
Amdahl Corporation |
System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set
|
|
CA2123442A1
(en)
*
|
1993-09-20 |
1995-03-21 |
David S. Ray |
Multiple execution unit dispatch with instruction dependency
|
|
US5673427A
(en)
*
|
1994-03-01 |
1997-09-30 |
Intel Corporation |
Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
|
|
US5537629A
(en)
*
|
1994-03-01 |
1996-07-16 |
Intel Corporation |
Decoder for single cycle decoding of single prefixes in variable length instructions
|
|
US5600806A
(en)
*
|
1994-03-01 |
1997-02-04 |
Intel Corporation |
Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
|
|
US5586277A
(en)
*
|
1994-03-01 |
1996-12-17 |
Intel Corporation |
Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
|
|
US5566298A
(en)
*
|
1994-03-01 |
1996-10-15 |
Intel Corporation |
Method for state recovery during assist and restart in a decoder having an alias mechanism
|
|
US5559974A
(en)
*
|
1994-03-01 |
1996-09-24 |
Intel Corporation |
Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation
|
|
US5630083A
(en)
*
|
1994-03-01 |
1997-05-13 |
Intel Corporation |
Decoder for decoding multiple instructions in parallel
|
|
US5758116A
(en)
*
|
1994-09-30 |
1998-05-26 |
Intel Corporation |
Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
|
|
US5867701A
(en)
*
|
1995-06-12 |
1999-02-02 |
Intel Corporation |
System for inserting a supplemental micro-operation flow into a macroinstruction-generated micro-operation flow
|
|
US5815724A
(en)
*
|
1996-03-29 |
1998-09-29 |
Intel Corporation |
Method and apparatus for controlling power consumption in a microprocessor
|
|
US6789186B1
(en)
*
|
2000-02-18 |
2004-09-07 |
Hewlett-Packard Development Company, L.P. |
Method and apparatus to reduce penalty of microcode lookup
|
|
US7698539B1
(en)
|
2003-07-16 |
2010-04-13 |
Banning John P |
System and method of instruction modification
|
|
US9122465B2
(en)
*
|
2011-12-06 |
2015-09-01 |
International Business Machines Corporation |
Programmable microcode unit for mapping plural instances of an instruction in plural concurrently executed instruction streams to plural microcode sequences in plural memory partitions
|