DE3128400A1 - "INTERFACE OF A DATA TRANSFER SYSTEM" - Google Patents

Description

11066 / H / V (DB if58)

Interface of a data transmission system

The invention relates to an interface according to the preamble of claim 1.

Messages of all kinds are increasingly digital and independent of the Type of the respective analog or numerical information transmitted. Between the actual transmission system, e.g. a PCM system, and its terminals usually require interfaces that are supported by the Adapt the data supplied to the end station to the respective conditions of the transmission system and, on the other hand, the data received by the transmission system Bring data into a form suitable for the end station. Known interfaces for a PCM system receive the signal below from its line Control by the line clock and send it along with addresses for the channels under clock control by the terminal itself to this. In the opposite direction they receive the data bits from the terminal, with which a standardized PCM signal is formed. The invention is based on the object of specifying an interface, which can perform more functions than the previously known interfaces.

This task is achieved by the interface characterized in claim 1 solved.

The interface described here operates in channel G of each PCM frame in dialog mode with the terminal. In particular, you can use the terminal Give instructions on how to transmit messages to the line van the remote monitoring circuit with which the PCM system is equipped, as well as loop commands for loop connection the transmit and receive sections immediately before the line interface. On the other hand, the interface described here is able to handle alarm states regarding malfunctions in the PCM connection (loss of the Frame synchronization, excessive error rate, etc.) and to report them to the end station. It also provides her with messages that come from the remote terminal to indicate that an alarm condition has been detected or the execution of the loop formation or the remote monitoring process is required.

11G66 / H / V (DB

The main advantages of the invention come in conjunction with each any end point to apply. Preferably, however, the interface should between a PCM system and a time division multiplex exchange for Switching through the PCM channels are used, in particular a transit switching center an integrated switching network for telephone and data signals. Such a transit exchange is for example described in IT-PS 1.G37.25S.

In a preferred embodiment, the invention is described below described in more detail. In the drawing show:

FIG. 1 shows a block diagram of the interface; Figure 2 shows a schematic representation of a Hanalbildungskreises (IPD) Figure 1;

FIG. 3 shows a modification of the interface according to FIG. 1 for use with two terminals which are operated according to the master-slave method; and FIG. k shows a preferred embodiment of a circuit for determining the phase shift between the line clock and the clock of the terminal.

In Figure 1, the interface described here (interface circuit) marked with UL. Its transmission section consists of a transmission control circuit CT, which receives the data DE to be transmitted and the transmission clock CKT from the terminal T, for the channel D of each frame proper binary configuration (words A or B) generated before the data is encoded, and the output signal SU obtained in this way sends to the line interface IL of the PCM system. The transmission control circuit CT provides the channel D to be transmitted Data DE, possibly loop commands, whereupon it generates a corresponding signal L. If necessary, it also determines the command to send remote monitoring messages on the line to send, whereupon it changes the code used to generate the output signal accordingly. The remote terminal is in in both cases (loop formation or remote monitoring) by the word B informed. The terminal T preferably determines the by a command S code normally to be used by the transmission control circuit CT. Furthermore, on the command of the terminal T, the loop status can be obtained from the transmission control circuit CT of the remote terminal are indicated by the fact that all bits sent on the line have a constant binary value

11066 / H / V (DB if5B)

granted ujird. A transmission control circuit CT which uses the above Permitted to perform functions, was already in the patent application P 312572 * ν.Ο suggested.

The receiving part of the interface UL receives the PCM signal SE from the PCM line via its interface IL, which signal _{reaches the input of a first multiplexer M 1} , which is controlled by the loop signal L from the transmission control circuit CT. The output signal SU of the transmission control circuit CT is applied to the second input of this multiplexer. The signal SE (or SU in the case of a loop) is decoded by the decoder DEC, whose signal, that is to say the decoded data DD, is processed by a clock circuit TR together with the line clock CKL. The line clock CHL is obtained by the circuit EC which, in the example shown, is connected upstream of the decader DEC. In the context of the invention it is also possible to obtain the line clock CKL from the decoded data DD. The clock circuit TR has the following functions: It obtains the line bundle clock from the line clock CKL, each channel of the PCM frame being assigned its address I and the write signal Ld for an elastic memory ME being generated. It also establishes, if necessary, that the frame synchronization has been lost, and uses the FAT signal to inform the terminal T and the transmission control circuit CT, which in turn informs the remote terminal. Furthermore, the clock circuit TR detects malfunctions in the PCM connection or in the interface UL (e.g. excessive error portion, weight determination of the synchronous word A, etc.) and reports these to the terminal T via a plurality of signals, dis in the figure as a whole ALL are designated. Finally, it responds to an alarm signal (ATL) sent from the remote terminal. An example of a clock circuit TR for performing the functions explained has already been proposed in patent application P 3125723.2 (where the addresses I and the signal U belong to the clock signals CK).

üAs already explained, the channel D of each frame is used by the interface UL is used as a service channel to the terminal T by the clock circuit TR to deliver recorded alarm messages and, if necessary, to report a slip in the elastic memory ME. Contains the cutting parts UL

-B-

11066 / H / l / (DB 458)

X O ^Y 1 ^Y 2 ^Y 3 X ^Y 5 ^Y 6 X 1 FAT SL X X X

hence a channel formation circuit ITQ, which is in the channel O of each frame of the decoded data DD enters the data intended for the terminal T, before the elastic store ME the frames modified in this way the data DL are supplied.

Referring to Figure 1, the channel formation circuit ITO, which is shown in more detail in Figure 2, is shown is controlled by the clock circuit TR, through which it also receives the alarm signals ALL and FAT. He alternately creates two Messages that, for example, have the format

Frame A
Frame B

bits X are "transparent" (ie keep the binary values they have in the data DD), V ₁ to Y _g contain the information regarding the alarm signals ALL and SL informs the terminal that in the frame or in the double frame (Frame A + Frame B) of the data DD a slip will occur.

In the context of the invention, however, it is also possible to send alarm signals ALL directly to the terminal T using the bits Y ,, to Y _c for transmission

I α

other information or in all frames for channel 0 to use a single format, e.g. as indicated above for frame B. is. It is also possible that the channel formation circuit has more than two Messages generated.

The line data DL from the output of the channel formation circuit ITO are combined with the corresponding addresses I sent to the elastic store ME, which consists of a memory part MED for the data and a memory part MEI for the addresses. There they are under the control of a write signal Id, which is generated by the clock generator TR according to the line clock, is written and read by a read command R, which the terminal T obtains from its internal clock. The data DT and the addresses IT used by the elastic Memory ME are output, are therefore with the clock of the terminal T synchronized.

Elastic memories are made up of synchronous systems of data transmission per se generally known, as well as the so-called slip method to compensate

11D66 / H / V /

(DB

of differences between writing and reading clock. In the Italian patent Wr. 1.DA3.9B1, however, a special elastic memory is written, in which the data are written and read in parallel alternately in two identical registers. A binary switching mechanism controls the slip, ie the change of the write signals, if coincidence between the read pulses of one register and one of the two control pulse sequences is determined, which precede or follow the read pulses of the respective register by a period of time in which it is possible to to read the entire content of the register before the next write operation or to carry out the write operation before the next read operation. The elastic storage parts MED and MEI are preferably designed in a manner similar to this known storage device; they consist of k registers that are written and read cyclically and each have the capacity corresponding to a channel or an address.

The two memory parts are made by the same clock circuits controlled and controlled by the same binary switching mechanism that causes the slip when the write clock is compared to the reading by about 16 bits shifted. The restoration of the right relation between Reading and writing are done by suppressing (or reading twice after channel 3) of channel 0 during two consecutive frames. At the command of the terminal T, the UJeite of the binary switching mechanism assumed bit spans are reduced to half and the channel D suppressed or repeated once.

FIG. 2 shows an expedient embodiment of the channel formation circuit ITD shown. It includes a serial-parallel converter SP, in which the decoded Data DD in accordance with the line clock CKL or a clock GK that exactly corresponds to this, which the clock circuit TR together with signals ST or T "sends, can be entered. The signal Τη identifies the Channel D, the signal ST identifies the frame (A or B). The circuit ITD also contains a multiplexer PL which is controlled by the signals T 1 and ST and forms the messages mentioned in channel 0, while in the others Channels the data supplied by the serial-parallel converter SP are allowed through. The inputs of the multiplexer Mp are so with the

- 1D -

11066 / H / U CDB 45B)

Converter SP and the clock circuit TR (signals FAT, ALL) connected as well as with the slip control circuit of the elastic accumulator (signal SL). The output of the data DL is connected to the elastic store ME, to which the bits of each channel are fed in parallel. If requested becomes that the channel forming circuit ITD sequentially three or more messages is generated, the frame is identified by two or more bits of the signal ST.

The processing units and / or management units are very often duplicated in systems of the type under consideration and work according to the master-slave method in order to increase the reliability of the system and to ensure uninterrupted operation. In the event of minor changes, as can be seen in FIG. 3, the interface UL is able to work between a PCM system and two terminals T ₁ and T ″. For this purpose, it is sufficient to connect the channel formation circuit ITG and the memory parts MED, MEI of FIG. 1, ie a first memory ME .., a second channel formation circuit and a similar second memory ME _? to connect in parallel. The data DL. or DL "and the addresses I are entered into both memories ME ₁ , MEp on the basis of the same write signal lii (or write signal groups). Each memory is provided with its own slip control circuit and each assigned to a terminal from which it _{receives the read commands R 1} , R "and to which it sends the data DT and the corresponding addresses IT. The input data DE ₁ , DE "and the transmission clock ' _{CKT 1} or CKT" are connected to the inputs of a third multiplexer M, which is controlled by the master-slave criterion M / S and the transmission control circuit CT the data DE and the Send clock CKT delivers.

The messages entered into channel 0 by the two channel-forming circuits ITO differ only in the slip information according to the signal SL, which each channel-forming circuit receives from the memory allocated to it. If this information SL is not required, DL ₁ = DL "= DL, and the presence of the second channel formation circuit is unnecessary.

According to a possible embodiment of the invention, the interface is able to notify the terminal T of the amount of the phase shift α ψ between the line clock CKL and the transmission or transmission clock CKT regardless of the slip. For this purpose, for example, at least some of the bits Y ₁ to Y _{fi of} the message entered in frame A by the circle ITD can be used.

11066 / H / V (DB 458)

K in the figure, a particularly simple circuit is shown to measure this phase shift δ Ψ. It is a counter C, which is enabled for counting by a signal MT, which is generated by the transmission control circuit CT or by the terminal T and is linked to the transmission clock CKT, and is blocked by a signal ML which the clock circuit TR supplies and is bound to the line clock CKL. If the frequency of the signal F for advancing the counter C and the signals ML and MT is selected in an expedient manner, the bits which represent the phase shift Δ ^ can be taken in parallel from the cells of the counter itself.

Only as an example it is assumed that the read signal of one of the k registers which form the data storage part MED is used as the enable signal MT and that the write signal of the relevant register and the signal F have twice the bit frequency as the blocking signal ML. If the two clocks CKL and CKT in phase, so the nchreihainnai ties on riüß Zeitnhstandes middle coat (32 bits) between two aufeinuntjerfni qenden l.nsesiqnalen and dei ^v C counter 32 counts pulses. It should be noted that according to this solution the counter C counts a certain number of pulses in each case. The terminal T regards the line clock CKL as leading or delayed compared to its internal clock CKT, depending on whether more or fewer pulses than 32 are counted. The signals MT and ML can exchange their functions within the scope of the invention.

Claims (1)

DR. DIETER V. BEZOLD DIPL. ING. PETER SCHÜTZ DIPL. ING. WOLFGANG HEUSLER MARIA-THERESIA-STRASSE 22 PO Box 86 02 60 D-8OOO MUNICH 86 APPROVED BY THE EUROPEAN PATENT OFFICE EUROPEAN PATENT ATTORNEYS MANDATAIRES EN BREVETS EUROPEENS TELEPHONE 089/4 70 60 TELEX 522 638 TELEGRAM SOMBKZ 11DS6 / H / U (D8 458) ITALTEL Societä Italiana Telecomunicazioni s.p.a. Piazzale Zavattari 12, Milan / Italy Interface of a data transmission system Claims Interface between a PCM system and one with time division multiplex working terminal of a data transmission system in which the Terminal with a given send clock (CKT) delivered data (DE), possibly including loop commands for loop connection contained in channel 0 of the transmitting section with the receiving section as well as remote monitoring messages, according to a prescribed code on the line of the PCM system and in the channel D of each frame internationally standardized words A and B are formed and by the line that is provided with its own interface (IL), data are received with a given line clock (CKL), in particular for a PCM exchange for switching through telephone and data signals, POSTSCHECK MÖNCHEN NO. 69148-SOO BANK ACCOUNT HYPOBANK MÜNCHEN (BLZ 70 200 40) KTO. 6 060 257 378 SWIFT HYPO DE MM 11D66 / H / V (DB ί * 58) marked by a transmission control circuit (CT) which, after receiving the data to be transmitted (DE) and the transmission clock (CKT) from the terminal (T), forms the guard A or B and inserts the data changed in this way into the channel D of each frame encoded before they are sent on the line, and in channel D of the data to be transmitted (DE) recognizes the loop command or the remote monitoring message and forms a corresponding loop signal (L) or remote monitoring signals and transmits them to the line; a first multiplexer (M ₁ ) which is controlled by the loop signal (L) and has one input connected to the output (SLJ) of the transmission control circuit (CT), while its other input (SE) is connected to the interface (IL) of the line ; a decoder (DEC) connected to the output of the first multiplexer (M ₁ ); a circuit (EC), which from the data coming from the PCM line the Line clock (CKL) wins; a clock circuit (TR), the line clock (CKL) and the decoded Data (DD) receives and each channel of the PCM frame an address (I) allocates; a write signal (W) for an elastic memory (ME) generated; detects a loss of frame synchronization and a corresponding one Alarm signal (FAT) for the transmission control circuit (CT) and for the terminal (T) generated; and malfunctions of the PCM connection and the Interface (LJL) detected and the terminal (T) corresponding alarm signals (ALL) transmitted as well as an alarm signal sent from the remote terminal (STL) reports; a channel forming circuit (ITD) controlled by the clock circuit (TR) is and in the channel D of each frame of the decoded data (DD) of he enters generated messages that are to be forwarded to the terminal (T); and an elastic memory (ME), which on the basis of the write signal (W) the data (DL) supplied by the channel formation group (ITO) and their assigned addresses (I), sends them to the terminal (T) on the basis of a read signal (R) generated by the terminal (T) (DT, IT) and in the event a slip generates a corresponding signal (SL) for the terminal (T). 11066 / H / U (DB £ * 5Β) 2.) Interface according to claim 1, - because you r'ch characterized, that the alarm signals (FAT, ALL), which are generated by the clock circuit (TR), as well as the signal (SL), which from the elastic memory (ME) as Slip information is generated, fed directly to the terminal (T) will. 3.) Interface according to claim 1, characterized in that that the alarm signals (FAT, ALL) generated by the clock circuit (TR) and that generated by the elastic memory (ME) as slip information Signal (SL) are fed to the channel formation circuit (ITD), which they der Terminal (T) transmitted via the messages that are in channel O of each frame are included. <+.) Interface according to claim 1, 2 or 3, characterized in that that the channel formation circuit (ITO) contains a series-parallel converter (SP) which is connected to the output of the decoder (DEC) and controlled by the line clock (CKL), and a second multiplexer (M ₂ ), which with a part its inputs is connected to the series-parallel converter (SP) and, depending on a signal (T _n ) generated by the clock circuit (TR), generates the messages to be transmitted to the terminal (T) during channel D of each frame , and that the outputs of the second multiplexer (M ") are connected to the elastic store (ME). 5.) Interface according to claim 4, characterized in that that the channel forming circuit (ITD) is able to sequentially at least to generate two types of messages when responding to a signal (ST), which is supplied by the clock circuit (TR) for controlling the second multiplexer (Mp). 11OS6 / H / V (DB 6.) Interface according to one of the preceding claims, characterized by Means (Fig. 4) to detect the amount of phase shift (A ψ ) between the line clock (CHL) and the transmission clock (CKT) and to report it to the terminal (T) via the channel formation circuit (ITD). 7.) Interface according to claim 6, characterized in that that the means mentioned are formed by a counter (C) which is through a first one linked to the send clock (CKT) or the line clock (CKL) Signal (MT) is enabled for counting and by a second, to the line clock (CKL) or the signal (ML) bound to the send clock (CKT) is blocked, and the output of which is connected to the second multiplexer (M "). B.) Interface according to claim 7, characterized in that that if the phases of the two clocks (CKL, CKT) match, the counter (C) a predetermined number of pulses (F) counts, and that a doubly unique one Relationship between the number exceeding or falling below the specified number The number of pulses counted and that of the two clocks (CKL, CKT) consists of qegeru'labove the cattle varelland b / ui. is lagging. 9.) Interface according to one of the preceding claims, characterized marked, that it is connected to two terminals (T ,,, Tr,) that work according to the master-slave principle, that parallel to the channel formation circuit (ITD) and to the elastic memory (ME ,,), which from the read signal (EL) the first terminal (Τ.) is controlled, a second channel formation circuit (ITO) and a second elastic memory (ME ") is connected, which is controlled by a read signal (R ₂ ) generated by the second terminal (T_), and that a third multiplexer (M,) is provided, which is controlled by a signal (M / S), which indicates which terminal is working as master, and whose inputs the data (DE ₁ , DE ₂ ) and the transmission clock (CKT ₁ , CKT ₂ ) of the two terminals (T ₁ , Tp), while the transmission control circuit (CT) is connected to its output (DE, CKT).