DE3009530A1 - DATA PROCESSING SYSTEM - Google Patents

Description

Applicant: Digital Equipment Corporation, Maynard, Massachusetts / United States

Data processing system

The invention relates to a data processing system.

A digital data processing system generally has three Basic elements: a memory, an input / output unit and a processor. The memory stores information at addressable Storage locations. This information has both dates and commands to process the data. The processor transfers the information between it and the memory; the processor evaluates the incoming information either as data or commands and processes the data accordingly Command. The input / output unit is also available with the memory in connection to transmit input information to the system and to receive information processed by it.

Since the demand for computing power and speed for years

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age has risen is already proposed and it is also known to have multiple processors in one processing system to use. Typically, in such multiprocessor processing systems, each of the processors should have one have partial or full access to the same storage and input / output units »Consequently, facilities which prevent the processors from having access to the same unit at the same time. These are various arrangements are known. In a first arrangement, the processors are assigned priority waiting, whereby then processors with a higher priority before processors with a lower priority access the memory and Input / output units is permitted. This inevitably slows the round-trip time for programs that are in Units with a low priority circulate.

In a second arrangement, a computer circuit is provided with a host computer system to switch between a number subordinate or slave processors to decide. This decision can be made by factors such as the duration ρ the one Secondary processor access to the storage or input / output unit the time since the last access, etc. However, if the main system fails, that's because of it prevents the subordinate or slave processors from having access to the storage or input / output units until the main system has been repaired. Furthermore, there may be a bottleneck in the main system when the main system with respect to the access to the memory or input / output units must decide too quickly, so that the subordinate or secondary processors become slower.

In a third arrangement, there is a reciprocal control unit between the processors and the memory and memory Input / output units are provided to allow access between the processors and the storage and input / output units steer. However, this reciprocal control unit does not prevent the processors from working themselves, while

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rend they are waiting to access the storage and input / output units to have. Otherwise the same difficulties arise with this arrangement as with the one mentioned above Processing system with main and secondary processors.

As the demands on the computing power have increased further, more and more control information has to be exchanged between the various Go through units and parts of the system. For this purpose, there is also a number of control lines between the Units and parts required, reducing the cost of both the control line itself and the additional Electronic circuits that are required to evaluate information on the lines and information are increasing to accommodate on the lines.

The invention is therefore intended to be a multiprocessor data processing system create, in which the various central processors are prevented from simultaneously accessing the memory and the input / output units. Furthermore, a multiprocessor data processing system is intended can be created in which the various processors are prevented from accessing to other units in the system without a previously assigned priority or a main unit or a To use intermediate phase.

According to the invention there is provided a data processing system in which all connections between the various Units or elements on a single transmission path in the form of a single trunk or a single Bus. The trunk has lines for a decision, for an information transfer and to control. The information transmission part of the various units has a device for delivering a Command for a locking operation received by other processors in the system. This command prevents the other processors from issuing the same type of switch-off command until a switch-on command (un-

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locking command) is issued. Each processor can issue such a switch-on command. In connection with this Device only needs one line to be activated to indicate that the information transmission is intended Multiple lines are used instead of the usual number of lines between the various units or parts will.

According to the invention, a data processing system a number of data devices and a connection device on. The data devices have a first data device with devices for issuing commands, including a switch-off and a switch-on command. Each data device has switching arrangements that address these commands, so that when the first data device issues a switch-on command, it is prevented that In addition to the first data device, other data devices collect information about the connection device transmitted with a switch-off command until a switch-on command is issued by one of the data devices.

The invention is described below on the basis of preferred embodiments with reference to the accompanying drawings. Show it:

Fig. 1 is a block diagram of digital data

processing system according to the invention;

Figures 2A through 2C schematically illustrate types of data used in connection with a particular embodiment of the invention;

3 shows the lines and corresponding signals,

which is a connection for links in the digital data processing system show in Fig.1;

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Fig.4 a scheme in which the order

a read transaction is shown, which between the shown in Fig.3 Shortcuts can occur;

Fig.5 is a diagram in which orders

of operations for a read transaction between the links shown in Figure 3 can occur;

Fig. 6 is a schematic circuit diagram of a part

the main link shown in Figure 3 ; and

7 shows a schematic circuit of a part

a subordinate or secondary link shown in Figure 3.

For example, as shown in Figure 1, the Basic elements of a data processing system, in particular a multiprocessor system, a first central processor 10, a second central processor 10A, storage units 11, and input / output (I / O) units 12. A multiple line or a bus 14 connects the central processors 10 and 10A, the storage units 11 and the I / O units 12. In one Multiprocessor systems can also have more than two central processors connected to the multiple line 14. You would then connected to the trunk 14 in a manner similar to the processors 10 and 10A.

The central processor 10 has a control panel 15, a Coupling means for the trunking and other conventional circuitry normally found in the central processor are housed. The central processor 10A and other central processors connected to the trunk line 14 can be, correspond to the central processor 10;

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however, it is necessary that the central processors be coupled to a trunking or bus 14 can. A coupling circuit 16 receives all data from the Stores and carries out all transactions for the remaining circuits in the central processor 10.

The control panel 15 serves as a connection or coupling device for the operator. From here, the operator can check and file data, the operation of the Central processor 10 stop or by a series of program instructions advance step by step. An operator can initialize the system by a bootstrap and can perform various diagnostic tests on the entire data processing system. The central processor * 1 OA generally has a control panel (not shown) on.

In FIG. 1, the memory unit 11 has a memory control unit 20, which are connected to a number of memory fields 21 is. The operation of the memory unit 11 corresponds to that in the US patent application filed on 10/10/1978 S.N. 954 601 is described.

Various types of I / O units 12 are shown. An I / O bus adapter 22 connects multiple input / output devices 23, such as teleprinters or cathode ray tubes, with the multiple line 14. The connection and transmission s signals between the I / O bus adapter 22 and the input / Dispensing devices are described in part of U.S. Patent No. 3,710,324.

The two other I / O units 12 shown in FIG provide a secondary storage facility for the data processing system. You assign a secondary storage bus adapter 24 and a number of disk drives 25. There is also a second secondary storage bus adapter 26 and a belt drive 27 is shown. The connection of the seconds

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memory bus adapters 24 and 26 and their respective disk drives 25 and the belt drive 27 are described in US Pat. No. 3,999,163.

The multiple line or the bus connects the various units or parts of a data processing system. Before an information transfer between different pairs of the When describing units associated with the trunking, it may be useful to begin with some definitions of terms or introduce terms that have already been used and that will be used in the future.

"Information" is the intelligence that is used for control and creates the basis for data processing. she includes data and address as well as command and status information. The term "data" includes information which object or result of processing is. Transfers of information between the units in the data system shown in FIG. 1 take place via the multiple line 14 and complete transmissions of discrete information data words with a. Each data word has a characteristic length on the multiple line 14. Other units can be information data words process with other lengths. The simplest information data word is the byte. In a specific embodiment of the data processing system shown in Figure 1, the byte has eight binary digits (or bits). In Fig. 2A shows eight contiguous bytes. The next larger data word length is a "word" as shown in FIG. 2B is shown. A word has two contiguous bytes. Two related words form a "long word", as in Fig.2C is shown.

The trunk line 14 can transmit all information in parallel as a long word. In the two shown in Fig. 2A, related long words, byte 0 is the least significant byte position of each long word. The word 0 and that Longword 0 are the low-order word and longword positions

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in Fig. 2B and 2C, respectively. In the following description it is assumed that that appropriate alignments are obtained in the data processing system; however, there is no condition or requirement that any of these alignments be maintained.

When two entities are to exchange information over the trunk line 14, at least two transactions are over the multiple line, i.e. two "bus transactions" are necessary. During an initial bus transaction, a unit requests the Exchanges information and transmits command and address information to the trunk line 14. The other, through the Address information addresses certain element and prepares for information exchange. This is a first bus transaction ended. During the second bus transaction, the information to be exchanged runs over the multiple line 14th

Each unit connected to the trunk line 14 is called a nexus. The special, in The system shown in FIG. 1 has 6 links. A shortcut is determined in the form of their function during an exchange of information. During such an exchange the linkage which transmits command and address information to the multiple line 14 is shown in FIG "Main Link" designated 3OA. The entity that is responsive to this command and address information is called the "slave or sub-link "3OB. Thus, when a central processor receives data from the memory control unit 20 must find again, the central processor becomes a main link and transmits a read (or read enable) command and a memory address during a first bus transaction. The memory control unit 20 becomes a subordinate link, when it receives the command and address information from the trunk line 14 and takes it over.

A link is also called a sending or receiving

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Linking unit specified. A sending link unit controls the signal lines, while the receiving Linking unit scans and checks the signal lines during each bus transaction. The following example is the central processor provides a sending link during the first bus transaction and a sending link during the second bus transaction its receiving link. Similarly, the memory controller 20 is one during the first bus transaction receiving link unit and a sending link unit during the second bus transaction. Similar Transactions occur in an exchange of information between any other linking units. However act the storage control units normally only act as subordinate or subsidiary link units, while central processors usually act as main link units.

In the particular embodiment of the invention, the Multiple line 14 a number of signals to and from the various units, which via corresponding lines with her are connected. These lines and signals can be listed in three general classes:

1. A decision signal via decision line 31 the multiple line;

2. An information transfer over the data / address lines 32 and 33 of the multiple line; and

3. A control signal via control lines 34 to 38 of the multiple line.

Lines 31 to 38 form the multiple line 14. The data address or information transmission multiplex has information lines 32 and function lines 33. Commands are issued via function lines 33.

The control lines and signals have a status line 34, a hold line 35, a waiting line 36, and a DBBZ line 37 and a clock line 38. The status information shows

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whether the addressed memory location contains the requested information and whether the information is valid. The hold signal, when inserted on hold line 35, prevents that any links from the data / address trunk be controlled. Stop signals can be used, for example, to determine the speed in certain memories control with which write transactions occur.

The wait signal asserted and enforced on the wait line 36 includes interrupt transactions. The DBBZ signal or the data / address bus busy signal indicates when it is on the DBBZ line 37 is asserted and enforced when a link via the data address multiple line is a requesting or is sending information.

A number of commands are sent over the function line 33, namely read; Read disable, write, and write disable commands. When a logic unit issues a read command, it requests the content of a memory location to be read Address is transmitted over the transmission lines 32. A read disable command indicates that the commanding logic unit is requesting to read the addressed memory location and prevents other link units from using their own Disable read commands get access to the trunk until a enable enable command is given to the functional line will. The read shutdown command does not prevent another master link from issuing a read or write command issues. The read shutdown command is mainly used to prevent other processors or logic units from being used Have access to a memory in which there may be valid information, or possibly a read valid information. This is possible if the processor that originally issued the read shutdown command Has access to the memory and can modify information in the memory at the same time as another

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Processor tries to read them from the same memory. To prevent this, the first processor issues a read shutdown command thereby ensuring that other link units are prevented from gaining access to the memory.

As stated above, for each read and for write transaction two transactions over the multiple line, i.e. two bus transactions required. In Fig.4 and 5 are for the illustrated embodiment examples of a read and a write transaction shown. In Fig.4 and 5 are the positive (to be claimed) signals for simplification of the description as correct or claimed when they are high. Earthed stress control circuits and signals (i.e., which are asserted or correct when low) are usually complementary this logic. However, the conversion between positive and grounded logic, which is based on the so-called Morgan theorem, is lsi: known to the person skilled in the art.

FIG. 4 is an example of a read transaction between two link units shown in FIG. The clock pulses characterize and limit the various cycles on the trunk, with a new cycle beginning on the leading edge of each positive going pulse. If the main connection unit wants to use the trunking in order to read from a subordinate connection unit, for example a memory, the main unit asserts its priority signal on the decision line 31. If its priority is the highest, and if the Halte7 and DBBZ lines are all at unclaimed level I ¹ ± gen, the main unit gets control of the multiplex mg 14 by d. DBBZ-i, as at time B in

Fig.4 is shown. The main unit claims for one Cycle the D3BS line. -And transmits at the same time Address and control information on the data / address line 32 and 33. The main unit then shifts the DBBZ signal

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BATH ORIGINAL

to an unclaimed level.

The addressed slave unit claimed _VO m time C to time D t he DE3S line., As shown. No other link unit can then receive control on the multiple line as long as the subordinate unit uses the DBBZ line. When the slave unit is ready to transmit information to the master unit, the slave unit shifts the DBBZ signal to an unclaimed level and, as shown from time D to time E, transmits the information on the data / address line and simultaneously status information is returned on the status line 34.

Since the DBBZ line is no longer used after time D. another master may attempt control of the trunk during the beginning at time D. Cycle. During this cycle it can then assert its priority signal and the DBBZ line claim during the cycle beginning at time E to transfer an address and control and to obtain a new one To begin transaction. This allows transactions to overlap in a cycle, reducing transaction time. In other words, it can while More accesses to a memory are attempted in a given period of time than if the transactions are on the trunk do not overlap. This overlap is shown in part by the status signal in FIG. The left one the most significant status signal that was emitted during the cycle immediately following time B for example from a previous transaction.

This then makes both the main unit and the subordinate unit Unit asserts a DBBZ signal on the same line, thereby increasing the number of lines in the trunk (i.e. the bus lines) is reduced. The practice has been to provide a number of busy lines to indicate that the

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Multiple line is in use. By reducing the number of busy lines, the total number of lines in of the multiple line and, as a result, the circuitry required to drive that line can be reduced in size.

A waiting transaction is shown as an example in FIG. A master that desires a wait transaction asserts its priority signal via arbitration line 31. When the hold and DBBZ lines are both at a so-called unclaimed level and the priority of the master is the highest, it gains control of the DBBZ line and claims the DBBZ line. It then simultaneously transmits address and control information to the data / address line for one cycle. The addressed subordinate unit uses the DBBZ line _and receives the signals on the data / address line. At the beginning of the last cycle, the subordinate unit shifts the DBBZ signal to an unclaimed one. Level and transmits status information on the status line 34. The last cycle then begins at time D. Since the DBBZ line is low, another master can assert its priority signal, even if the hold and wait lines are not claimed

it can get control of the main line by claiming the DBBZ line at time E.

In Fig. 6 and 7 are examples of circuits for a main and subordinate unit shown to route the DBBZ between claimed and unclaimed levels to move. The main unit circuit 50 shown in FIG. 6 provides a means for preventing the Main connection unit 30A is given access to DBBZ line 37 with a read shutdown command if another main unit has previously issued a read switch-off command that is not switched on or unlocked by a write switch-on command has been.

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The circuit 50 has a command decoder 51 which controls the circuit in accordance with a command such as read, write, like switching off reading and switching on writing, actuated. When a read disable command is issued, the decoder issues 51 a high input to a NAND gate 52 and a high input to an AND gate 53. If, as described below, the second input of NAND gate 52 is low the output of NAND gate 52 is high, and when the hold signal is low (not asserted) when the arbitration line main unit is high (indicating that main unit has priority) and when the DBBZ line is continuously low (is not used.), is the AND gate 53 output high. At the next clock pulse from a clock generator 54, the set output becomes a D flip-flop high, shifting DBBZ line 37 to a high (claimed) level. An inverter 54A then makes the output of AND gate 53 low. With the next clock pulse the flip-flop 55 is reset, whereby the DBBZ line is shifted to an unclaimed level. As a result, the main unit claims the DBBZ line for one cycle for the time between the first two clock pulses.

The circuit 50 has an AND gate 56 and a D flip-flop, which the first cycle of a transaction of the main unit designated via the multiple line. Before the flip-flop 55 claims the DBBZ line, the reset output is activated of the flip-flop 57 as well as the one input of an AND gate 56 high. When the flip-flop 55 claims the DBBZ line the second input to AND gate 56 goes high and its output also goes high. The next clock pulse will flip-flop 57 is set, its reset output goes low and thereby AND gate 56 goes low. The AND gate 56 is therefore only high during the first cycle otherwise called the address cycle.

The circuit 50 has a JK flip-flop 58 which the transaction on the trunk recognized by this

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special main unit is initiated. When the output of AND gate 53 goes high on the next clock pulse, will also the set output of the JK flip-flop 58 is high (and its reset output becomes low). By having the set and reset outputs of flip-flop 58 go high and low, respectively the transaction initiated by this master unit is displayed.

The circuit 50 also has a second JK flip-flop 59, that recognizes when a read switch-off command has been issued on the function line and when a write switch-on command has been issued is. The flip-flop 59 also recognizes when the previous read disable command has been output through this particular main unit. When this main unit receives the read shutdown command has issued does not prevent another read disable command from being issued. With the flip-flop 59 is accomplishes this in the following way. If a read shutdown command on function line 33 during an address cycle is accommodated, inverters 6OA decode the command on the function lines and set the function inputs at the AND gate 60 high. This causes the output of AND gate 56 to go high. When the read disable command from the circuit 50 is no longer output, the reset output of flip-flop 58 goes high. Consequently, the output of the AND gate 60 high, and on the next clock pulse the set input of JK flip-flop 59 goes high. When the set output is high and when a read disable command is decoded by the decoder 51, the NAND gate 52 is driven low and circuit 50 cannot claim the DBBZ line. The set output of the JK flip-flop 59 stays high until the K input is driven high on a clock pulse. This is the case when a switch-on wait command occurs during an address cycle is output on the function line. The inverter 61A decodes this command and sets the functional inputs of the AND gate 61. During the address cycle the output of AND gate 56 which drives the output of AND gate 61 high. This causes the flip-flop 59 to reverse

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set and its set output low. The flip-flop remains reset until it is set again by a read switch-off command will. When the set output is low and when a read disable command is decoded by decoder 51, a the NAND gate 52 high so that the circuit 50 can claim the DBBZ line.

If, on the other hand, the circuit 50 issues the read disable command, the reset output of the flip-flop and the output of the AND gate 60 low. The flip-flop 59 thus remains reset and its set output goes low. The NAND element 52 passes a read disable command when the output of flip-flop 59 is low, which can only occur when the previous read disable command has been issued by circuit 50, or when this command has been issued by the write enable command has been invalidated.

In Fig.7 is an embodiment of a circuit 70 for a subordinate unit for controlling the DBBZ line is shown. When the main unit has address information outputs the data / address line, an address decoder 71 decodes the address and identifies this link unit as the addressed slave or slave unit. The decoder 71 has one input of an AND gate 72 connected, the output of which is connected to the J input of a JK flip-flop 73 is connected, which controls the DBBZ line 37. The DBBZ line 37 is in turn with an AND gate 76 and the D input a flip-flop 77. The reset output of the Flip-flops 77 are connected to the other input of AND gate 76. The output of the AND gate 76 is with the second Input of the AND gate 72 connected. The flip-flop 77 is identified the first (address) cycle of the transaction on the trunk in a similar way to the AND gate 56 in circuit 50 is successful. The address cycle is claimed for one cycle, whereupon it is shifted to an unclaimed level. When the address cycle is claimed, the flip-flop 73 controls the DBBZ line

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37 at. During the subsequent clock cycles, the address cycle and AND gate 72 low, but flip-flop 73 remains on (or claimed) until, as below, the information is ready to be posted.

A command decoder 78 in the subordinate logic unit detects when the data is ready to be transmitted over the data / address line to be transferred; the data ready line H would go high, thereby resetting the flip-flop 73 and the DBBZ line 37 would be brought low. This drives the output of AND gate 76 low, which in turn drives the output of AND gate 72 low. The flip-flops 73 and 77 are both activated by the clock 54 controlled.

According to FIG. 6, a read switch-off command is issued for a write transaction from the command decoder 51 is not output. The read shutdown line goes low (unused.) so that the logic unit can write whether or not there is a read switch-off command on the function line not. The memory request line H is used for a read transaction, whereby the AND gate 53 is driven high and the flip-flop 55, which controls the DBBZ line 37, is set. The subordinate or subsidiary unit claims at a write transaction the DBBZ line in a similar way like a read transaction. The slave unit controls the DBBZ line 37 until it receives a command that indicates that the next cycle is the last cycle. The command decoder 78 of the slave unit then controls the data ready line H high, resetting flip-flop 73. Status information is then provided by the subordinate unit transmitted to the main unit via the status line.

End of description

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Claims (3)

Applicant: Digital Equipment Corporation, Maynard, Massachusetts USA Claims M, data processing system with a number of data devices, which has a first data device and a device for connecting the data device to a number of devices, to transmit signals between the data devices, wherein the first data device comprises means for issuing commands to the connecting device, which commands include a shutdown command to the first data device Can transmit information on the connection device and to prevent other data devices from receiving information transmitted on the connection line together with a switch-off command, and which commands include a switch-on command, so that the other data devices transmit information together with a shutdown command to the connection device can, characterized in that each of the data devices a switching arrangement (59, 60, 61) which is connected to the connecting device, which is responsive to a shutdown command responds, which has previously been output by the first data device in order to prevent the corresponding Data setup information with a shutdown command 030039/0781 ORIGINAL INSPECTED transmits to the connecting device, and that each of the switching arrangements (59, 60, 61) responds to a switch-on command, which has been output by a data device, so that a data device sends information to the connection device can be transmitted if the switch-on command is more recent than the previous switch-off command. 2. Data processing system according to claim 1, characterized in that each of the devices on responsive to the shutdown command comprises a command decoder (60, 60A) connected to the connector is to include commands from this, on the further with the corresponding switching arrangement is connected to set the switching arrangement when a shutdown command is given by the corresponding command decoder (60, 60A) is decoded. 3. Data processing system according to claim 1, characterized in that each of the devices on responds to a switch-on command, comprises a command decoder (61, 61A) connected to the connection device is in order to receive commands from this, and which is also connected to the corresponding switching arrangement to the Reset switching arrangement when a switch-on command from the corresponding command decoder (61, 61A) is decoded. 030039/0761