DE3001588A1 - DIGITAL VIDEO CORRELATOR - Google Patents

Description

Digital video correlator

There are types of optical image correlators by which a living or real scene can be correlated with a reference image in such a way that an output signal that shows the degree of correlation between the two. These optical image correlators were generally in guide system for Airplanes, projectiles or the like. Used. For the state of the art, see US patents 3,723,717; 3751,705; 3,748,042; 3,496,290; 3-514,535; 3-564,126 and 3,609,762, all of which are optical Show image correlator, in which a photocathode converts the light, which on it a corresponding electron beam which passes through a vacuum tube for storage on a storage grid. The electron beam is focused on the storage grid by an electromagnetic coil or the like, ^ icht next to the storage grid there is a collection screen to a secondary mission to take from this.

With the reference image stored in this way, a living Image converted into an electron beam and directed to the storage grid. This electron beam will nutated by means of electromagnetic bending in such a way that the living image is nutated over the reference image that is on is held in the storage grid. The electrons that pass through the grid are scanned at an anode, some directly on the degree of correlation between the living input image and the reference image on the storage grid is related. A further detailed understanding of the prior art can be obtained from the above Pamphlets are taken.

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While the approximation of the prior art in general is sufficient, there are certain problems. This is how all the problems that arise in connection with vacuum tubes occur arise when using such correlators. The inaccuracies in the use of magnetic Deflection coils for nuting focusing were just difficult and expensive to circumvent or overcome. A susceptibility of these systems to damage caused by shaking or shaking their operational Environment always exists. The previous teachings have used a full analog technique in correlating and suffered from corresponding inaccuracies. In general, the prior art has suffered from a lack of a correlation device and a technique for the optical image a digital solid state.

It is therefore an object of the invention to provide a digital video correlator indicate in the case of digitized video data that is both a reference image and an actual one Display image, can be used in a correlation method. This video correlator is supposed to be digitized data can process in seal time, with the disadvantages of electromagnetic data shifts due to solid state shift registers avoid moving the data digitally. This correlator can be used to operate either can be used in the multi-level product type or in the multi-level difference type. He also leaves no harmful Effects or physical shocks, vibrations, temperature changes, contrast reversals and the like. The correlator is simple in construction, reliable in operation, relatively inexpensive and light to be used with available components.

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These and other objects of the invention result from the description of a digital video correlator for the comparison of a real image with a reference image with the following components: a digitizer for dividing the life image and the reference image into images and digitizing this in fixed voltage values, shifting devices, those with the digitizing devices for successive recording of the digitized images of the real ones Pictures; and

a correlator connected between the digitizing device and the displacement device successively for recording and for holding the image portions of the reference image and capturing the digitized images of the real image from the shifting device, the correlator comparing the corresponding image parts of the real and the reference image with one another and delivering an output signal, that shows the correlation between them.

The drawings serve to understand the techniques and the structure according to the invention. In these is:

Figure 1 is a functional diagram of the digital video correlator system according to the invention;

Figure 2 is a circuit diagram of a binary video processor that can be built into the system of Figure 1 and digitized analog video input signals;

Figure 3 is a schematic of the dynamic memory relationship and the digital correlator according to the invention;

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Figures 4A and 4-B show schematically the correlator logic for one bit of video data or a table of operation;

Figure 5 is a functional diagram of the relationship of a Reference image shift register, the real image shift register, a cover shift register and the one-bit correlator of Figure 4-A;

FIG. 6 shows the block diagram of a correlator according to the Teaching the invention of the in the manner of surplus value difference correlation is working; and

FIG. 7 shows the block diagram of a correlator according to FIGS Teachings of the invention operating in the value-added product correlation mode.

The digital video correlator 10, as shown in Figure 1, has a video source 12 of a suitable type, for example a TV raster scanner, Radar or the like., The analog video data to a bi-valued video processor 14- is. During the Processor 1A- will be described in detail later, we are told that he will digitize the data in such a way that analog heights falling above, below or into certain values are determined accordingly by fixed output states. The digitization of the analog signal can be done using a known device in a manner which is explained in connection with FIG. In general becomes a running average of the incoming real one Image kept and constantly brought up to date. Discrete image parts are digitized and from a or several fixed values of digital data accordingly

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the respective partial image relationship to the running mean or average value of the incoming real image shown. The output of the video processor 14 is fed to a dynamic memory 16 which has a plurality of shift registers which can shift several data bits in parallel to the parallel bi-valued correlator 20. The correlator 20 also feeds a bi-valued reference source 18 which again holds digitized data of a reference image on a partial image basis. Between the Correlator 20 and the reference source 18 and the processor 14 is a switch 21, which controls whether the relationship for the correlation of a real image supplied by the source 12 and by the processor 14 or by the bi-valued reference source 18 is to be digitized. The reference source 18 consists of several shift registers or can also consist of a magnetic tape, the successive digital data of image parts of the reference image wearing. Image data from the correlator 20 can also be sent via the line 23 to the reference source 18 for storage will.

As will be explained, the correlator 20 compares the real image of the dynamic memory 16 with that Reference image obtained either from reference source 18 or from video processor 14. In any case, the digital ones Correlations are established on a per-image basis by the correlator 20, each image correlation being one Fixed amplitude output generated. The correlation output for each reference image portion is compared with each Image portion of the real image is summed via a current summing switch 52 and sent to the lane check stop logic 22 given, which, as the skilled person understands, a standard

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Test and hold circuit 27 can have the outputs maximum amplitude of the! Correlator 20 is sampled and recorded. The circuit 22 also includes a counter, which is fed by a clock circuit 23, which also controls the dynamic memory 16. The counter is in turn connected to a register 29 which is owned by the Test and hold circuit 27 is switched on. When the circuit 27 from the correlator 20 and the current summing switch 52 detects a new high value, the register 29 can record the count of the counter 25 and thus holds the location address of the highest degree of correlation achieved by the correlator 20. The test and Holding circuit can thus also feed a comparison device 31, which determines whether the highest from the correlator The degree of correlation provided is actually a comparison between the reference and the real picture.

! FIG. 2 shows a video processor 14 using a Hull mean filter 24 which receives the multivalued video input signal Ai from the video source 12. The filter 24 generates a running average of input Ai over the time constant of the filter. This average is denoted by Xi, so that the output of the high-pass filter 24 is the zero-center1 video signal Ai-Si. The circuit 26 generates the standard deviation of the input video signal Adding the absolute value of Ai - A "i to the time constant of the filter. This standard deviation is applied to gain control circuits 28, 30, which have corresponding preselected degrees of gain of K1 and K2. The reinforced Outputs of the circuits 28 and 30 are applied accordingly to the comparison circuits 32 and 34, which receives the Mull-Mittel video signal Ai-Ii from the high-pass filter 24 as second inputs.

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BATH

The correlator 20 operates on video data in binary Shape. The video data can be in a bi-valued or multivalued format. In the video processor 14 after In FIG. 2, the comparison device 32 generates a positive one Output only when the zero-mean video signal Ai-Ii is greater than K1 times the standard deviation. The comparison device 34- produces a positive output only when this signal is less than -K2 times the standard deviation. The circuit of Figure 2 can thus be a analog input signal with respect to three values for three-value correlation mark. This identification can be transferred into binary form via the AND gates · 13 »15. When the AND gate is switched on by the clock, each clock pulse determines a part of the image, whereby the output of gate 13, for example, the smallest valid bit of the binary value of the image part and gate 15 the most significant Bit builds up.

For the bit-valued correlation, the circuit according to FIG. 2 only has to be modified slightly so that K1-0 and K2 -OO . In this case, P2i will always be a logical zero (the highest bit) and P1i a logical one if Ai is greater than Ii and otherwise a logical zero. In this case, a single bit of binary data P1i is necessary for each picture part.

When using an infrared sensor (IE) to obtain the video data signal for the real picture on the system it is desirable to have the video processor 14 for contrast reversals is made insensitive. Because IR sensors are temperature sensitive can be a contrast reversal in a Change in ambient temperature, rain and the like.

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step. By supplying the outputs of the AND gates 13 and 15 to the exclusive-OR gate (EOE) 17 - shown in dashed lines - the circuit according to FIG. 2 can be in a bi-valued manner Work wisely while unaffected by contrast inversions. In this situation is the output of gate 17 is a logic zero when Ai-Si between K1 times the standard deviation and -K2 times the standard deviation while it is a logical one at all other times.

Before the detailed description of the circuitry of the system 10 the correlation functions are to be considered. When working on bits of binary data, the invention results basically the following bi-valued function:

Equation 1

Ci

Where 0 is a correlation function, Ai the bit-i of η bits, Bi the bit-1 of η of these bits and Ci the bit-i of a cover or Is the gate function that belongs to every bit A and B. The equation simply says that the correlation function for η-bit of the data from PeId A when comparing with n-bits of the data from field B on a bitwise basis as chosen by the value of C equal to the sum over η of the Α-field and the B-field, which is logically led with the C-field via an AND gate.

The correlation function for the absolute mean difference (MAD) is given by equation 2:

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0 = / Ai-Bi

BATH ORIGINAL

ti k. V - - -

Equation 2

MAD

i = 1

Ai-Bi

Ci

y Gi

i = 1

When the G-field or the C-frame determining the function initiates, in which the bits of the Α-field and the B-field are to be correlated, the absolute mean difference can be used (MAD) easily by dividing Equation 1 by the sum of Gi over the field of η bits in Equation 2 to be determined. The summation of Ci can thus be derived from the Equation 1 can be obtained by setting either field A or field B to ones, the other being Field is set to zeros. Then the correlation function of equation 1 is formed.

Using fields A, B and C can result in a summation of the product correlation, which is the correlation function of equation 1 is used by setting field B to zero, thus a product correlation 0p results of equation 5:

Equation 3

AiCi

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The correlation function 0 _A for the opening can be derived from the correlation function of equation 1 by setting the B-frame to zero and the C-frame to one, as results from equation 4:

Equation 4

n
Z

Knowing the opening correlation function 0 ^ and the Product correlation function 0 can be an opening for get a normalized product, as equation 5 shows:

Equation 5

η
\ AiOi

0 _N. «= I

0A η

Ai

i - 1

The correlation technique can be used to perform the above Algorithm with the multi-valued inputs of A, B and Q, through appropriate coding, scaling down and bit splicing of the data are formed.

I ^{1 For} this consideration, in the case of a two-bit, the three-valued MAD becomes equal to 6:

1 3 0 030 / OA 1 1 " ¹⁸ "

Equation 6

IiAD

- ΣΙ

i = 1

Ai2-Bi2

Gi

Oi

where Ai2 and Bi2 are the highest value bits of the elements Ai and Bi are respectively, while Ai1 and Bi1 are the lowest value bits. The equation becomes from the equation 2 derived if the data are encoded according to Table 2.

• Q A. 2 0101 Table 1 0 0010 -2 JD 0 0000 3 1010 0101 1 1 2 2 4- 0001 2 0001 1 1 3 2 0000 3 1 O O 2 1 0010 4th 0 1 .1 1 0 1010 1 2 0 -1 2 -2 3

Table 1 shows the correlation relationships between data A and data B for five values. If A and B insist on pentavalent data, the correlation function 0 is given by the whole table. If A and B consist of four

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If there is any significant data, the part of the table containing the values of A and B from -1 to 2 is used; and A and B consist of three binary bits each. With the trivalent Correlation, this part of the table is in the area where A and B are between 1 and -1 and consists of two bits consist of binary data. Finally, the table for the two-valued correlation puts where A and B are either Are zero or one and are expressed by a single bit of binary data.

A multi-valued correlation of two-bit data can be obtained in the same way as single-bit correlation, the need for hardware increases. When the elements to be correlated are represented by binary elements of each Q-bit the possible number of correlation values is Q +1 when A and B are encoded to match the equation 1 suffice for several values.

The sum of the production for a two-bit input correlation on A and C (B is made zero) is by the Given equation 7:

Equation 7

Xü.2Ci2 + 2 (Ai2Ci2) + 2 (Ai2Ci2) + 4 (Ai2Ci2) i

Table 2 shows this correlation:

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σ K1 Al C1 Table 2 Ä2 01 Κ2 Α1 02 Κ3 Α2 02 0Ρ A. 0 1 O O Κ2 O O 2 O O O O O O 0 1 1 O 2 O O 2 r O ' 4th O O O 1 0 1 O O 2 1 O 2 O O 1 O O 2 0 1 1 O 2 1 O 2 1 O 4th 1 O O 3 1 1 O 1 2 O 1 2 O O O O O O 1 1 1 1 2 O 1 2 1 O 4th O O 1 1 1 1 O 1 2 1 1 2 O O 4th 1 O 2 2 1 1 1 1 2 1 2 1 O 4th 1 O 3 3 2 1 O O 2 1 1 2 O 1 O 1 O O 2 1 1 O 2 O O 2 1 1 4- O 1 2 1 2 1 O O 2 1 O 2 O 1 4th 1 Λ 4th 2 2 1 1 O 2 1 O 2 1 1 4th 1 1 6th 3 2

03101 201 201 401 0

13111 201 211 401 3

23 101 2 11 201 411 6

33111 211 211 411 9

Pur the previous Pall of a two-bit input product correlation the opening function 0 »is obtained from equation 4 to:

Equation 8

η
0Α =;> ( ^{Ai1 + 2} ^ ² )

A multi-valued product correlation that is based on the opening

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normalized for a two-bit input can thus by dividing Equation 7 by Equation 8 can be achieved as shown in Equation 5. The EeId -C can work as a cover or trigger field and result in the data to be treated with the correlation technique. Furthermore, the product correlation technique can easily extended to the inclusion of many values only by doubling the equipment necessary for the two-value system will. For example, in the case of a multi-valued product correlation, the necessary

Number of correlators Q, in which a particular embodiment of the invention is shown. The number of values achieved is 2 ^.

FIG. 3 shows a special embodiment of the invention in which the dynamic memory 16 has N shift registers of M bits each, which are interconnected and the data is controlled by pulses from the clock 1 of the clock circuit 23 push through. The data supplied to the memory 16 contain the digitized image parts Pi of the video processor 14 after Figure 1. Correlator 20 includes three sets of N shift registers of each IT bit for receiving and storing the digital Data of the reference image parts Ri, the digitized data of the real image parts Pi and a control cover. The three sets of shift registers are called Α, Β and C registers and satisfy the algorithms mentioned.

The Α shift register of the correlator 20 comes from the Data gate 36 "which, as you know, one of four entrances can deliver to the output under control of address lines. According to Figure 3, the data gate 36 can be sent to the A register either a logical 1 from the + V source, a

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logical O from the basic source, the digitized reference image Ri from the reference source 18 or a covered reference image supply, via the AND gate receiving the inputs from the cover generator 42 and the reference source 18 44 is coming. The data bits given by the data gate 36 are subtracted from the Α shift register on a bit-by-bit basis Control of the clock generator 2 of the clock generator circuit 23 is recorded, shifting the data in series through the A registers until the entire register is loaded.

The B shift register of the correlator 20 receives data via the data gates 38 which are similar to the gates 36 leading to the Av register. The data sources available to the B registers are logical ones from the + V source, logical zeros from the basic source and the digitized data bits corresponding to the image portions of the real image as supplied by video processor 14 and in the Ή M χ 1 -Shift registers of the dynamic memory are kept. The video data of the real picture are thus shifted into the shift registers of the memory 16 under the control of the clock generator 1 and the same thing happens in series. If (however, this data of the real image is to be shifted into the processor 20, this is done in parallel to each of the N registers of the memory 16, which is entered through an associated data port 38 and into a corresponding B register 20, also under the control of the clock generator) 1 leads.

Correlator 20's G registers are through the data gates 40 with either a logical 1, which is via the + V source is supplied, a cover that is supplied via the cover generator 42, or data of the real image, which come from the dynamic memory 16 is supplied.

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If the -C registers just a cover from the cover generator 42 to record, this can be done under control of the clock 2 in series, with the output of C register N-1 through data gate 40 leads. The C registers can also be loaded in parallel, e.g. by loading all logical ones via the + V input or by loading the data of the real image from the dynamic memory 16 and through the associated AND gates 44 under control of the Clock 1,

The interconnected respective bits of each of the A, B and G E registers of the correlator 20 result in several logic correlator circuits 46 of Figure 4A. An Exelusiv-Oder-Tor (EOR) 48 exempts an entrance a bit from the Α register and a corresponding bit from the B register. The output of the EOR gate 48 arrives to a standard AND gate 50, which serves as the control input for the respective Takes bit from the C register. Circuit 46 then functionally forms the Boolean operation of (A 0 B) .C according to the table in FIG. 4B. From this it follows that when the respective bits A and B are the same are, the output 0 is at a logical zero, while the inequality between these bits of a logical One thing is noted. If the C input is a 0, 0 is a zero regardless of the correlation or Inequality between the corresponding A and B bits.

Complementary logic could easily be used to achieve a desired correlation technique, which is compatible with their teachings. The application of complementary logic to the invention is considered to be within the

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Opportunities considered by those skilled in the art and this is just a variation on the basic theme of the preferred described embodiment.

The connection of the single tBit correlation circuits 46 with the A, B and C registers is shown in FIG. Their outputs are interconnected and surrendered together a current summing switch 52 or another corresponding summing circuit, which the correlation aggregate between the respective bits of the A, B and G register indicates. If a single bit correlator circuit 46 belongs to each of the N bits of the A, B and C registers,

the current summing switch 52 receives N signals common to each other and determine the degree of correlation between the data in the A and B registers when they are dated C registers are covered. The table in FIG. 4B shows that the output signal of the current summing switch 52 is kept as small as possible for the largest number of correlations. That is, the correlation signal output the summing circuit will have a negative going pulse, this pulse having a minimum value at the point of maximum Correlation hits. This is the output signal from the test and hold circuit 27 of the circuit of FIG 1 is scanned.

The invention is used in guidance and control systems in which a real image is compared with a reference image, where the degree of correlation between this indicates whether the system is working on a target. As for describing a single bit correlator circuit according to ^ igur 4A, provide the C registers a trigger input to the Uhd gate 50 and thus serve

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BAD ORIGINAL

as a cover for the operation of the single-bit correlator circuit 46. The cover held in the C register dials by switching on the various Single-bit correlators 46 select the portion of the reference image, which is to be compared with the real image and then cause the output of the correlator 20. Then the shift register C provides such an adjustment aperture that it can be used as a field of view of the real image as a floor or the like. Smaller, which uses the system 10 close to its target. This part of the reference image, that is necessary for guiding becomes smaller in the same way and the cover serves to isolate the part of the reference image, which is important during the closing. While it is not important to the invention that at the same time With the closure, a different downsizing of the images is necessary, the field of view is smaller and the real goal gets bigger. Similarly, the effective reference image can be reloaded by itself the data gate 36 and changed to the A ^ register. Generally talked about the cover that kept in the C register causes the correlator on the target, in the reference image, to be held at zero when closing occurs.

With an understanding of the covering technology and observance of the circuit according to FIGS. 3 and 4, the equipment of the algorithms will be described, which has been illustrated about the circuit according to the invention. From equation 1 results that an absolute difference correlation occurs easily by loading, for example a reference image is in the A register is given from the reference source 18 via the data port 36. Simultaneously with the loading of the reference image, a cover from the cover generator 4-2 can be provided by the data

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BATH ORIGINAL

gate 40 and entered into the C register will. With the reference image and the cover thus stored, the clock 1 can set the dynamic Load memory 16 from video processor 16 in series. Simultaneously with loading and moving of data in dynamic memory 16, the real image is paralleled through data gates 38 into the B register of the! Correlator 20 shifted. After N (M + 1) pulses The dynamic memory 16 and the B shift register of the correlator 20 are completely loaded from the clock generator 1 and the counter 54-, which is decoded in the sense of this situation, can make the current summing switch 52 effective. With a subsequent pulse of the clock generator 1, the whole is in dynamic memory 16 shifted reference image in series from an image part and the real image, held in the B register of correlator 20 is similarly shifted in parallel. When the clock is 1 continues, the real picture, which is constantly fed by the processor 14, is shifted through every point in the B register. With each shift, a bit-wise correlation takes place via the single-bit correlator 46 and the correlation output function is determined by the current summing switch 52. An absolute difference correlation between a real picture and a reference picture can use the described circuit according to FIG. Thus, the Output current summing switch 52 to test and hold circuit 27 to determine the best match.

Using this circuit, mean absolute difference (MAD) correlation can be easily performed. In this case, the covering from the covering generator 42 can be transferred to the C register and the one loaded with all ones.

130 030 / 0.4 1 1 - 27 -

_. - nni / MMAI

nen AvRegister and the B-registers loaded with all zeros or vice versa are given if the MAD correlation function 0 of equation 1 can be generated can. Then the output of the current summing circuit 52 equals the denominator of Equation 2 and the summation of the Cover bits are held in the C register. This value can be held in the buffer register 33 according to FIG. The Α register can then be filled with the reference image and the B register with the real image, as it was already has been described. The operation necessary for the algorithm of Equation 1 can be performed. This is the numerator of Equation 2.

The output of the buffer register 33 can be applied as a denominator to the divider 35, the simultaneous correlations of the correlator 20 being given to each pulse of the clock Λ as a numerator. The MAD correlation of equation 2 can then easily be performed by the correlator 20 as a shift of the real image.

The normalized product correlation of the opening after the Equation 5 can be generated by loading a covered reference into the Α register through TJnd port 44 and data port 36 be performed so that the register A contains the reference image covered by the masking function. Thereafter can logic zeros through the data ports 38 in the B register are given. At this time, the real picture can be shifted through the data gates 40 through the C register will.

Thus, the counters for the algorithm of Equation 5 are developed under the control of the clock 1. Before the Shifting the real image through the G register can load this with all ones, with the BeRegister be loaded with zeros to the algorithm of the

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BATH ORIGINAL

Equation 4- who is the expert on Equation 5. ^ü urch storing this result in the buffer register 33 as the denominator of the divider 35 and then by applying the divider 35 ^a n counters subsequently obtained, which have just been described, the algorithm of Equation 5 can be obtained to a normalized product correlation for the To maintain an opening between the real and the reference image.

The multivalued MAD correlation of equation 6 and Table 1 can use the circuit according to FIG. The correlator 20 to ^ igur 1 would thus be enlarged for this correlation technique, the more calls than any digitized image part multi-bit binary data to their _w ert build and thus works for a trivalent correlator of Figure 7 "of an equal number of image parts as that of Figure 1. The sizes of the A, B and O registers would be doubled. Similarly, twice as many single-bit correlators 01 and 02 would be necessary, which act on corresponding bits of the reference and actual image data, the single-bit correlators being similar to the described correlators 4-6. The total correlation function 0MAD between corresponding image parts of the reference and the real image is the summation of the outputs of the single-bit correlators 01 and 02 according to Table 1. All correlator elements 46 can lead to the single summing circuit 52 and the rest of the system operates as after Figure 1.

For the necessary increase in the circuit size, however, the correlation function of equation 6 is used according to the same

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BATH ORIGINAL

Method obtained like that of equation 2. The denominator can by setting the Α register to logical ones and the B register to logical zeros and by performing the correlation of Equation 1 can be obtained. The result can then be stored in the buffer register 33 to be applied to the divider 35. Then a new denominator can be sent to the Divider 35 can be placed when the real image is graded above the reference value.

Depending on the type of data required and / or the target area viewed or the reference image used, it may be desirable to perform the correlation function as a multi-valued product correlation. The normalized product correlation for the opening of equations 7 and 8 and Table 2 can be carried out using a circuit which is similar to that according to FIG. It is again necessary to double the single-bit correlators (GI to 04). According to Table 2, multipliers 54 to 60 are necessary to determine the values of the outputs of the correlators G1 to 04. To obtain 0A of Equation 8, the B register is loaded with zeros, the 0 register with ones and the Α register with covered reference image data from the cover register 42, the Und gate 44 and the data gate 36. The output of the current sun switch 52 is then 2A, which is given to the divider 36 and reduced by a factor of two or kept at the value, especially as this value is used as a denominator for all correlation functions to be carried out, such as the real image through the 0 register is pushed. However, a factor of 0A can also be stored as a denominator in the divider 35. The real image is shifted through the 0 register under the control of the clock Λ, whereby the correlation

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functions, as mentioned, via the single-bit correlators 46 (C1 to C4) and their outputs are passed through multipliers 54 to 60 (K1 to K4) evaluated according to Table 2. The current summing switch 52 takes the outputs of the multipliers 54 up to 60 and applies the following correlation outputs 0P of increasing values to the divider in accordance with the standard 35 · Here, the normalized multivalued product correlation is obtained by dividing 0P by 0A, according to the equation 5 received. The remainder of the circuitry of the system 10 operates in the manner described, so that the location address the best correlation can be determined.

You can by using a dual 128-bit correlator a large scale integration on a single microprocessor (chip). Such a microprocessor contains A, B and G registers of 128 bits each and correlation circuits for 128 single bits, as shown in FIG. 4A. Such a large scale integration enables Manufacture of a video correlator in a compact unit with low weight, the accuracy and reliability required for this being guaranteed.

It can thus be seen that the object of the invention through the structure and techniques described has been satisfactorily resolved. Although only a preferred embodiment of the invention is shown and has been described, the invention is not limited to this example but are various Deviations in terms of size, composition, design, etc. of the individual elements are possible without meaning and To depart from the scope of the invention.

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summary

In a digital video correlator, a reference picture and an actual picture are digitized and linked together compared in a shift circuit to determine the degree of correlation between the two images. Basically, the invention includes a video digitizer, the real and real pictures from different sources are divided into picture elements and their elements digitized into fixed voltage values.

The digitized real image is placed in a dynamic memory consisting of several interconnected Shift registers exists while the digitized reference image is held in a first set of shift registers which contain part of a processor. A second set of shift registers in the processor has one Cover function. A third set of shift registers in the processor is connected in parallel with the dynamic memory and records the digitized data of the real image under the control of a clock. Like the data of the real one Image is shifted through the third set of shift registers, single-bit correlators compare that with each other corresponding bits of each of the first, second and third sets of shift registers connect the digitized Values of the respective bit, whereby this comparison can be positive or negative due to the masking function. The outputs of all single-bit correlators are combined summed with the sum that represents the degree of correlation on a bit-wise basis between the real and reference images indicates. Another circuit is used to determine the point of best correlation between the two images and for normalizing and determining the mean value of the correlation output.

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BATH

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Claims (26)

Claims 1. Digital video correlator for comparing an actual one Image with a reference image, marked η ".et ·, by: a device for digitizing and subdividing real image and reference image in image parts and for digitizing these image parts into fixed voltage values; a displacement device (29) connected to the digitizing device for successive recording of the digitized image parts of the real image; and a correlator (20) interposed between the digitizer and the displacement device (29) and successively the digitized image parts of the Takes and holds the reference image and removes the digitized image parts of the real image from the 130030/0411 - 2 - * Branch (§28 PaO) TELEX: TELEGRAM: PHONE: BANK ACCOUNT: CHECK ACCOUNT: Munich: 1 - 856 44 INVENTION BERLIN BERLINER BANK AG. W. MEISSNER, BLN-W St. ANNASTR. 11 INVEN d BERLIN 030/891 60 37 BERLIN 31 122 82 -109 8000 MONKS 22
TFl. nönino or λα 030/892 23 8i 36D5716000 direction, and which compares the corresponding image parts of the real and the reference image with each other and generates an output indicative of the correlation between the images. • 2. Correlator according to claim 1, characterized in that that the digitizing device builds bits of binary data for the image parts. 3. Correlator according to claim 2, characterized g e identifier Inet that the shifter (29) sequentially the bits of binary data for the takes real picture. 4-. Correlator according to claim 3 »characterized that a second and a third shift register (A, B, C) are provided, each of which produces an output which the correlation between the binary states of corresponding bits of the second and third shift register. 5. Correlator according to claim 4, characterized in that that each logic circuit (22) has an exclusive-or gate between the corresponding Bit of the second and the third shift register are switched. 6. Correlator according to claim 5, characterized in that a fourth shift register is provided. - 3 - 130030 / 0Ä1t 7 Correlator according to Anspxmch 6, characterized in that that each logic circuit (22) has an AND gate, which is the input as the output the Exclusive-Oder-Gate and as another entrance receives the bit of the fourth shift register that corresponds to the Bit of the second and third shift register, which is connected to the exclusive-or-Ior. 8. Correlator according to claim 7 »marked thereby shows that a summing circuit (52) is provided, which receives and sums the outputs of each AND gate. 9 · Correlator according to claim 3 »characterized in the case of four shift registers, corresponding bits with several logic circuits to generate one corresponding to the exclusive-or-function Output are connected between corresponding bits of the second and third shift register, the logically with the respective bit of the fourth shift register and - moderately controlled. 10. Correlator according to claim 9j, characterized in that that the second shift register the. Bits of binary data for the reference image and holds. 11. Correlator according to claim 10, characterized in that that the third shift register bit holds binary x 'data for the real picture and holds. 1 3ö 0 3 0/0 4 1.1 12. Correlator according to claim 11, characterized in that the fourth shift register is ekennzei with the cover generator (4-2) for picking up and holding a binary cover is connected. 13. Correlator according to claim 9 »characterized in that that a gate circuit with the four shift registers for controlling selectable pulses for this register is connected. 14-. Correlator according to claim 14, characterized in that that the gate circuit with the second shift register for selective binary ones, binary zeros or the bit of binary data of the reference image of the second register. 15 · Correlator according to claim 14, characterized in that, indicates that the cover generator (4-2) is connected to the gate circuit, which makes the bits binary Data of the reference picture which are passed to the second shift register. 16. Correlator according to claim 13 »characterized in that that the gate circuit between the first and the third shift register for selective Passing binary ones, binary zeros, or bits of binary data of the real image to the third register is switched. 17 · Correlator according to Claim 13, characterized in that that the gate circuit between the masking generator (4-2) and the first shift register 1.30030 / 0411 BATH ORIGINAL for selectively passing a cover, binary ones, or bits of binary data from the real image of the fourth register is switched. 18. Correlator according to claim 13, characterized in that that the outputs of each logic circuit are summed in a summing circuit (52) and also a divider circuit is connected to the summing circuit to reduce that of the summing circuit delivered sum to divide when a first set of inputs from the gate of the sum the summing circuit and a second set of inputs is selected from the gate circuit. 19. Correlator according to claim 3, characterized in that that the first shift register sequentially the bits of the data of the real picture shifts. 20. Correlator according to claim 18, characterized in that that the third shift register is parallel to the first shift register at several points is connected that the shifting of the binary data through the first register through the second register and takes place from the first register to the second register under the control of a common clock generator (1). 21. Apparatus for comparing the bits of binary data of a reference image with bits of binary data of an actual one. Image in a system with a correlator according to the preceding claims, characterized by: - 6 1 3 0 0 3 0/0 k 1 1 a first shift register that receives and holds binary data of an actual image; a second shift register which the bits of binary data of the real image under control, a clock (1) shifts, and several logic circuits one of which between respective bits from each of the first and second shift registers is switched and provides output signals corresponding to the correlation between corresponding bits. 22. The device according to claim 21, characterized in that that a summing circuit is connected to several logic circuits and the Output signals are summed to produce a correlation signal as an aggregate of the output signals. 23. The device according to claim 22, characterized in that that a masking generator is connected to a third register at a third shift register, and that corresponding bits of the third register are connected to a corresponding logic circuit which is connected to corresponding Bit of the first and the second register is set. 24 ·. Device according to claim 23, characterized in that that the cover generator (4-2) and the third shift register the output signals of the Make logical circuits effective and block them. 25. Device according to claim 23, characterized in that that every logic circuit contains an exclusive-or-gate, which between corresponding- 130O3O / OA11 BATH ORIGINAL the bit of the first and second shift register and an AND gate between the exclusive-or gate and the third Shift register is located. 26. The device according to claim 21, characterized in, that a fourth shift register sequentially the bits of binary data of the real picture shifts that the inputs of the second register are connected in parallel to the outputs of the fourth register and that the data is shifted through the second and fourth registers under the control of the same clock (1) will. 27 · Device according to claim 21, characterized in that that several multiplier circuits with the outputs of certain logical Circuits are connected to evaluate their output signals, and that a summing circuit is connected to the evaluate Output signals and receives them. 130030/0411 ORIGINAL