DE2965878D1 - Buffer memory device for data transfer between a processor and an input/output unit - Google Patents

Buffer memory device for data transfer between a processor and an input/output unit

Info

Publication number
DE2965878D1
DE2965878D1 DE7979104895T DE2965878T DE2965878D1 DE 2965878 D1 DE2965878 D1 DE 2965878D1 DE 7979104895 T DE7979104895 T DE 7979104895T DE 2965878 T DE2965878 T DE 2965878T DE 2965878 D1 DE2965878 D1 DE 2965878D1
Authority
DE
Germany
Prior art keywords
processor
input
memory device
output unit
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE7979104895T
Other languages
English (en)
Inventor
Chester A Heath
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE2965878D1 publication Critical patent/DE2965878D1/de
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/063Dynamically variable buffer size
DE7979104895T 1978-12-28 1979-12-04 Buffer memory device for data transfer between a processor and an input/output unit Expired DE2965878D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/973,938 US4258418A (en) 1978-12-28 1978-12-28 Variable capacity data buffer system

Publications (1)

Publication Number Publication Date
DE2965878D1 true DE2965878D1 (en) 1983-08-18

Family

ID=25521396

Family Applications (1)

Application Number Title Priority Date Filing Date
DE7979104895T Expired DE2965878D1 (en) 1978-12-28 1979-12-04 Buffer memory device for data transfer between a processor and an input/output unit

Country Status (6)

Country Link
US (1) US4258418A (de)
EP (1) EP0013347B1 (de)
JP (1) JPS5591026A (de)
CA (1) CA1124887A (de)
DE (1) DE2965878D1 (de)
IT (1) IT1165427B (de)

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Also Published As

Publication number Publication date
JPS6318220B2 (de) 1988-04-18
EP0013347B1 (de) 1983-07-13
JPS5591026A (en) 1980-07-10
IT7928122A0 (it) 1979-12-18
IT1165427B (it) 1987-04-22
US4258418A (en) 1981-03-24
CA1124887A (en) 1982-06-01
EP0013347A1 (de) 1980-07-23

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