DE2512935C2 - Data exchange system - Google Patents

Description

The invention relates to a data exchange system according to the preamble.

Information cards which can be used as credit cards, bank cards and the like are already known (US-PS 02 464), each of which contains a memory consisting of solid-state elements, in which the respective Purpose of use is stored in accordance with the data. Such a memory can, for example, from Semiconductor elements or be constructed from bistable switching elements. By introducing such a Information card, which represents a data carrier arrangement, in a correspondingly designed receptacle Data input / data output device, it is then possible to enter information into the data memory of such a To write data carrier arrangement or to read information from such a data memory. There no security measures with regard to access to the data memory of the respective information card or data carrier arrangement are made, is thus an improper use of such a data

bo carrier arrangement possible in a very simple way. In particular, this can be done in a very simple manner the memory content of the data memory provided in each case can be changed.

There is also a data exchange system known (FR-PS 20 44 691), in which the individual data carrier arrangements also allow easy access to data memories contained in them, in particular are formed by shift registers. It is sufficient for the respective data carrier arrangement via their

d5 coupling device with which it can be connected to the data input / data output device, clock pulses to feed. In the event that data is to be read from such a data carrier arrangement, In addition to the supply of the mentioned Taklimpulse at the mentioned coupling point a separate one is sufficient To connect memory, in which then to a certain extent the content of the data memory of the respective

Disk arrangement can be mapped. However, this also makes this known data exchange system very easy to operate improperly, d. h that in an unauthorized manner the content of data memories in each provided data carrier arrangements is changeable or can be read out.

Although it is already a Speichtrschutzeinrichtung known (DE-AS 14 99 687), the protection of Information in certain memory areas of a data processing system against unauthorized access intended to serve by unauthorized users. In this case, this device is intended to store units assigned to the memories to control the access operations to the memories. For memory access operation should the protection of stored information in this known arrangement only depends on the identity of the accessing user on the type of access and on certain geometric memory area limits be expanded. However, even with this known device, there are already simple possibilities for one thing: o Abuse present. For improper use of the known arrangement only needs a forged user identity to be given in order to gain access to storage areas to which as such, no access should take place. But this means that in this known arrangement improper Accesses to the intended memory are not excluded, since for such accesses with the usual Control signals get along.

After all, it is also an arrangement for data backup in the main memory of an electronic one Calculating machine known (DE-AS 12 47 707), in which a comparison device is provided that the at Execution of a program in a memory address register successively occurring data by comparison with provided in a second register.! Data checked for membership of the memory area to which the currently running program is assigned, and which emits a signal that the control of the blocks the respective memory cell if it does not belong to the program currently running. on in this way, parts of the> main memory are to be protected against destruction by incorrectly programmed addresses will. The fact that for this backup in each case corresponding data in said second register have to be provided, this known arrangement has little flexibility in terms of locking or release of different memory areas of the main memory for access to. This The disadvantage becomes particularly clear when a relatively large number of storage locations of the RAM is to be secured against access.

The invention is now based on the object of showing a way as in a data exchange system of any type of repeated write operation mentioned at the beginning, especially in a certain defined memory area / address area can be prevented.

The object indicated above is achieved according to the characterizing part of the main claim. This measure has the advantage that a particularly flexible blocking or release of the Storage locations of the data memory is made possible with regard to their control channel, while at the same time on relative a simple way of protecting specified storage locations in the data memory from unauthorized manipulation is made possible.

Further expedient refinements of the invention can be found in the subclaims.

The invention is explained in more detail below with reference to drawings, for example.

1 shows the general structure of a data exchange system for processing payment transactions with a bench in which the invention according to FIGS. 4-9 can be used,

FIG. 2 shows in detail a portable device that can be used in the data exchange system according to FIG Data carrier;

F i g. 3 shows in detail a in the data exchange system according to FIG. 1 usable balancing unit;

F i g. 4 shows an embodiment of a data carrier arrangement in which, according to the invention, writing in memory sections marked as forbidden in the intended data memory are prevented;

F i g. 5 shows yet another possibility of realizing the data carrier arrangement; F i g. Figure 6 shows one embodiment of a control circuit for a memory drive disable circuit;

F i g. 7 shows yet another embodiment of a data carrier arrangement whose data memory is by means of a counter can be addressed in an addressable manner;

8 shows a modified embodiment of a data carrier arrangement in which the occurrence of memory addresses between a lower limit X and an upper limit K prevents the control of the data memory provided;

FIG. 9 shows an embodiment of a data carrier arrangement in which the memory activation blocking circuit is designed so that the reading of data from certain memory sections of the intended Data storage is prevented.

All the embodiments of the file exchange system according to the invention described below are in particular intended for use in banking and accounting. For this reason and for reading To simplify matters, the banks are largely responsible for explaining how it works and its effects and the management of a bank account uses its own terminology. However, the embodiments can can also be used for other purposes and wherever necessary. Data, in particular in a confidential and irreversible manner. bo

The electronic circuits of all the embodiments described below are because of their use inaccessible in banking in a portable, hereinafter also referred to as a data carrier arrangement Object, which is designed in particular in the form of a flat rectangular card, arranged. they are incorporated into this object in an inaccessible manner, α. i.e., it is not possible to use the electronic Approach circuits without destroying them. This result can be achieved in particular by that these circuits run in the form of integrated circuits and in an opaque plastic are embedded, but other mechanical solutions are also conceivable.

In all figures that relate to the data carrier arrangement (the card), the envelope which the switch-

parts that are electrically or optically inaccessible from the outside are limited by a dashed line shown.

The coupling means are the only elements that provide electrical or optical access to the im Enable electronic components contained inside the card.

It should be noted that for other applications a more intensive protection against attempts of fraudulent It is not necessary to impair the content of the map, although certain - if not all - elements, which form a memory activation blocking circuit, outside the data carrier arrangement, in particular can be arranged in a data recording / data output device. They are also for others Applications the measures provided for the inaccessible incorporation of the circuits in the data carrier arrangement superfluous.

In order to make the description of the electronic circuits as simple as possible, it has been dispensed with showing the supply circuits etc. in order to keep only the absolutely necessary functional circuits. As far as the coupling means are concerned, however, the supply connections which are to be set up between the data carrier arrangement and the data input / output device are indicated by the characters VP, VC, ground (characters which each represent the write voltage source, the general supply source of the linkage circuits and the zero Mark line).

Finally, it should be noted that the monolithic read-only memories used in these embodiments of various types, in particular of a programmable or non-programmable type. Such memories do not require any energy to store information. In contrast, requires writing information is generally a considerable amount of power (several watts). Therefore guarantee the manufacturers an extremely long storage period on the order of several decades in the event the reprogrammable memory. Storage of this type are:

INTEL 1702 and National Semiconducter 5203. These memories can be made by ultraviolet rays or by X-rays are deleted. HARRIS 7620. Monolithic memory 6340, TEXAS INSTRUMENT 74 S 387, INTERSIL 5604. These memories, which work without destroying the information when reading, are in the Fuse or connection breakdown type implemented.

Memories with capacities of 4096 bits are currently being produced by various manufacturers, especially in the area of MOS memories (erasable). Modern methods of interconnecting integrated circuit wafers enable a memory block of 16 kbits or 32 kbits (4 or 8 wafers) to be produced at low cost on a surface area of several tens of mm ² , including the special circuits of the subject matter of the present invention that this block can be enclosed in a card with the dimensions 2 × 60 × 80 mm.

These monolithic semiconductor memories have, in comparison to other memories, such as magnetic »cassettes«, elastic discs, etc., have considerable advantages. They are more reliable and their dimensions are small They do not require any mechanical movements for reading and writing, are insensitive to magnetic fields and difficult to falsify and damage (the impostor must have complicated use electronic means to change the state of the semiconductor memory). This semiconductor memory are therefore particularly suitable as data memories in the invention in comparison to other memories to be used. This is particularly true for the applications of the systems for banks.

The various embodiments of the data memory of the invention differ significantly from each other by the construction of the portable data carrier arrangement.

It is clear to those skilled in the art that each of the portable data carrier assemblies shown in the figures can be connected to a transmission device comprising all or part of the Has properties of the transmission devices described.

The in Fig. 1 shown data exchange system has two different parts that are in operation by a transition are connected, which is symbolically represented by a dash-dotted line.

In the left part of FIG. 1 shows a portable data carrier arrangement, preferably in the form of a Ring, a card, a tag, a pen, with a certain number of electronic circuits (e.g. implemented in an integrated circuit design).

On the right side of the FIG. 1 is a data input / output device, preferably a bank note dispenser or a cash register, displayed for immediate use at a point of sale. in the in the latter case, the business process described below does not involve the issue of banknotes connected, but with the writing of information in the cash register of the merchant, which it to this later allowed, from the bank of the holder of the data carrier arrangement, a counterpart in paper money or To receive book money.

For the sake of clarity, this description continues to assume that banknotes are issued, Which is completely equivalent to the use of a cash register in terms of the electronic structure is.

The circuits of the ring as a portable data carrier arrangement here contain a identification memory 40, a target memory 51 and a credit memory 50 as a data memory. The system allows in the course its use the following operations:

Identification of the holder of the data carrier arrangement -. a process that enables or prevents the further course of the processes;
possible reading of a credit note and transferring the credit amount of this note to the credit memory of the data carrier arrangement;

Issuance of a requested amount of cash if and only if the account balance of the holder of the data carrier arrangement allows this in view of the amount of this amount;
Registration of the entirety of the transactions for the purpose of booking and / or for possible later

Control on a data carrier such as a semiconductor memory.

The operations to be performed by the data carrier arrangement holder are as follows:
Eventually entering the value of an approved loan through reader 114,
Entering the confidential identification number through the keyboard 31,

possible entry of a target amount using the keyboard 63. -,

whereby these three operations can be carried out in different chronological order,
Introducing a protruding part of the data carrier arrangement (the ring) at a corresponding point provided in the housing of the data input / output device.

At the moment in which the owner of the data carrier arrangement completes the last operation incumbent on him, i. h .. the Introduction of the data carrier arrangement in the data input / data output device, all of them operations listed above performed very quickly. Almost instantly, the system will perform this operation have finished giving any of the following possible outcomes according to the holder's choice of Disk arrangement and its account balance allows:

Simple checking of the account balance through numerical display of the balance by means of a display element 69,
Checking the account balance after entering a credit amount as a result of an entered »credit approval«, which is recorded, deleted or eliminated in a manner not shown, after the credit amount has been written into the credit memory of the data carrier arrangement,

Check the account balance after entering a credit balance and issuing cash, with the new Account balance must necessarily be positive or zero after these two operations.

Checking the account balance after issuing cash; as in the previous case, the cash is withdrawn would only exist if the balance of the new balance is positive or zero.

The various functional sequences of the system, which serve as an overview for the following description, are the following:

Feeding the data carrier arrangement,

Commissioning of the general control of the various elements of the system by triggering a pulse distributor 38, operation of one of three memories (FIG. 2),
Operation of one of two series baling plants (marked with A-SZS) ( Fig. 3),
Reading of the previous holdings,
Enrolling new credit status,

Reading of previous target statuses. jo

Registration of the new status.

The dispensing device for dispensing bank notes has a power generator 150 which feeds a winding 15. When the data carrier arrangement is inserted into the output device and thus into the data input / output device, the winding 151 as the primary winding of a transformer is coupled to a secondary winding 105 which is part of the circuits of the data carrier arrangement. Via a rectifier circuit consisting of a diode 106 and a non-capacitive electronic filter 107, this winding supplies a direct voltage which is intended for the various supply circuits of the data carrier arrangement. If necessary, the electromagnetic coupling is replaced by an optical coupling, the elements 150 and 151 being replaced by a light source and the winding 105 being replaced by a photocell. The coupling of the data carrier arrangement and the data input / data output device is effected in a simple manner in that a protruding part of the data carrier arrangement is inserted into a corresponding location provided in the housing of the data input / data output device. This introduction causes a mechanical shock to close a contact 27 which is part of a general supply device, not shown, of the circuit of the bank note dispenser. At the same time, a timer 28 is triggered, as a result of which a 1 signal is output to a first input of an OR gate 41. This 1-signal is kept upright so long that the identification of the owner of the data carrier arrangement can be effected. It should be noted that the second input of the OR gate 41, which is connected to the output of a flip-flop 42, carries a 0 signal, as a result of the corresponding setting of the flip-flop 42, which is triggered by the occurrence of an! is set at its clear input CL via the OR gate 86. If this identification attempt succeeds (from the following it becomes clear under which conditions this happens and what this entails), the supply connection is maintained until the end of operation of the banknote dispenser, based on a 1 signal at the second input of the OR Link 41.

The absence of this signal, which indicates that the user has used an incorrect identification number, In contrast to this, suppresses the supply connection by the occurrence of 0 signals at both of them Inputs of the OR gate 41, the 1 signal being converted back to a 0 signal from the first input while the 1-signal at the second input has not been set. This allows the bank note dispenser cannot be used. The embodiment of the timer 28 can be understood by those skilled in the art be left.

It should be noted that the entire arrangement described here is wired in positive logic.

Commissioning of the general control

If an i signal occurs at one of the two inputs of the OR gate 41, this signal is transmitted via this ODbR gate an AND gate 34 and also an on the occurrence of a rising signal or Pulse edge triggered monostable multivibrator 35 supplied. The monostable multivibrator 35, in which stable state the signals 1 and 0 indicated at its two outputs, delivers a pulse of complementary value (1-pulse at the output marked with 0 and 0-pulse at the output marked with 1

'■ / recorded output) during the occurrence of a rising pulse leading edge at its input. While the duration of the pulse emitted by the monostable multivibrator 35 is given by the one denoted by 1

$ Output sends an O-pulse to the second input of the AND gate 34, which thus blocks, d. H. locked

j * remains. The other output 0 of the monostable multivibrator 35 delivers a positive 1-pulse to one

¹ Jf 5 Input of a counter 36 which is reset to zero and which takes over the control of the demultiplexer 38.

t | At the end of the pulse emitted by the monostable multivibrator 35, the stable one appears again

^; 1 signal at the output marked 1 of this multivibrator, which opens the AND gate 34,

p d. H. transferable, becomes. This AND element now leaves a first one supplied by the clock generator 33

$ Pulse pass. This pulse transmitted to the counter 36 brings the demultiplexer 38 into its first position,

Il ίο where the 7-line 160 is connected to the starting position 0. The impulse just mentioned becomes at the same time

1% to the input of a monostable multivibrator that can be triggered on a falling signal or pulse edge

^ 37 supplied, which works like the monostable multivibrator 35, but with the difference that it only

h delivers a pulse at output 0 when a falling leading edge occurs at its input.

; '.. This pulse occurring at the output 0 of the multivibrator 37 is converted by the demultiplexer 38 to its

j $ 15 transfer output 0 to. After this pulse occurs, this part of the arrangement remains unchanged until

ρ to the occurrence of the next pulse sent by the clock 33. The cycle then repeats itself in

jl in the same way as before, the counter 36 passing the demultiplexer 38 from output 0 to output 1

'Jl' lets; the next pulse sent by the clock 33 is then delayed and after shaping

t | given by the monostable multivibrator 37 from output 1 (again leading in the case of a 0 signal

fi 20 /? G line 161 of the demultiplexer 38). This operating cycle is sequentially applied to the ten output

I; the demultiplexer 38 would be executed, the last eight successively each having a positive pulse

$ output one and the same clock generator line 162 via the OR gate 39. It should be noted that the signal feed

ψ> stood at the output 9 of the demultiplexer 38 immediately followed by the signal state described above, which

S | occurs at output 0. This part of the arrangement ensures that the system will remain operational during its entire service life

ti 25 controlled. In addition to supplying the circuits of the data carrier arrangement, the transmission of

r \ Information between the data carrier arrangement and the data input / output device in the

p. in the same way by optical coupling between a light-emitting diode and a photodiode

Iv ■ works.

i 30 Reading of the confidential identification number

H If a positive pulse occurs at output 0 of the monostable multivibrator 35, a 1 signal is over

S the OR gate 60 and the optical coupling 45 to a memory input RM of the data carrier arrangement

ig supplied, whereby their have memory 50 and their target memory 51 on their first memory page in the

35 get in the correct position to trigger a later read process (a memory page is understood here as a set of several parallel memory locations of the respective memory, with each memory page or memory location defining a blocked state or an open state, depending on whether it has been written to or not, and in an irreversible way). The said signal also resets the serial balancing units 32 and 49 and the counter 47 to the counting position 0 in each case. The memory 40 is open

40 of its first memory page is determined by a constant 1 signal at its (zero) memory input (this Signal is indicated by a plus sign in FIG. 1 symbolizes); because the memory contains only one in principle and Page previously described for the life of the data carrier arrangement, which contains the confidential identification number of the holder, registered when opening the account. It should be noted that the confidential Code (not shown) is designed in such a way. that he is both the owner of the data carrier arrangement as

45 also represents his bank.

The memory or data storage 40 of the data carrier arrangement (F i g. 2) continuously by a 0 signal at its read / write input E / L in reading position, which as ^r closing of the contacts 3 and the Unwirksam.T.achen the memory driving Locking circuit or the locking member 2 causes. The 8-bit counter 1 (address counter), followed by the blocking circuit or the locking element 2, is used to address the memory

50 5 (a single address is used here, which is that of the first memory page). For the credit memory and the target memory, the transition from one to the other memory page takes place at the beginning of each Tßkigebcf cycle by a pulse at the "G input J51; this pulse, which is delayed by the monostable multivibrator 88, causes the address counter 1 to continue counting. The first pulse which appears on the conductor RG resets the 4-bit counter 6, which controls the output multiplexer 4, it leaves

55 count the address counter 1 by one step after it has been delayed by the monostable multivibrator 88.According to the occurrence of the clock pulses, the values of the various bits are recognized on the selected memory page of the memory 5, which at the considered output 3 from the bit with the highest Weight up to the bit with the lowest weight are present and which are transmitted in series via the coupling 104 to the balancing unit 32, which by counting in binary and parallel form a number χ

ω indicates which is fed to the input of a comparator 30 The other inputs of the comparator 30 are already fed a number y in the same form, which is not shown from the identification number previously entered with the decimal keyboard 31 by the owner of the data carrier arrangement has been encoded. If χ and y are the same, the comparator 30 gives a signal via the AND element 85! to the set input of the flip-flop 42, which thereby toggles and from its output a signal 1 to the one

b5 input of the OR gate 41 emits. This ensures that the clock control is maintained by the clock generator 33 after the timer 28 has stopped. The presence of the UN D member 85 obliges the owner of the data carrier arrangement to enter his confidential code within a prescribed period corresponding to the time that the timer 28 is active.

Operation of the identification balancing plant 32 (Fig. 3)

In the present case, the balancing unit 32 is operated only as an addition device. It is held in the positive counting position by a continuous signal 1 at its input number subtraction C / D , symbolized in Fig. I by a plus sign. It essentially has a 16-bit counter / subtractor 11 (of which only the 8 low-order bits are used here), to which, if a positive information bit is present at the input of the AND element 10 from the memory 40, the from the clock generator μ5 üoer the AND gate 14 conducted pulses are emitted. The zero reset signal originating from the conductor 161 blocks the AND gate 14 via the OR gate 16 and the flip-flop 13 and resets the 4-bit counter 12 to zero, which puts the multiplexer 9 in its ineffective zero position. The first clock pulse leads the multiplexer 9 out of one position, whereby it is returned to its input state by the counter 12! is convicted. The first clock pulse can also tilt the hip-flop 13, whereby the blocking of the AND gate 14 is canceled, which allows the pulses of the clock 15 to pass; the clock generator 15 is 300 times faster than the clock generator 33. Before the second clock pulse occurs, 128 pulses from the clock generator 15 have been introduced into the 16-bit counter / subtractor 11 via the AND element 10, if necessary. At the end of the 128th pulse, the frequency divider 20 outputs a signal i to the input i of the multiplexer 9, whereby the AND element 14 is blocked via the OR element 16 as a result of the flip-flop 13 being tilted. The system remains unchanged until the occurrence of the second clock pulse, which puts the multiplexer 9 into its input state 2. The previous cycle is now repeated. The following on the AND gate

Information occurring 10 corresponds to the reading value of the bit that follows immediately after the bit with the highest weight in rank (2nd bit of the first memory page of the memory 40). The confidential identification number is thus read, translated into a pulse number according to its value, in stable binary form in the unit

11 and transmitted in parallel to the input χ of the comparator 30 (see. Fig. 1). An arrangement consisting of the shift register 17 with series input and parallel output (FIG. 3), followed by the locking element 18 and the OR element 19 , signals the end of an empty memory page, ie a memory page, by emitting a signal 1 , on which all bits contain the information 0, i.e. nothing has been written. This arrangement for the detection of zero, marked with DZ, is not used here; rather, it becomes so in the balancing unit 49, as will be described further below.

Reading of the previous credit balance (see Fig. 1)

When a signal 1 appears at the output of the comparator 30, it is transmitted via the AND element 85 (the timer 28 has not yet been stopped), which is connected to the set input PR of the flip-flop 42. This flip-flop now emits a signal 1 from its output instead of a signal 0, which maintains the operation of the general clock generator 33 until the end of operation of the entire arrangement. This signal 1 is fed to one input of the AND element 87, as a result of which this AND element can be transmitted until the end of operation of the arrangement; The units 50, 51, 49, 47 and consequently 46 and 48 are already reset to 0, as described above. At the beginning of the cycle the data carrier arrangement to be introduced, the information contained in credit memory 50 in the Saldierwerk 49 via the output sdes memory 50, and the coupling 1 19 according to the identification of the holder, according to a method of reading the confidential identification number during the first Clock cycle corresponds. The transition from one memory page of the memory 50 to a subsequent memory page takes place in the memory 50 by means of a pulse at the beginning of the clock cycle via the /? G line 161, via the coupling 44. The sum of the values of all previous credit balances shown in the have store in a v. The manner described below appears in a stable form at the output of the series balancing unit 49 in binary form. It is made visible by means of the display device 69 after recoding (not shown), which is familiar to the person skilled in the art. The same remark for an inverse transformation applies to keyboards 31 and 63 in the decimal system. It should be noted that during the reading operation of the credit balance, the serial numbering unit 49 is in the counting position, to be precise due to a signal 1 at its input from the output 0 of the decoder 48 and the OR gate 52. After arrival of the value contained on the last written memory page of the memory, the memory page that is read in the following clock cycle is an empty page, which is recognized in the serial processing unit 49 by a signal i that is output at its output DZ to identify an empty page (Fig. 3), the eight locking circuits 18 at the beginning of the second clock cycle from the output Γ and the NOR gate 19 are controlled. This signal 1 blocks the output of a clock pulse RC 161 from the output of the AND element 82 via the multivibrator 81 (FIG. 1), which can be triggered on rising signal or pulse edges, in such a way that the addressing of the memory 50 is maintained and the writing of a new credit or credit balance, which may be required by the holder of the data carrier arrangement, is made possible on the blank side.

Registration of the new credit

The same signal 1 for the detection of zero, which passes through the OR gate 108 , causes the counter 47 to advance in its counter position, and it sets the multiplexer 46 in its input position 1 and the decoder 48 in its output position 1, which the balancing unit 49 through A signal i at the other input of the OR element 52 holds in the positive counting position. The same signal 1 reaches the write / read input of the memory 50 via the coupling 57, whereby the memory in question, due to ineffective locking elements 2, opens the read contacts 3 with the transferable AND gate 7 is brought into writing. Entering the information in serial form on the page reserved for registered mail

now effected via the multiplexer 113 (Fig. 1), on the one hand in the direction of the credit memory via the coupling 120 and on the other hand in the direction of the serial processing unit 49 via the multiplexer 46, the multiplexer 113 by aen counter 115, which is in turn by the general clock is controlled, is controlled. The value of the credit total is therefore written to the first empty memory page of the credit memory 50 and added to the total previously displayed by the display element 69 via the 16-bit counter / subtractor of the serial balancing unit 49. The end of the written memory page is detected by the AND gate 59; whose two inputs each carry a signal 1 at this moment, the first input being connected to output 1 of the decoder 48, while the second input is connected to the Av.sgang of the highest weight of the counter 115 via the falling signal or pulse edges there

to triggerable monostable multivibrator 140 is connected, the task of which is to detect the transition of the counter il5 from state no. 7 to state no. When the reading and writing of the new credit or credit balance in the memory 50 is finished, the corresponding value is in a manner not shown in a credit card reader 114 by a. Conductor 93 to the input E towards transmitted signal deleted. The output of the AND gate 59 carrying a 1 signal now controls the credit memory and the target memory - «here the OR gate 60 and the coupling 45 back to zero, and it also leaves the counter 47 via the OR gate! to step forward in his stance.

Reading of the previous target status

The new position of the counter 47 brings the multiplexer 46 to its input state 2 (reading of the target memory 15 "), whereby stn output 2 of the decoder 48 a signal! occurs; the outputs 0, 1 and 3 of the decoder 48 carry 0 signals, as a result of which the serialsaldierwerk 49 reaches the subtracting position as a result of a signal 0 at its input CJD. The reading of the previous soil levels is now effected like the reading in the credit memory 50 via the coupling 122 , whereby the number representing the sum of these target levels is subtracted from the number already written in binary form in the 16-bit counter / subtractor of the serial indicator 49 , ie Vv> n of the number which was previously displayed by the display element 69. The first empty memory page of the target memory is detected by a signal 1 at the output DZ of the serial processing unit 49 by means of the AND element 109 . It should be noted that at the moment this information appears, the outputs of the serial counter 49 are in a stable, numerically binary state, corresponding to the operation

X = (sum of previous credit balances) + (true credit balance) - (sum of previous debit balances).

The value of X is necessarily positive even if the new habenMand is zero. If the previous balance and the new credit balance are zero, then -isr value X is obviously also zero, which is a borderline case.

The value of the money intended for issuing by the system described - this value was entered by the owner of this data carrier arrangement through the decimal keyboard 63 before the data carrier arrangement was introduced into the output device - is given in its binary form Y by the binary comparator 110 compared to the value X. If a signal 1 occurs at the output 3 of the decoder 48, which occurs during the last reversal of the counter 47, caused by a signal 1 at the output of the element 1S £ H through the element 108, the comparison of X and Y leads to the output of a signal 1 from the single output of comparator 110 if and only if X is greater than Y. At this moment the counter 115, which controls the successive input states of the multiplexer 116 , is reset to zero as soon as the counter 47 has been determined in its last state. The arrangement is now in writing position for entering a new target position.

Registration of a new target status

The multiplexer 46, which is in its input position 3, is connected to the target memory 51 via the coupling 124 in order to write a new target status, the value of which is simultaneously deducted in the same way as before by the scrient dialing unit 49 and displayed in the display element 69. It should be noted that the monostable multivibrator 81 plays the same role for the target memory 51 as it plays for the credit memory 50, that is, the entry in the memory is made on the first empty memory page and not on the next, which is also an empty one Memory page is. On the other hand, the output 2 of the decoder 48, which is a Signa! 1 leads, the target memory 51 is brought into writing position during this last phase of the operation of the arrangement via the coupling 123, where at the end of this phase a general stop signal is caused by the flip-flop 42 tipping over. As a result, a signal 1 arr delete input of this flip-flop occurs via the OR gate 86, as a result of the corresponding output from the AND gate 111, which in turn is made transferable by a positive pulse at its input, which is derived from the output zero of the monostable multivibrator ί · Λ originates, which acts in the same way as at the end of the writing of the new credit or credit balance in the memory 50 ben the new target level in the target memory 51 happens to an amount whose amount has previously been entered in decimal form by the owner of the data carrier arrangement with the keyboard 63 and checked, as previously described.

The coupling with the help of a transformer for supplying the data carrier arrangement from the data input Gabe '/ Ddtenausgabeeinrichtung her has been selected and in FIG. I represented in such a way that this is a galvanic «

Isolation guaranteed The secondary winding 105 of the transformer, which is formed by the windings 151 and 105 during the interaction of the data carrier arrangement with the data input / output device, is followed by a filter 107, which supplies a regulated or stable DC supply voltage at its output Filter is not capacitive because of the reduction in size, since the required capacitance for a classic filter cannot be made sufficiently small in relation to the other electronic elements. This supply coupling could also be realized by an optical coupling between a light source, which is contained in the data input / data output device, and a photocell in the portable data carrier arrangement, whereby the desired galvanic isolation is ensured. in order to avoid any short circuit that could destroy the memories contained in the data carrier arrangement. The same applies to the other optical couplings that have been selected for the transmission of information between the data input / output device and the data carrier arrangement. The three memories, the functions of which have been described, are basically of the same type. When implemented in an integrated circuit, they have the property of being written to one after the other and irreversibly as desired (with the exception of certain types of memory that are not accidentally, but by appropriate treatment can be deleted). These memories, the capacity of which is approximately 100 times greater per unit area than that of the magnetic memories generally used for this purpose, have the advantage over the latter that reading and writing are easier and more adaptable due to the fact that they do not require the immediate vicinity of the reading device. They are addressed electronically, with complicated, expensive and less reliable electromechanical devices being replaced by simple conductors, the number of which can also be reduced by the known multiplex method. Among these integrated circuit memories, non-volatile memories are preferably used.

The display element 69 is used for simple visualization by means of luminous digits, but it can also be by means of a Printing unit are replaced, this printing unit having parallel branches at its inputs can, in order to give the holder of the data carrier arrangement the opportunity to submit a document in front of the by the Data input-ZData output device read operations carried out during the operation described above to get or keep.

The method applied to a bill dispenser can also be used directly at a point of sale, thereby enabling the holder of a data carrier assembly to have his or her own Make purchases without paying the purchase amount due by cash or check.

4 is described below, in which an embodiment of the memory control blocking circuit is shown, which is intended to change the content of coded as prohibited Prevent memory sections. The blocking circuit is contained on a card 400.

The memory 601 is arranged for words of 9 bits, e.g. B. for 256 χ 9 bits. In the empty state, all storage locations carry the signal 1. The identification number, which z. B. of 21 digits, ie 84 bits, is divided into eleven words with 8 bits, each word being followed by a bit B9 of the value zero. The initial write takes place from B1-B9 for each of the eleven memory pages occupied by the identification number, such that the cancellation of the ninth bit (i.e. "writing a zero") only prohibits the write after it has been carried out . The blocking element 602, which may have to be able to withstand an increased voltage at its input 605 , controls the separation input 606 of the memory (often identified in the technical literature with CS, E or ME). This is addressed by the conductor bundle 604 (8 conductors in the example given), while the eight input / output bits are available at point 603. The command is given on conductor 607.

This embodiment has the advantage of making each address irreversible with eight bits of the memory, if necessary. However, it requires a considerable number of connection points to the outside (21 in the example shown) and a device with diodes 608, which prevents the logic element 602 from being made capable of transmission from the outside.

It is possible to reduce the number of these connections by creating a memory for words with a Bit is set up, is used in a circuit as shown in Fig. 5 and in the following is described.

In Figure 5, a further embodiment of the memory control blocking circuit is shown, which for this purpose is intended to prohibit the modification of the content of memory sections coded as forbidden. the Lock circuit is included on a card 400.

The address conductors 613 of the memory 609 (set up for 2048 words with one bit) also control the parallel 11 address bit comparators 611 and 612, which are connected at their second output to two connection networks, whereby they are connected to coding elements A and B in this way are that diode matrices, dead memories or simple connection points determine the numerical forbidden "window" (in other words, the addresses of the memory sections coded as forbidden). The comparators allow the AND logic element 614 to be opened. Writing can be prohibited by controlling the blocking input of the blocking element 610, which is connected to the output of the logic element 614. bo

It should be noted that when the lower limit address of the memory is the first address of the memory corresponds to, the comparator 612 and the corresponding coding element are omitted can.

In order to ensure the initial writing of the identification number, it is necessary that the Input 615 of the logic element 614 is blocked during the manufacture of the integrated circuit and then finally (signal 1) after introduction is made transferable. That is done by the activation circuit 617 enables the card to be controlled from outside at 618 only once in its life

In the following, an embodiment of the activation circuit 617 is described with reference to FIG.

Such a circuit can consist of a transistor 620 connected in series with a fuse element 621

An inverter 622 forms the output element at the junction of the transistor and the

Fuse. A diode 623 is interposed in order to prevent that during the blocking process

(which is generally done with the help of a pulse of the value VB, which is above the general supply VC of the

Circuits is effected) current flows towards the inverter

In addition, a resistor is located 624 between the input of the inverter and the positive terminal of ίο supply VC, This is when the fuse is intact, consequently, the input of the inverter to the ground potential (permeable diode), the output of inverter supplies the signal to the first

If the fuse is blown, the input of the inverter 622 carries the potential of the positive terminal of the

Supply and therefore the output carries a signal 0. Before the lock command is given, is at the output

of the inverter 616 a signal 0, which permits the writing process. If this is done, a signal is carried out

of sufficient duration on the control 618, the final switching of the element 617, whereby the element 614 is unlocked.

If one wishes to reduce the number of connection points, it is conditionally necessary to use the card to deliver the addresses in serial form: be it through a shift register, be it through a counter. The counter has the advantage of enabling the arrangement to operate based on a predetermined sequence of addresses (from address no. 0 to address 2047), which is not the case in the case of a shift register

In addition, the complexity of its integration is less than that of the shift register, so that the Counter (asynchronous, increasing) is brought forward.

In Fig. 7 shows an embodiment of the memory activation blocking circuit which is intended to forbid changing the content of the memory sections marked as prohibited in the case of a memory equipped with a counter 626. The blocking circuit is contained on the card 400 . In addition to the memory 609 (set up for 2048 words with one bit) and the blocking element 610, this embodiment has a decoder gate circuit 629, starting capacitors 627 and 633, an AES flip-flop formed from NOR gates 631 and 632, and an activation circuit 617 . The decoding circuit 629 is designed to detect in the form of a high level at the output the upper address y of the sections 0 - y coded as forbidden (address no. 83 in the example under consideration) or the bank account number, the 21 digits, ie 84 bits, which occupy the first 84 addresses of the memory. After applying the voltage (element 617 is activated), the output signal of the flip-flop is set in stable form as signal 1 because of the (only) pulse emitted by capacitor 633. The output of element 617 as well as element 629 is at a low level because of the automatic setting to zero which is arranged by capacitor 627 of counter 626 . The locking member 610 is consequently closed in a stable manner.

As soon as 84 clock pulses have been received on the serial addressing conductor 630 , the output of the decoder 629 is set to level 1, whereby the output of the flip-flop is forced to zero, which causes the blocking element to open.

The address range 0-83 is therefore protected in general from the write process, since the output "Maximum count" of the counter systematically resets the flip-flop to 1 at the moment the

Counter reaches address 0 by exceeding its capacity. The initial writing process is made possible by the fact that a level 1 is originally applied to the output of element 617 , which forces the flip-flop to 0 in a stable manner. After the initial write has been made and verified, a command 1 on conductor 618, maintained for a sufficient period in relation to the properties of element 617 , allows the flip-flop to flip-flop once and for all, i.e., toggle the flip-flop. h “the final irreversibility of the initial inscriptions.

The embodiment shown in Fig. 7 can in particular be used to a payment card create that contains sections coded with as forbidden in their memory

Addresses 0 to 49: personal authorization code,

Addresses 50 to 133: account number,

Addresses 134 to 233: name of the user,

Addresses 234 to 273: serial number of the card.

In the example shown with a memory with 2048 bits, 1774 bits remain available for financial purposes To save operations, e.g. B .:

Balance amount: 12 bits

Date: 16 bits

Validity 1 bit

Thus 61 operations with 29 bits can be stored. If the registration of the date is unimportant and if 10 bits are enough to represent the balance, there can be 161 operations with 11 bits in memory registered on the payment card.

The modified scheme in FIG. 8 represents an embodiment which allows the lower limit χ of the numerical forbidden "window" to be dimensioned to a value x other than zero, e.g. B. Oxy 2047, allowed. The elements already described have the same reference symbols with reference to the preceding figures.

§ This embodiment has a second address decoder 641 , a second flip-flop 634-635

ρ, its starting capacitor 636, a decoder 637, which consists of an exclusive OR element and an OR

H element 638 is formed:

fe | The decoder 637 determines in conjunction with the other decoders 641, 629 and the connected ones

Ü circuits have the following sequential function:

y O < A <x: writing possible

'As x <A <y. Writing prohibited

Il y </ 4 <2047: writing possible

(A is the address that is available at the parallel outputs of the counter 626 )

In Fig. 9 shows an embodiment of a memory activation inhibit circuit which is in particular: <■■> intended to allow reading of the contents of different memory sections (or zones) of the memory

> ij: forbid. The blocking circuit is located on the card 400. The information contained in this zone

ί; ■ never leave the card 400: they are intended to be processed inside the card by a processing means 646

p to be processed. In the embodiment shown in Figure 9, zone 0-x is for reading

I: ' '! (Itersays Zone 0 - y is forbidden for writing The blocking circuit of the writing device is already in

: -m in connection with F i g. 8 described words. This circuit is not described again, it carries the

S have the same reference numerals.

■ ί The decoder 640, the flip-flop 641-642, the star capacitor 643 and the output element 644 form the

essential elements of the blocking circuit of the Lesemiael. If the blocking element 644 is blocked, the information contained in the memory of the card cannot leave the card and reach the reading devices which are arranged outside the card, in particular in the data input / data output device.

; Confidential information contained in Zone 0 — χ of the storage facility may be e.g. B. serve to the

Writing in the memory, with the aid of the special processing means 646, certain words are coded in the following way: these words enter their initial coding through the write input 647 and are output on the conductor 649 in the new code intended for the word prohibiting reading .

A switching element 648, which is actuated by the write command input 650 here, allows the PROPERLY jo ^r Permitted processing of the actual electrical writing operations in which the circuits with weak

Power can be isolated during the write phase.

In addition 6 sheets of drawings

35

Claims (10)

Patent claims: 1. Data exchange system with at least one data input / output device and at least a portable data carrier arrangement, at least one of which is an independent programmable data memory and an integrated circuit forming the control and addressing circuit thereof, wherein by means of the data input / data output device, data can be read from the portable data carrier arrangement or can be written into them and the data carrier arrangement only after a connection has been established The supply and control voltages required for their operation with the data input / output device is supplied, characterized in that a lock (602, 608 in FIG. 4; 610 in Fi g. 5, 7; 644 in FIG. 9) is provided that provides access (write / read) to the memory areas of the Data memory (601 in F i g. 4; 609 in F i g. 5, 7) allowed to be locked and the selective depending on in the information contained in the integrated circuit, which is provided by storage elements of the data memory or are determined by further circuit elements, come into operation and then unconditionally and is irreversibly in operation 2. Data exchange system according to claim 1, characterized in that a further bit (B ₉ ) is added to each word to be written into the memory (601) which activates the lock (602) to prevent further writing (FIG. 4). 3. Data exchange system according to claim 1, characterized in that the lock (610) has an address comparator circuit (611,612), which is only associated with the occurrence of certain, the data memory (609) delivers a signal releasing the lock (610) (FIG. 5). 4. Data exchange system according to claim 3, characterized in that the address comparator circuit (611,612) is housed in the associated data carrier arrangement. 5. Data exchange system according to claim 3, characterized in that the address comparator circuit (611,612) between the addressing circuit of the data memory (609) and a coding device device (A. B) is provided and effectively controls the lock (610) in the event that the memory address occurring in each case is a prohibited address (FIG. 5). 6. Data exchange system according to claim 3 or 4, characterized in that the address comparator circuit (611,612) to control the lock (610) via a logic element (614), which thereby in the transferable state it can be kept that at the input of the logic element (614) an activation jo approximate circuit (617) of the integrated circuit is connected, which irreversible the logic element can change course (Fig. 5,6). 7. Data exchange system according to claim 3 or 4, characterized in that at least one decoding link (629) is provided with which the limit addresses of forbidden memory sections of the data memory (609) can be determined (FIG. 7). 8. Data exchange system according to claim 7, characterized in that the decoding link (629) the lock (610) preventing the writing of data in the data memory via a Toggle switch (631,632) controls (Fig. 7). 9. Data exchange system according to claim 8, characterized in that the state of the trigger circuit (631,632) can be determined by means of activation circuit (617) connected to this. 10. Data exchange system according to one or more of the preceding claims, wherein the data transmission device Contains reading devices that are prohibited by a lock on reading data from encoded memory sections are prevented, characterized in that the data carrier arrangement Contains processing means (646) connected to control circuits of the data memory (609) and process the data in the data carrier arrangement in question which are prohibited for reading Storage sections of the data memory (609) are included.