DE19845316C2 - Stapelbares Ball-Grid-Array-Halbleitergehäuse und Verfahren zu dessen Herstellung - Google Patents
Stapelbares Ball-Grid-Array-Halbleitergehäuse und Verfahren zu dessen HerstellungInfo
- Publication number
- DE19845316C2 DE19845316C2 DE19845316A DE19845316A DE19845316C2 DE 19845316 C2 DE19845316 C2 DE 19845316C2 DE 19845316 A DE19845316 A DE 19845316A DE 19845316 A DE19845316 A DE 19845316A DE 19845316 C2 DE19845316 C2 DE 19845316C2
- Authority
- DE
- Germany
- Prior art keywords
- metal
- semiconductor chip
- conductor tracks
- metal conductor
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/055—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads having a passage through the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73219—Layer and TAB connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
Claims (8)
einen Träger (21), der eine Trägerplatte (23), einen auf einem Oberteil der Trägerplatte (23) entlang deren Rand teil geformten Trägerrahmen (25), an oberen und unteren Oberflächen des Trägerrahmens (25) freigelegte Metallmuster (26), an einem Unterteil der Trägerplatte (23) geformte und mit den Metallmustern (26) verbundene erste Metalleiter bahnen (24a), eine erste Lötstoppschicht (27), die die er sten Metalleiterbahnen (24a) abschirmt, und durch teilweises Freilegen der ersten Metalleiterbahnen (24a) geformte Ver bindungsteile (24b) beinhaltet;
einen Halbleiterchip (1), der auf der oberen Oberfläche der Trägerplatte (23) des Trägers (21) angebracht ist und der auf seinem oberen Rand Kontaktflächen (6) aufweist;
zweite Metalleiterbahnen (4a), die auf einem Oberteil des Halbleiterchips (1) angebracht sind;
Metallzuleitungen (4b), die mit Endteilen der zweiten Metalleiterbahnen (4a) und den randseitigen Kontaktflächen (6) des Halbleiterchips (1) verbunden sind und zu einer Außenseite des Halbleiterchips (1) verlaufen, um so mit oberen Oberflächen der Metallmuster (26) verbunden zu sein;
eine Mehrzahl von leitenden Kugeln (8a), die an den zweiten Metalleiterbahnen (4a) am oberen Teil des Halblei terchips (1) angebracht sind; wobei die Kugeln (8a) jeweils den Verbindungsteilen (24b) auf der unteren Oberfläche der Trägerplatte (23) entsprechen.
eine zweite Lötstoppschicht (5), die die zweiten Metal leiterbahnen (4a) bedeckt; und
eine Kapselung (28), die die zweiten Metalleiterbahnen (4a), die Metallzuleitungen (4b), die Metallmuster (26) auf der oberen Oberfläche des Trägerrahmens (25) und Teile der oberen Oberfläche des Halbleiterchips (1) bedeckt.
Formen eines Trägers (21), der eine Trägerplatte (23), einen auf einem Oberteil der Trägerplatte (23) entlang deren Randteil geformten Trägerrahmen (25), an oberen und unteren Oberflächen des Trägerrahmens (25) freigelegte Metallmuster (26), an einem Unterteil der Trägerplatte (23) geformte und mit den Metallmustern (26) verbundene erste Metalleiterbah nen (24a), eine erste Lötstoppschicht (27), die die ersten Metalleiterbahnen (24a) abschirmt, und durch teilweises Freilegen der ersten Metalleiterbahnen (24a) geformte Ver bindungsteile (24b) beinhaltet;
Anbringen von weiteren Metallmustern (4) auf einem Halbleiterchip (1), der auf seinem oberen Rand Kontaktflä chen (6) aufweist, wobei die weiteren Metallmuster (4) zwei te Metalleiterbahnen (4a) und Metallzuleitungen (4b) umfas sen;
Formen einer zweiten Lötstoppschicht (5) auf den zwei ten Metalleiterbahnen (4a);
Freilegen von Teilen oberer Oberflächen der zweiten Metalleiterbahnen (4a) durch teilweises Entfernen der zwei ten Lötstoppschicht (5);
Anbringen des Halbleiterchips (1) auf der oberen Ober fläche der Trägerplatte (23);
Formen der zweiten Metalleiterbahnen (4a) und Metallzu leitungen (4b) durch Anbringen der weiteren Metallmuster (4) an den randseitigen Kontaktflächen (6) des Halbleiterchips (1);
Verbinden eines Endteils jeder der Metallzuleitungen (4b) mit oberen Oberflächen der ersten Metallmuster (26)
Aufbringen einer Kapselung (28) zur Bedeckung der wei teren Metallmuster (4) und der randseitigen Kontaktflächen (6) des Halbleiterschips (1); und
Anbringen leitender Kugeln (8a) an entsprechenden frei gelegten Teilen der zweiten Metalleiterbahnen (4a) des obe ren Teils des Halbleiterchips (1).
Anbringen eines Elastomers (2), auf dessen Ober- und Unterseiten ein Klebstoffharz (3) mit hohem Haftvermögen aufgebracht ist, arg der oberen Oberfläche des Halbleiter chips (1); und
Anbringen der weiteren Metallmuster (4) auf dem Elasto mer (2).
Plazieren der leitenden Kugeln (8a) auf den freigeleg ten Teilen der zweiten Metalleiterbahnen (4a); und
Anwenden eines Fließlöt-Prozesses auf die leitenden Kugeln (8a).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980020098A KR100266693B1 (ko) | 1998-05-30 | 1998-05-30 | 적층가능한 비지에이 반도체 칩 패키지 및 그 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19845316A1 DE19845316A1 (de) | 1999-12-02 |
DE19845316C2 true DE19845316C2 (de) | 2002-01-24 |
Family
ID=19537977
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19845316A Expired - Fee Related DE19845316C2 (de) | 1998-05-30 | 1998-10-01 | Stapelbares Ball-Grid-Array-Halbleitergehäuse und Verfahren zu dessen Herstellung |
Country Status (4)
Country | Link |
---|---|
US (2) | US6291259B1 (de) |
JP (1) | JP3063032B2 (de) |
KR (1) | KR100266693B1 (de) |
DE (1) | DE19845316C2 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6768191B2 (en) | 2001-08-10 | 2004-07-27 | Infineon Technologies Ag | Electronic component with stacked electronic elements |
Families Citing this family (138)
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KR100318293B1 (ko) * | 1999-11-02 | 2001-12-24 | 김 무 | 플립칩 반도체패키지 및 그 제조방법 |
KR100324333B1 (ko) | 2000-01-04 | 2002-02-16 | 박종섭 | 적층형 패키지 및 그 제조 방법 |
KR100386081B1 (ko) * | 2000-01-05 | 2003-06-09 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그 제조 방법 |
JP3813402B2 (ja) * | 2000-01-31 | 2006-08-23 | 新光電気工業株式会社 | 半導体装置の製造方法 |
KR100639700B1 (ko) * | 2000-02-14 | 2006-10-31 | 삼성전자주식회사 | 칩 스케일 적층 칩 패키지 |
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Also Published As
Publication number | Publication date |
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KR19990086916A (ko) | 1999-12-15 |
KR100266693B1 (ko) | 2000-09-15 |
US20010048151A1 (en) | 2001-12-06 |
JP3063032B2 (ja) | 2000-07-12 |
JPH11354669A (ja) | 1999-12-24 |
US6291259B1 (en) | 2001-09-18 |
DE19845316A1 (de) | 1999-12-02 |
US6407448B2 (en) | 2002-06-18 |
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