DE19841893A1 - Datenverarbeitungseinheit - Google Patents
DatenverarbeitungseinheitInfo
- Publication number
- DE19841893A1 DE19841893A1 DE19841893A DE19841893A DE19841893A1 DE 19841893 A1 DE19841893 A1 DE 19841893A1 DE 19841893 A DE19841893 A DE 19841893A DE 19841893 A DE19841893 A DE 19841893A DE 19841893 A1 DE19841893 A1 DE 19841893A1
- Authority
- DE
- Germany
- Prior art keywords
- register
- logic
- unit
- boolean
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000006870 function Effects 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
Description
OUT1 = (a & b)|(c & d);
D0: 2 stellt c dar; und
Claims (11)
einen ersten Logikoperator, der mit einem ersten und zweiten Register als Eingaberegister verbunden sein kann und ein Aus gangs-Bit als Ergebnis einer Logikoperation erzeugt, und
einen Bool'schen Operator, der das Ausgangs-Bit des ersten Logikoperators als erstes Eingangssignal und ein zweites Ein gangs-Bit von einem dritten Register empfängt, und der ein Ausgangs-Bit als Ergebnis einer Bool'schen Operation erzeugt.
eine Schiebeeinrichtung, die mit einem ersten Register ver bunden ist, um eine Schiebeoperation auf dem Register durch zuführen, und
einen Logikoperator, der mit einem zweiten und dritten Regi ster als Eingaberegister verbunden werden kann und ein Aus gangs-Bit als Ergebnis einer Logikoperation erzeugt, wobei das Ausgangs-Bit in dem ersten Register gespeichert ist.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/928,427 | 1997-09-12 | ||
US08/928,427 US6961846B1 (en) | 1997-09-12 | 1997-09-12 | Data processing unit, microprocessor, and method for performing an instruction |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19841893A1 true DE19841893A1 (de) | 1999-03-18 |
DE19841893B4 DE19841893B4 (de) | 2005-06-30 |
Family
ID=25456219
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19841893A Expired - Fee Related DE19841893B4 (de) | 1997-09-12 | 1998-09-11 | Mikrokontroller |
Country Status (2)
Country | Link |
---|---|
US (1) | US6961846B1 (de) |
DE (1) | DE19841893B4 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104050077A (zh) * | 2013-03-15 | 2014-09-17 | 英特尔公司 | 利用多个测试源来提供或(or)测试和与(and)测试功能的可融合指令和逻辑 |
US9886277B2 (en) | 2013-03-15 | 2018-02-06 | Intel Corporation | Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8526601B2 (en) * | 2004-04-05 | 2013-09-03 | Advanced Micro Devices, Inc. | Method of improving operational speed of encryption engine |
US20110138156A1 (en) * | 2009-10-15 | 2011-06-09 | Awad Tom | Method and apparatus for evaluating a logical expression and processor making use of same |
US20120030451A1 (en) * | 2010-07-28 | 2012-02-02 | Broadcom Corporation | Parallel and long adaptive instruction set architecture |
US9672037B2 (en) * | 2013-01-23 | 2017-06-06 | Apple Inc. | Arithmetic branch fusion |
JP2020144480A (ja) * | 2019-03-04 | 2020-09-10 | パナソニックIpマネジメント株式会社 | プロセッサ及びプロセッサの制御方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3656109A (en) * | 1970-03-13 | 1972-04-11 | Sperry Rand Corp | Hamming distance and magnitude detector and comparator |
US3723710A (en) * | 1971-06-28 | 1973-03-27 | Ibm | Method and device for reading and decoding a high density self-clocking bar code |
US4061880A (en) * | 1975-03-21 | 1977-12-06 | Dicom Systems, Ltd. | Time-multiplex programmable switching apparatus |
US4003033A (en) * | 1975-12-22 | 1977-01-11 | Honeywell Information Systems, Inc. | Architecture for a microprogrammed device controller |
US4112490A (en) * | 1976-11-24 | 1978-09-05 | Intel Corporation | Data transfer control apparatus and method |
US4257110A (en) * | 1977-04-19 | 1981-03-17 | Semionics Associates, Inc. | Recognition memory with multiwrite and masking |
US4164025A (en) * | 1977-12-13 | 1979-08-07 | Bell Telephone Laboratories, Incorporated | Spelled word input directory information retrieval system with input word error corrective searching |
US4163211A (en) * | 1978-04-17 | 1979-07-31 | Fujitsu Limited | Tree-type combinatorial logic circuit |
JPS5569856A (en) * | 1978-11-22 | 1980-05-26 | Toshiba Corp | Overlap system |
US4338675A (en) * | 1980-02-13 | 1982-07-06 | Intel Corporation | Numeric data processor |
US4533992A (en) * | 1982-02-22 | 1985-08-06 | Texas Instruments Incorporated | Microcomputer having shifter in ALU input |
US4728927A (en) * | 1984-09-28 | 1988-03-01 | Aman James A | Apparatus and method for performing comparison of two signals |
US5493687A (en) * | 1991-07-08 | 1996-02-20 | Seiko Epson Corporation | RISC microprocessor architecture implementing multiple typed register sets |
US5251203A (en) * | 1991-12-23 | 1993-10-05 | Xerox Corporation | Hub privacy filter for active star CSMA/CD network |
JPH06332664A (ja) * | 1993-03-23 | 1994-12-02 | Toshiba Corp | 表示制御システム |
US5442577A (en) * | 1994-03-08 | 1995-08-15 | Exponential Technology, Inc. | Sign-extension of immediate constants in an alu |
US5781457A (en) * | 1994-03-08 | 1998-07-14 | Exponential Technology, Inc. | Merge/mask, rotate/shift, and boolean operations from two instruction sets executed in a vectored mux on a dual-ALU |
US5751614A (en) * | 1994-03-08 | 1998-05-12 | Exponential Technology, Inc. | Sign-extension merge/mask, rotate/shift, and boolean operations executed in a vectored mux on an ALU |
US5692207A (en) * | 1994-12-14 | 1997-11-25 | International Business Machines Corporation | Digital signal processing system with dual memory structures for performing simplex operations in parallel |
US5764550A (en) * | 1996-07-22 | 1998-06-09 | Sun Microsystems, Inc. | Arithmetic logic unit with improved critical path performance |
-
1997
- 1997-09-12 US US08/928,427 patent/US6961846B1/en not_active Expired - Lifetime
-
1998
- 1998-09-11 DE DE19841893A patent/DE19841893B4/de not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104050077A (zh) * | 2013-03-15 | 2014-09-17 | 英特尔公司 | 利用多个测试源来提供或(or)测试和与(and)测试功能的可融合指令和逻辑 |
CN104050077B (zh) * | 2013-03-15 | 2017-07-28 | 英特尔公司 | 利用多个测试源来提供测试的处理器、处理系统和方法 |
US9886277B2 (en) | 2013-03-15 | 2018-02-06 | Intel Corporation | Methods and apparatus for fusing instructions to provide OR-test and AND-test functionality on multiple test sources |
US10296347B2 (en) | 2013-03-15 | 2019-05-21 | Intel Corporation | Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources |
Also Published As
Publication number | Publication date |
---|---|
US6961846B1 (en) | 2005-11-01 |
DE19841893B4 (de) | 2005-06-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8110 | Request for examination paragraph 44 | ||
8125 | Change of the main classification |
Ipc: G06F 9/305 |
|
8127 | New person/name/address of the applicant |
Owner name: INFINEON TECHNOLOGIES NORTH AMERICA CORP., SAN JOS |
|
8364 | No opposition during term of opposition | ||
R082 | Change of representative |
Representative=s name: PATENTANWAELTE WESTPHAL MUSSGNUG & PARTNER, DE |
|
R081 | Change of applicant/patentee |
Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES NORTH AMERICA CORP., SAN JOSE, CALIF., US Effective date: 20121128 Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES NORTH AMERICA CORP., SAN JOSE, US Effective date: 20121128 |
|
R082 | Change of representative |
Representative=s name: WESTPHAL, MUSSGNUG & PARTNER PATENTANWAELTE MI, DE Effective date: 20121128 Representative=s name: PATENTANWAELTE WESTPHAL MUSSGNUG & PARTNER, DE Effective date: 20121128 |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |