DE19825011A1 - Integrated semiconductor memory device - Google Patents

Abstract

The memory device (1) has a redundancy circuit (3,4) for replacement of a defective memory cell (NZ1,NZ2,NZ3) by a redundant memory cell (R1,R2,R3), with a programming device (3) within the redundancy circuit for programming the address of the redundant memory cell. The redundant memory cells within a column (RS) of the redundancy matrix can be used for replacing memory cells within different columns (NS) of the memory matrix, the programming device providing the column address of the replaced memory cell and a partial line address.

Description

The invention relates to an integrated semiconductor memory device with a half on a semiconductor substrate headed storage device trained redundancy scarf arrangement for the replacement of a defective memory cell the integrated semiconductor memory device by selection a Red also arranged on the semiconductor substrate and memory cell, the memory cells and redundancy memory cells in normal columns and rows or redundancy Columns are organized, and the replacement of normal memory he cells by redundancy memory cells column by column follows, and the redundancy circuitry a program Rungseinrichtung for fixed programming an address of the Has redundancy memory cells.

In modern integrated semiconductor memories such as Modular Embedded DRAM memory with typical Ge total storage capacities between 0.25 Mbit and about 128 Mbit the memory cells are organized in several memory blocks siert, being in operation for reasons of electricity and time savings depending on address signals as a rule because only one memory block is activated. Usually are the generally uniform memory blocks arranged side by side and / or one above the other and result in the total the total capacity of the semiconductor memory direction. Each block of memory is unique in itself permanent memory and contains especially for the line or "Row" area all required to operate the memory the peripheral circuit elements. Such a spit cherblock is therefore not easily divisible. If more re such memory blocks are stacked one above the other, so be  each of them sits their own line control, while the column control (or "column" control) with column decoders and sense amplifiers (especially Secon dary sense amplifiers) suitably from all other stacked memory blocks can be shared. By stipulating that only data from one of these Memory blocks are read or written in avoided conflicts in this regard.

To increase the yield in the production of this semi-lead ter memory it is known to redundant lines with Redun precedence memory cells along the redundant lines hen. Memory with several memory blocks accordingly have over the normal bit lines with normal memory cells in addition one to eight or sixteen, for example dante lines with redundancy memory cells. The talk danten lines are used during operation, if necessary means if redundant memory cells defective normal memory to replace cells ("redundancy") instead of the norm len lines controlled. This is done via so-called Red andanzdecoder, based on the address of each normal Line with the defective memory cells to be replaced per are grammable. The programming is done in on known way about so-called fuse elements with tels electrical current or by means of a laser beam un are breakable.

Fig. 2 shows schematically a previously used semiconductor memory device 1 with a cell array 2 , the normal memory cells are organized in the known manner in a matrix in columns and rows. The arrangement and mode of operation of the parts of a modern integrated semiconductor memory device, which are shown only schematically in FIG. 2, on the basis of a semiconductor substrate (not shown in any more detail) are well known and therefore do not need to be explained in detail. The redundancy circuitry works column by column, ie there is a single bit error in the cell field 2 of a memory cell block, for example in the form of a single defective normal cell NZ, which error is to be repaired by column redundancy, so for the normal column NS, in which the defective cell NZ is located, a whole, redundant column RS is used. The number of repairable single-bit errors is therefore limited to the number of redundant columns.

The invention has for its object an integrated Semiconductor memory with redundancy circuitry to provide which, if necessary, that is if there are defective memory cells, a better off allows use of the redundancy circuit arrangement.

This task is accomplished through an integrated semiconductor memory Resolved device according to claim 1.

The semiconductor integrated memory device according to the Er is characterized in that the redundancy cells of a certain redundancy column or redundancy Row of several normal memory cells from different ones Normal columns are assignable, and in the programming direction next to the address of the normal column to be replaced also a partial line address of the one to be replaced Normal memory cells is stored.

The invention is based initially on the knowledge, at Auf an error caused by column redundancy ("Column" - Redundancy) should be repaired, not entire columns set, but only to replace parts of these columns. The partial replacement is achieved according to the invention in which next to the column address in the ge for the respective repair hearing fuse unit of the programming device also egg  ne partial line address is stored. The size of the partial line address specifies how high (i.e. how many lines one above the other) is the part of the column to be replaced. The main advantage of the invention is that a redundancy column, which in the known case only a single column repair enables significantly more repairs options can be brought out. Invention Ge This depends on how many parts the columns are broken up into be shared.

Appropriate developments of the invention are in the Un claims specified.

An embodiment of the invention is described below the drawing explained in more detail. It shows:

Figure 1 is a schematic representation of a DRAM memory according to an embodiment of the invention. and

Fig. 2 is a schematic representation of a previously used th integrated semiconductor memory device.

Fig. 1 shows schematically a semiconductor memory device 1 according to the invention with a cell array 2 , the normal memory cells are organized in normal columns NS and (not shown in more detail) normal rows, for example 512 rows and 2048 columns are present. In addition to the cell array 2 , a redundancy circuit arrangement with a programming device 3 , a redundancy control circuit 4 and with at least one redundancy column RS is arranged on the same semiconductor substrate of the semiconductor memory device 1 . The redundancy circuit arrangement works column by column, 3 programmable fuse elements being arranged in the programming device, which can be determined by light or current to determine the address of the redundancy column RS for the replacement of a defective memory cell NZ1, NZ2, NZ3 . The circuit 4 summarizes the redundancy decoder and lines required to control the selected redundancy columns. After It is not only stored in the programming device 3, the erfor to control the respective redundancy column RS derliche column address contraption, but also a partial row address to be replaced normal memory cells NZ1, NZ2, NZ3. In this way, it is possible to repair a single defective normal cell NZ1, NZ2, or NZ3, not the complete redundancy column RS, but only a very specific part of the redundancy column RS. For example, part of the redundancy column is used to repair three normal memory cells NZ1, NZ2, NZ3 from the three different normal columns NS1, NS2, NS3, namely part R1 for repairing normal cell NZ1, part R2 for repairing Normal cell NZ2, and the part R3 used to repair the normal cell NZ3. The parts R1, R2, R3 can comprise individual cells of the redundancy column, but also several individual cells of the redundancy column RS. The size of the partial row address specifies how high the proportion of the affected normal column is to be replaced, ie how many rows one above the other make up this part.

For example, in the case of 512, they are arranged one above the other Neten word lines for decoding a line nine lines address bits required. If you always have packages of eight on top of each other want to train the existing lines, so you can three last significant bits (LSB = Last Significant Bits) neglect the row address and must be in the column Fuse unit another six fuse elements for the partial time Provide len address. This means that instead of only one repair theoretically a maximum of 64 repairs can perform (8 × 64 = 512). However, this means  that you also have to reserve a maximum of 64 fuse units, because a complete fuse-in for every repair must be reserved. The number of per redundant The possible repairs column is up to a maximum of 64 in this calculation example depending on the number of provided fuse units limited, definitely ever but larger than in the previously known approach.

At this point there is the following restriction: Due to the Activation schemes used in DRAM memories can only such memory cells are replaced with each other on the the same line and that in the line activation were activated before column access. Because every column part can only be replaced once by means of the fuse elements thus only one error per line by a Redun danz column to be replaced. To more than one mistake on egg Replacing a line becomes more than just a speech danz column required. However, this is not a problem significant since there are several errors that occur on one line corrected by a single line repair.

Claims (5)

1. Integrated semiconductor memory device with a redundancy circuit arrangement ( 3 , 4 ) formed on a semiconductor substrate of the semiconductor memory device ( 1 ) for the replacement of a defective memory cell (NZ1, NZ2, NZ3) of the integrated semiconductor memory device ( 1 ) by selection a redundancy memory cell (R1, R2, R3) likewise arranged on the semiconductor substrate, the memory cells and redundancy memory cells (R1, R2, R3) being organized in normal columns (NS) and rows or redundancy columns (RS), and the replacement of normal memory cells by redundancy memory cells (R1, R2, R3) in columns or rows, and the redundancy circuit arrangement has a programming device ( 3 ) for fixed programming of an address of the redundancy memory cells (R1, R2, R3), characterized in that the Redundancy memory cells (R1, R2, R3) of a certain redundancy column (RS) different normal memory cells from different The normal columns (NS) can be assigned, and a partial row address of the normal memory cells to be replaced (NZ1, NZ2, NZ3) is also stored in the programming device ( 3 ) in addition to the address of the normal column to be replaced (NS). 2. Semiconductor memory device according to claim 1, characterized in that the programming device ( 3 ) for fixed programming an address of the redundancy memory cells (R1, R2, R3) by light or current action has separable fuse elements. 3. A semiconductor memory device according to claim 2, characterized in that in the programming device ( 3 ) each the column addresses and memory cells to be replaced are permanently programmed. 4. A semiconductor memory device according to one of claims 1 to 3, characterized in that the memory cells of the integrated semiconductor memory device ( 1 ) are formed in blocks and are addressable. 5. The semiconductor memory device according to claim 4, characterized, that the memory blocks each have their own line control have, and the column controls and sense amplifiers al len memory blocks are assigned together.