DE19751560A1 - ATM multiplexer unit for high data transfer speed - Google Patents

Abstract

The arrangement is connected on one side with a switching component (X15) over a high-frequency data bus (DB), and on the other side with at least one subscriber connection arrangement over respectively at least one subscriber data bus (TB). The multiplexer unit (MUX) contains a reception module (R) for transmission of data from a subscriber connection arrangement to the switching component, and transmitting module (T) for transmission of data from the switching component to a subscriber connection unit. The reception module and the transmitting module comprise individual memories (FIFO0,..., FIFO3) for each subscriber data bus (TB0,..., TB3). Data in the reception module are written with an individual connection arrangement through the respective subscriber, with a pre-settable clock rate (TBCLOCK), into an individual memory. The data are read with a clock rate (DBCLOCK), pre-settable through the switching component. Data in the transmitting module are written into an individual memory, with the clock rate determined by the switching component, and are read with the clock rate determined by the respective subscriber connection arrangement.

Description

Due to the increasing need for a transmission of video-in formation in modern communication technology, such as B. Fixed and moving images in videophone applications, or the Representation of high-resolution graphics on modern personalities nalcomputers, the importance of transmission and Ver averaging techniques for high data transfer rates (larger 100 Mbit / s). A known data transmission method for ho he data speed is asynchronous transfer mode (ATM). A data transmission based on the asynchronous trans fer mode currently enables a variable transmission bitra up to 622 Mbit / s.

Known switching centers, including those based on the Asynchronous transfer mode are usually modular builds. There are usually a large number of assemblies - the z. B. an interface for connecting subscriber lines or central control - on one, common, central plug assembly, all modules, egg ner so-called "backplane" insertable and with this connected to each other. The modularity of the Ver averaging devices enables easy Adaptation of a switching device to different ones Configurations, as well as a simplified error analysis Services.

In particular the switching devices (e.g. switching networks) of switching systems are on one or more separate switching modules arranged, which also can be plugged in on the central plug assembly.

From the data sheet "MOS INTEGRATED CIRCUIT µPD98410", NEC Cor poration, 1997, Document No. S12624EJ1V0DS00 (1st edition)  is a highly integrated circuit block known an addressing of several subscriber-related cuts put on a high-frequency ATM-specific bus interface (UTOPIA: Universal Test & Operations PHY Interface for ATM) allowed.

With an arrangement of such a highly integrated through switch module on a separate circuit board would for structural reasons one, the high-frequency Switch-through module with other modules - in particular Subscriber connection facilities - connecting, high-frequency ter (clock rate <50 MHz) data bus of the highly integrated through switch modules - even with smaller switching equipment tungen - have a length of about 30 to 40 cm, which consists of theoretical reasons for the desired clock rate is great. To make matters worse, contacting several modules with the high-frequency data bus for opening the maintenance of management theory additional reduction in bus length required.

The present invention has for its object a Specify arrangement by which a longer transmission stretch between the highly integrated circuit module and subscriber line equipment upon receipt of the clock rate of the high-frequency data bus can be implemented.

This object is achieved according to the invention with the Features of claim 1.

The present invention is based on the idea that high integrated circuit block on the central connector to place assembly of an ATM switching device and thus reducing the cable length.

The arrangement according to the invention has the advantage that interposing a multiplexer device between  the highly integrated switching module and subscriber connection the length of the high-frequency data bus - the the highly integrated switching module with the Mul tiplexer equipment connects - be kept very low can.

By interposing the multiplexer devices becomes a time decoupling of the high-frequency data bus realized by the subscriber data buses so that each one individual subscriber data bus with a lower, given if individually by the subscriber connection device Predeterminable clock rate can be operated. It also arises between a multiplexer and a subscriber closing device a pure point-to-point connection, d. H. only two connections per connecting line. The so he targeted more favorable line characteristics allow a ge larger than the high-frequency data bus Length of the subscriber data bus.

Advantageous developments of the invention are in the Un claims specified.

The implementation of the subscriber data buses with a first Da width - preferably 8 bits - on the high-frequency data tenbus with a second data width - preferably 16 bits - and conversely, allows the use of conventional ones 8-bit wide blocks in the subscriber line facility gene.

An embodiment of the invention will follow hand of the drawing explained in more detail.  

Show:

FIG. 1 is a structural diagram schematically illustrating the processing on a base assembly of a Vermittlungseinrich arranged substantially functional units;

Figure 2 is a structural diagram for the schematic representation of the essential functional units of a multiplexer device.

Fig 3a is a structural diagram for the schematic representation of the essential functional units of a Empfangsmo duls a multiplexer.

FIG. 3b is a structural diagram for the schematic representation of the essential functional units of a transmission module of a multiplexer;

Fig. 4 is a structural diagram schematically showing egg nes busindividuellen transmit register and a mul tiplexerindividuellen transmit register;

Fig. 5 is a structural diagram for the schematic of busindividuellen address registers.

Fig. 1 is a schematic representation of the sisbaugruppe on a Ba BBG shows an ATM switching means is arrange th essential functional units. The basic module BBG has a highly integrated circuit module X15 - hereinafter referred to only as circuit module X15 - which is connected via a memory data bus to a first memory MEM1 and a second memory MEM2. The first memory MEM1 is used for intermediate storage of useful information stored in an ATM cell. In the second memory MEM2, routing information for the ATM cells to be switched is stored in the form of switching tables. For a connection to subscriber connection devices (not shown in the drawing), the switching module X15 has a first and a second high-frequency (clock rate: 50 MHz) data bus DB0, DB1 with a 16-bit width.

The basic module BBG has eight connection slots SLOT0, . . ., SLOT7 for contacting subscriber lines units, as well as four, in a closer area of the scarf tebausteins X15 MUX0 multiplexer devices, . . ., MUX3 on. A first and a second multiplexer device MUX0, MUX1 are over the first high-frequency data bus DB0 and third and fourth multiplexers MUX2, MUX3 are via the second high-frequency data bus DB1 connected to the switching module X15. By the arrangement of the multiplexer devices MUX0,. . ., MUX3 in a nä The length of the switch-over block X15 becomes larger the first and second high-frequency data bus DB0, DB1 minimized.

For the connection of subscriber connection devices the switching module X15 is a first connector SLOT0 slot via two subscriber data buses TB and one two ter slot SLOT1 via two further subscriber data tenbuses TB with the first multiplexer device MUX0 ver bound. The third to eighth connection is analogous slot SLOT2,. . ., SLOT7 to the second to fourth multiple xereinrichtung MUX1,. . ., MUX3 connected.

Fig. 2 is a schematic representation of the essential functional units is a multiplexer MUX. The multiplexer device MUX has a reception module R, via which data are transmitted from a subscriber connection device to the switching module X15. Furthermore, the multiplexer device MUX has a transmission module T, via which data from the switching module X15 are transmitted to a subscriber connection device.

On the input side, the reception module R has four bus-specific ones Receiver interfaces RP0,. . ., RP3 on, over the four to the Multiplexer device MUX connected subscriber data  buses TB0,. . ., TB3, each with a bus-specific emp catch memory FIFO0,. . ., FIFO3 are connected. These are with connected to a receive multiplexer module RMUX, the four incoming subscriber data buses TB0,. . ., TB3 to go out to the reception via a so-called "Utopia port" UP multiplexer module RMUX connected, high-frequency data bus DB summarizes. A reception arbitration facility RA controls on the basis of information transmitted by "Utopiaport" UP tion, which input-bus-specific memory FIFO0,. . ., FIFO3 for a transfer of cached ATM cells to the interconnection module X15, via the receive multiplex xermodul RMUX connected to the high-frequency data bus DB becomes.

The transmission module T has a "utopia port" UP on the input side via which the high-frequency data bus DB to a transmitter tiplexer module TUUK is connected to the incoming high-frequency data bus DB on four outgoing subscriber Da tenbuses TB0,. . ., TB3 splits. The transmission multiplexer module On the output side, TUUK has four individual bus transmitters FIFO0,. . ., FIFO3 connected in which to participants cached directions to be transmitted ATM cells become. The four bus-specific transmit memories FIFO0,. . ., FIFO3 are via four bus-specific transmission interfaces TP0, . . ., TP3 with the respective subscriber data buses TB0,. . ., TB3 connected. A transmission arbitration device TA opens due to information stored in the transmitter module T, in which bus-specific transmit memory FIFO0,. . ., FIFO3 one, ATM cell arrived via the high-frequency data bus DB is cached.

By connecting a subscriber connection device with separate receiver or transmission interfaces (RP0,..., RP3; TP0,. . ., TP3) for each subscriber data bus TB0,. . ., TB3, ent there is a defined point-to-point connection between egg ner subscriber connection device and the respective recipient  ger or transmit interface (RP0,..., RP3; TP0,..., TP3). The allow more favorable line properties achieved with it one more generous than the high-frequency DB data bus measured length of the subscriber data bus TB0,. . ., TB3.

Before going into the other figures, he it seems appropriate for a better understanding of them, briefly outline the essential structure of an ATM message. In the known as Asynchronous Transfer Mode (ATM) over Carrying procedures are data packets for data transport fixed length, so-called cells used. An ATM cell sets out of one that rele for the transport of an ATM cell vanten switch data containing five bytes long Cell header, the so-called "header" and a 48 byte long User data field, the so-called "payload" together.

Fig. 3a shows a schematic representation of the main functional units of the reception module R of the MUX Multiplexerein direction. The bus-specific receive memories FIFO0,. . ., FIFO3 each consist of n (e.g. n = 80) memory cells MEM1,. . ., MEMn together. The memory cells MEM1,. . ., MEMn each have a storage capacity of 64 bytes, so that MEM1,. . ., MEMn a 53 byte ATM cell can be stored. Each memory cell MEM1,. . ., MEMn is subdivided into two parallel 32-byte sub-memories TSP1, TSP2, with storage of data via a subscriber data bus TB0,. . ., TB3 arriving ATM cell byte byte al ternary, so that z. B. a first byte 1 of an incoming ATM cell in the first partial memory TSP1, a second byte 2 in the second partial memory TSP2, a third byte 3 in the first partial memory TSP1 following the first byte 1, etc., is buffered.

In the receiver interfaces RP0,. . ., RP3 is based on a information stored in the cell header of an ATM cell checks whether a currently received byte is a cell identifier  is the defining SOC byte (Start Of Cell). Is that ak If the received bytes are not a SOC byte, it will - in the above described way - following the previous byte in the memory cell MEM1 currently to be filled. . ., MEMn shouted ben. If the currently received byte is a SOC byte, a new memory cell MEM1,. . ., MEMn selected and that currently received bytes are stored in this. The ATM cells who the one with, through the respective subscriber connection establishment of predefined clock rate TB_CLOCK in the bus indivi dual receive memory FIFO0,. . ., FIFO3 written.

If one in a memory cell MEM1,. . ., MEMn intermediate Stored ATM cell requested by the switching module X15 If this is changed, this is done using a through-switch module X15 predefined clock rate DB_CLOCK from the memory cell MEM1, . . ., MEMn read out and via the receive multiplexer module RMUX and the "Utopiaport" UP on the high-frequency data bus DB issued.

FIG. 3b shows a schematic representation of the main functional units of the transmission module T of Multiplexereinrich tung MUX. The bus-specific transmit memory FIFO0,. . ., FIFO3 are each composed of m (eg m = 16) memory cells MEM1,. . ., MEMm together. Like the memory cells MEM1,. . ., MEMn of the bus-specific receive memory FIFO1,. . ., FIFO3, the memory cells MEM1,. . ., MEMm of the bus-specific memory FIFO1,. . ., FIFO3 a memory capacity of 64 bytes, so that per memory cell MEM1,. . ., MEMm a 53 byte ATM cell can be stored. Each memory cell MEM1,. . ., MEMm is divided into two parallel 32-byte partial memories TSP1, TSP2.

From the switching module X15 via the multiplexer device MUX to be transmitted to a subscriber line ATM cells are via the "Utopiaport" UP and the transmitter tiplexer module TMUX in one of the subscriber connection facilities  device associated memory cell MEM1,. . ., MEMm cached chert. The "Utopiaport" UP checks against that in the cell head the ATM cell stored information whether a currently emp catch 16-bit wide data word, a cell start defining SOC data word (Start Of Cell). Is that ak Data word received no SOC data word, it will previous data word below, to be filled in the currently memory cell MEM1,. . ., MEMm written. Is that up to date? Every data word is a SOC data word, becomes a new memory cell le MEM1,. . ., MEMn selected and the currently received data word stored in this. The ATM cells are included the clock rate specified by the switching module X15 DB_CLOCK in the bus-specific transmit memory FIFO0,. . ., FIFO3 written.

A cached ATM cell is sent to a subscriber closing device sent, a readout of the zwi cached ATM cell alternately in such a way that z. B. in the first partial memory TSP1 in the first place buffered byte 1 first, one in the second part store TSP2 in the first place buffered byte 2 second, one in the first partial memory TSP1 the first byte 1 subsequently buffered byte 3 as third, etc. via the associated transmission interface TP0,. . ., TP3 on the respective subscriber data bus TB0,. . ., TB3 is issued. The ATM cells are with the by the respective subscriber closing device predetermined clock rate TB_CLOCK on the Subscriber data bus TB0,. . ., TB3 issued.

Due to the reception and sen the memory FIFO0,. . ., FIFO3 implemented temporal decoupling the subscriber data buses TB0,. . ., TB3 from the high-frequency Da Each subscriber data bus TB0,. . ., TB3 with egg ner separate, through the respective subscriber connection direction specified, lower clock rate are operated. The more favorable cable properties achieved with this are possible  ben in turn compared to the high-frequency data bus DB Generously dimensioned length of the subscriber data bus TB0, . . ., TB3.

Fig. 4 shows a schematic representation of bus-individual transmit registers Tx_CLAV0,. . ., Tx_CLAV3 and a multiple xerindividual transmit register Tx_CLAV_STATUS of the Sendemo module T. Since the switching module X15 for addressing subscriber devices connected via subscriber line devices, a five-bit address information TxADD <0,. . ., 4 <provides for addressing 32 - corresponding to 2 ⁵ - subscriber devices, the registers stored in the multiplexer device MUK have 32 memory cells for storing subscriber-specific status information about the subscriber.

In each transmission interface TP0,. . ., TP3 is a bu are individual transmit register Tx_CLAV0,. . ., Tx_CLAV3, in which a recipient status information is stored with which those via the associated subscriber data bus TB0,. . ., TB3 addressable subscriber facilities are designated, can receive the data from the X15 circuit block. in the This embodiment can, for. B. the one about which he Most subscriber data bus TB0 with the address 1 and 26 adres user equipment that can be switched on stone X15 received.

The multi is located in the "Utopia port" UP of the transmitter module T. plexer-specific transmission register Tx_CLAV_STATUS, in which one Total recipient status information is stored with the those above all at the multiplexer MUX closed subscriber data buses TB0,. . ., TB3 addressable Subscriber facilities are designated, the data from the switch block X15 can receive. Those in the busindividu or transmit registers Tx_CLAV0,. . ., Tx_CLAV3 the participant da tenbuses TB0,. . ., TB3 deposited recipient status informa  tion is sent to the multiplexer indi via an OR link viduelle transmission register Tx_CLAV_STATUS forwarded and there saved. In the present embodiment, for. B. the over the subscriber data buses TB0,. . ., TB3 with the Address 1, 2, 14, 26 and 31 addressable subscriber devices received data from the X15 circuit block.

Are data to be transmitted between the switching block X15 between are stored by the switching module X15 Sequentially the memory cells of the multiplexer individual Transmit registers Tx_CLAV_STATUS after a positive total temp searched catcher status information, d. H. it is checked which subscriber facilities can receive data. Find the interconnection module X15 is a positive overall receiver status information and are in the interconnection module X15 data associated with this subscriber device If the switch-through module X15 transfers this data to the high-frequency data bus DB and simultaneously deletes the positive total recipient status information from the multiple x individual transmission register Tx_CLAV_STATUS and the ent speaking bus-specific transmission register Tx_CLAV0,. . ., Tx_CLAV3. The switch-through module X15 starts its search starting with the next memory cell of the multiplexerindivi duel transmission register Tx_CLAV_STATUS.

Analogous to the bus-specific transmission registers Tx_CLAV0,. . ., Tx_CLAV3 of the transmission module T has the reception module R busin individual receive register Rx_CLAV0,. . ., Rx_CLAV3. In every Receiver interface RP0,. . ., RP3 is a busindi vidual receive register Ex_CLAV0,. . ., Rx_CLAV3, in which a Send status information is stored with those via the assigned subscriber data bus TB0,. . ., TB3 adres sizable subscriber facilities are referred to Switch-through module X15 have data to be transmitted. Can FIFO0,. . ., FIFO3 data is cached, i. H. the busindividu  Receive memory FIFO0,. . ., FIFO3 have free memory memory capacities, the memory cells are sequentially egg nes bus-specific receive register Ex_CLAV0,. . ., Rx_CLAV3 searched for positive send status information, d. H. it is checked which participant facilities to transmit have telecommunications data. Finds the MUX multiplexer a positive send status information, the associated Data via the RP0 individual receiver interfaces, . . ., RP3 to the bus-specific receive memories FIFO0,. . ., FIFO3 transmitted and together with a send information, which identifies the sending subscriber device, between cached. The positive send status information will from the corresponding bus-specific receive register Ex_CLAV0,. . ., Rx_CLAV3 deleted. The multiplexer device MUX starts the search with the next memory cell of the bus-specific receive register Ex_CLAV0,. . ., Ex_CLAV3 away.

Can the switch-through module X15 receive data from a subscriber? received the device, it searches the individual bus Receive memory FIFO0,. . ., FIFO3 after one, by the send-in formation associated with this subscriber facility data. Finds the switch-through module X15 of the subscriber device Allocated data becomes this via the receive multiplexer modul RMUX and the "Utopiaport" UP on the high-frequency Da tenbus DB issued.

Fig. 5 shows a schematic representation of bus-individual address registers of the transmitter module T. In each transmit interface TP0,. . ., TP3 is a bus-specific LRU address register Tx_LRU0,. . ., Tx_LRU3 (Last Recently Used), in which an LRU address status information is stored, with which those via the assigned subscriber data bus TB0,. . ., TB3 are addressable subscriber devices which have requested data from the switching module X15 within a predetermined time period. After a predetermined period of time, for. B. 1 second, is in the bus-specific LRU address registers Tx_LRU0,. . ., Tx_LRU3 stored LRU address status information, bus-individual address register Tx_MATCH0,. Stored in the transmit arbitration device TA. . ., Tx_MATCH transferred. In the present embodiment, for. B. closed with the address 1 and 2 addressable subscriber devices via the subscriber data bus TB0 to the multiplexer device MUX. By transferring the LRU address status information into the bus-specific address registers Tx_MATCH0,. . ., Tx_MATCH ensures correct addressing of the subscriber devices, even with a changing configuration of the subscriber connection devices of the multiplexer device MUX.

The switch-through module X15 transmits data to a part subscriber device, the transmitted address information Tx_ADDR <0,. . ., 4 <of the subscriber device using busindi vidual address multiplexers ADDR_MUK0,. . ., ADDR_MUK3 with that in the bus-specific address registers Tx_MATCH0,. . ., Tx_MATCH3 compared stored address status information. The data is stored in the bus-specific transmission memory FIFO0,. . ., FIFO3 cached, whose assigned bu are individual address register Tx_MATCH0,. . ., Tx_MATCH3 a Entry for the transmitted address information Tx_ADDR <0,. . ., 4 <. In the present embodiment z. B. Data sent to the subscriber facilities with the Address 1 or 2 are to be submitted in the first Subscriber data bus TB0 assigned bus-specific sen cached FIFO0.

Claims (18)

1. ATM multiplexer device
which is connected on the one hand to a switching module (X15) via a high-frequency data bus (DB) and on the other hand to at least one subscriber connection device via at least one subscriber data bus (TB),
wherein the multiplexer device (NUX) a receiving module (R) for the transmission of data from a subscriber connection device to the switching module (X15) and a sensor module (T) for the transmission of data from the switching module (X15) to a subscriber connection device having,
wherein the receive module (R) and the transmit module (T) have a bus-specific memory (FIFO0,..., FIFO3) for each subscriber data bus (TB0,..., TB3),
whereby in the receiving module (R) data can be stored in a bus-specific memory (FIFO0 ... (DB_CLOCK) are readable,
and wherein in the transmitter module (T) data can be stored in a bus-specific memory (FIFO0,..., FIFO3) with the clock rate (DB_CLOCK) which can be predetermined by the switching module (X15) and with which the bus-specific memory (FIFO0, .., FIFO3) can be read out individually by the respective subscriber connection device predeterminable clock rate (TB_CLOCK). 2. Arrangement according to claim 1, characterized, that as a high-frequency data bus (DB) a 16-bit wide Da tenbus and as a subscriber data bus (TB) an 8-bit wide da tenbus is provided.   3. Arrangement according to one of the preceding claims, characterized, that the bus-specific memory (FIFO) FIFO memory (First In First Out). 4. Arrangement according to one of the preceding claims, characterized in
that the bus-specific memory (FIFO0,..., FIFO3) of the receiving module (R) are designed such that an implementation of the subscriber data bus (TB0,..., TB3) with a first data width on the high-frequency data bus (DB ) with a second data width,
and that the bus-specific memories (FIFO0,..., FIFO3) of the transmitter module (T) are designed such that a conversion of the high-frequency data bus (DB) with a second data width to a subscriber data bus (TB0,..., TB3 ) with a first data width. 5. Arrangement according to one of the preceding claims, characterized in
that the bus-specific memories (FIFO0,..., FIFO3) of the receiving module (R) each have a first number n of memory cells (MEM1,..., MEMn) "and
that the bus-specific memory (FIFO0,..., FIFO3) of the transmitter module (T) each have a smaller or identical second number m of memory cells (MEM1,..., MEMm) compared to the first number n. 6. Arrangement according to claim 5, characterized, that the memory cells (MEM1,..., MEMn; MEM1,..., MEMm) of the bus-specific memory (FIFO0,..., FIFO3) in this way are that in a memory cell (MEM1,..., MEMn; MEM1, . . ., MEMm) an ATM cell can be stored in each case.   7. Arrangement according to claim 5 or 6, characterized, that the memory cells (MEM1,..., MEMn; MEM1,..., MEMm) of the bus-specific memory (FTFO0,..., FIFO3) each in two same size, for storing q-bit wide data sequences designed partial memory (TSP1, TSP2) are divided. 8. Arrangement according to claim 7, characterized, that the memory cells (MEM1,..., MEMn) of an individual bus Memory (FIFO0,..., FIFO3) of the receiving module (R) for on save one via a subscriber data bus (TB0,..., TB3) received ATM cell are designed such that the on store alternately, so that successive q-bit wide data sequences of an ATM cell in different Chen partial memories (TSP1, TSP2) of the same memory cell (MEM1,..., MEMn) can be stored. 9. Arrangement according to claim 7, characterized, that the memory cells (MEM1,..., MEMm) of a bus-specific Memory (FIFO0,..., FIFO3) of the transmitter module (T) for reading out a stored ATM cell are designed such that the reading takes place alternately, so that in the two part save (TSP1, TSP2) saved q-bit-wide data sequences zen alternately from the first and the second partial memory (TSP1, TSP2) on the subscriber data bus (TB0,..., TB3) will give. 10. Arrangement according to claim 5 or 6, characterized in
that for receiving ATM cells at least one interface device (RP0,..., RP3; UP) for checking received data sequences with regard to the occurrence of egg, a cell start characterizing, stored in an ATM cell SOC information (Start Of Cell), where
in cases in which the currently received data sequence does not indicate a cell start, the data sequence can be stored in the memory cell to be filled (MEM1,..., MEMn; MEM1,..., MEMm),
and in cases in which the currently received data sequence indicates a cell start, a new memory cell (MEM1,..., MEMn; MEM1,..., MEMm) can be selected and the currently received data sequence can be stored therein. 11. Arrangement according to one of the preceding claims, characterized, that via a respective subscriber data bus (TB0,..., TB3) several on the with this subscriber data bus (TB0,..., TB3) connected subscriber connection device connected Subscriber facilities are addressable. 12. Arrangement according to claim 11, characterized, that the first sub-module (R) for each subscriber data bus (TB0,..., TB3) a bus-specific receive register (Ex_CLAV0,..., Ex_CLAV3), in which a send status-in formation is stored with those over them Subscriber data bus (TB0,..., TB3) addressable subscriber mer facilities are referred to, which are used for switching stone (X15) have data to be transmitted. 13. Arrangement according to claim 11 or 12, characterized, that the second sub-module (T) for each subscriber data bus (TB0,..., TB3) a bus-specific transmission register (Tx_CLAV, . . ., Tx_CLAV3), in which a recipient status informa tion is saved with which those about this participation mer data bus (TB0,..., TB3) addressable subscriber device the data from the circuit block (X15) can receive.   14. Arrangement according to claim 11 to 13, characterized, that the second sub-module (T) is a multiplexer individual Transmission register (Tx_CLAV_STATUS) has a total receiver status information is stored with which address over the subscriber data buses (TB0,..., TB3) cash subscriber facilities are designated, the data from Switch-through block (X15) can receive. 15. Arrangement according to claim 11 to 14, characterized, that the second sub-module (T) for each subscriber data bus (TB0,..., TB3) a bus-specific address register (Tx_MATCH0,..., Tx_MATCH3), in which an address status-in formation is stored, which identifies which part subscriber devices via this subscriber data bus (TB0,..., TB3) are addressable. 16. Arrangement according to claim 11 to 15, characterized, that the second sub-module (T) for each subscriber data bus (TB0,..., TB3) a bus-specific LRU address register (Tx_LRU0,..., Tx_LRU3), in which an LRU address status in formation is stored with those over the Subscriber data buses (TB0,..., TB3) addressable subscriber mer facilities are designated, of which within one predefined period of time ready to receive data for highly integrated circuit block X15 was signaled.   17. Arrangement according to claim 15 and 16, characterized, that the bus-specific LRU address registers (Tx_LRU0,..., Tx_LRU3) and the bus-specific address register (Tx_MATCH0,..., Tx_MATCH3) are coupled such that according to Ab run a predefinable period of time in the individual bus LRU address registers (Tx_LRU0,..., Tx_LRU3) stored LRU address status information in the assigned busindividu The address register (Tx_MATCH0,..., Tx_MATCH3) can be transferred is. 18. Arrangement according to claim 15, characterized, that the second sub-module (T) for each subscriber data bus (TB0,..., TB3) a bus-specific address multiplexer (ADDR_MUX0,..., ADDR_MUX3), which is configured in this way is that an address information transmitted with an ATM cell tion (Tx_ADDR <0,..., 4 <) with the address in the individual bus Address registers (Tx_MATCH0,..., Tx_MATCH3) stored addresses status information is comparable, so that the ATM cell egg nem bus assigned to the address information (Tx_ADDR <0,..., 4 <) individual memory (FIFO0,..., FIFO3) of the transmitter module (T) is assignable.